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STLD, UNIT III Assignment #3 FOR GIRLS

3.1) A PN flip-flop has four operations: clear to 0, no change, complement, and set to 1, when

inputs P and N are 00, 01, 10, and 11, respectively.

a) Tabulate the characteristic table.

b) Derive the characteristic equation.

c) Tabulate the excitation table.

Show how the PN flip-flop can be converted to a D flip-flop.

a) b)

P N Q(t+1)

0 0 0

0 1 Q(t)

1 0 Q′(t)

1 1 1

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3.3) Show how to build a J-K flip-flop using a T flip-flop and some combinational logic.

A J-K flipflop is a synchronous sequential circuit with two inputs (J and K) and one

state flip-flop (A). We design this from a state transition table.

Present

State

Next Flip-Flop

Input State Inputs

A J K A TA

0 0 0 0 0

0 0 1 0 0

0 1 0 1 1

0 1 1 1 1

1 0 0 1 0

1 0 1 0 1

1 1 0 1 0

1 1 1 0 1

To find TA look at the present state of A and the next state of A. If they are the same, the

flip-flop should not toggle (TA should be 0); if they are different, the flip-flop should toggle

(TA should be 1). We draw a three-input (A,J, K), one-output (TA) Karnaugh map:

TA = A J + AK

The circuit looks like this:

3.5) Explain the differences between ring and Johnson counters. Design and explain the

operation of a decade Johnson counters.

This circuit is a 5-bit Johnson counter used to implement a decade counter. The ring of 5 D

flip-flops is the Johnson counter. The Johnson counter output is used to generate 10 outputs;

each output goes high in turn.

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3.7) Realize D-FF and T-FF using JK-FF. Draw the logic diagrams with their truth tables.

Conversion of JK flip flop to T flip flop:

For the conversion of JK flip flop to T type of flip flop, T will be the external input

(input of combinational circuit) and the output of this combinational circuit is

connected to the inputs of actual flip flop (J and K).

Then we prepare a conversion table and using this table express J and K in terms of T

and Qn.

The conversion table, K-Maps and logic diagram for the conversion of JK flip flop to

T type of flip flop is shown below:

Logic Diagram Conversion Table K-Maps

Conversion of JK flip flop to D flip flop:

In case of converting JK flip flop into D flip flop, D is the external input of the

combinational circuit, whereas J and K are the inputs of the actual flip flop.

D and Qn make four combinations. So, prepare a conversion table and using this table

express J and K in terms of D and Qn.

The conversion table, K-map and logic diagram for the conversion of JK flip flop to

D flip flop is shown below:

K-Maps Conversion Table Logic Diagram

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STLD, UNIT III Assignment #3 FOR BOYS

3.2) Obtain the characteristic equations of JK, SR, D and T flip-flops. Also explain excitation tables of all

these flip-flops. (REFER TEXT BOOK or MY NOTES)

3.4) What is race around condition? How does it get eliminated in a Master–slave JK flip-flop?

(REFER TEXT BOOK or MY NOTES)

3.6) Design a 4-bit universal shift register and explain its operation?

(REFER TEXT BOOK or MY NOTES)

3.8) Explain the differences between ring and Johnson counters. Design and explain the operation

of a Ring counter.

(REFER TEXT BOOK or MY NOTES)

STLD, UNIT IV Assignment #4 FOR GIRLS

4.1) Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat. Use JK flip-flops.

Solution:

Step 1: Since it is a 3-bit counter, the number of flip-flops required is three.

Step 2: Let the type of flip-flops be RS flip-flops.

Step 3: Let the three flip-flops be A,B,C.

Step 4: The state table is as shown in Table 4.1.

Table 4.1: State table

Present State Next State

A B C A B C

0 0 1 0 1 0

0 1 0 1 0 1

1 0 1 1 1 1

1 1 1 0 0 1

Step 5: The next step is to develop an excitation table from the state table, which is shown in

Table 4.4.Table 4.2: Excitation table

Output State Transitions Flip-flop Inputs

Present State Next State

JA KA JB KB JC KC A B C A B C

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 1 0 1 1 X X 1 1 X

1 0 1 1 1 1 X 0 1 X X 0

1 1 1 0 0 1 X 1 X 1 X 0

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Step 6: Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh

maps in Tables 4.3–4.8 to derive a simplified Boolean expression for each flip-flop input.

Table 4.3 K-map for JA

Table 4.4 K-map for KA

Table 4.5 K-map for JB

Table 4.6 K-map for KB

Table 4.7 K-map for JC

Table 4.8 K-map for KC

From the K-maps, the following expressions for the J and K inputs of each flip-flop are

obtained:JA = JC = A’BC’; KA = ABC; JB = B’C+AC; KB = AC; KC = A’B’C

Step 7: The final step is to implement the combinational logic from the equations and connect

the flip-flops to form the sequential circuit. The complete logic of a counter is shown in Fig. 4.1.

Fig. 4.1 Logic diagram of a counter

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4.3) Design a one input, one output serial 2’s complementer. The circuit accepts a string of bits from

the input and generates the 2’s complement at the output. The circuit can be reset asynchronously

to start and end the operation.

2’s complement of a number can be obtained by keeping the least significant bits as such until the

first 1, and then complementing all bits. EXAMPLE : 001010 → 110110

The state diagram has two states: State A : Output = Input; State B : Output = Complement of

input;

DA= A + x; y = A ⊕ x;

State diagram of the design: Let A, B be the two states representing the output states of a D flipflop.

Implementation of the state diagram..

Input(x) Present State Next State D-Input Output

0 A = 0 A = 0 A = 0 0

0 B = 1 B = 1 B = 1 1

1 A = 0 B = 1 B = 1 1

1 B = 1 B = 1 B = 1 0

4.5) Derive the state table and the state diagram of the sequential circuit shown in Fig. Explain the

function that the circuit performs.

TA = A + B ; TB = A' + B;

A counter with a repeated sequence of 00, 01, 10.

Present State Next State Flip-flop Inputs TA TB A B A B

0 0 0 1 1 0 1 1

0 0 1 0 0 0 0 0

0 1 1 1 1 0 1 1

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4.7) Design an 11011 Sequence Detector circuit for Mealy machine (overlap sequence), draw the

state diagram using state table.

A. State A is the initial state. It is waiting on a 1. If it gets a 0, the machine remains

in state A and continues to remain there while 0’s are input.

B. If state B gets a 0, the last two bits input were “10”. This does not begin the

sequence, so the machine goes back to state A and waits on the next 1.

C. If state C gets a 1, the last three bits input were “111”. It can use the last two

of these 1’s to be the first two 1’s of the sequence 11011, so the machine stays

in state C awaiting a 0. We might have something like 1111011, etc.

D. If state D gets a 0, the last four bits input were 1100. These 4 bits are not part of

the sequence, so we start over, so the machine goes back to state A

E. If state E gets a 0, the last five bits input were 11010. These five bits are not part of the

sequence, so start over, so the machine goes back to state C.

Present State Next State / Output

X = 0 X = 1

A A / 0 B / 0

B A / 0 C / 0

C D / 0 C / 0

D A / 0 E / 0

E A / 0 C / 1

Each state has two lines out of it – one line for a 1 and another line for a 0.

STLD, UNIT IV Assignment #4 FOR BOYS

4.2) Design and explain an Asynchronous MOD-12 down-counter using j-k flipflop.

The modulus of a counter is the number of discrete states a counter can take up. A counter with n

no. of flip flops will have 2n number of possible states. So counters with modulus, for example, 2,

4, 8, 16, can be built up using 1, 2, 3, 4 flip flops. It is quite often desirable to construct a counter

having a modulus of 5, 9 or 12 etc. To design counters of modulus-12 (say), one has to use a

modulus 16 counter and to arrange the circuit in such a way that it skips some of its natural states

restricting it to12. The simplest way of doing this is the direct clearing method, where a gate circuit

is used to clear all the flip flops as the desired count is reached. Thus, for a modulus N counter,

the number n of flip-flops should be such that n is the smallest number for which 2n>N and then

to skip the surplus states with some rearrangements of the circuit.

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The circuit diagram for a Mod-12 counter is shown below. It is obvious that a mod-12 counter will

require 4 flip-flops which when connected as a counter, will provide 16 states. This counter counts

0, 1, 2, .., 15 and then it resets to 0. For a mod-12 counter, one may skip state 12 and return to

state 0 from state 11 and the cycle should continue this way. For this an additional combinational

logic circuit, i.e. a 4-input NAND gate is required, whose output is connected to clear terminal of

all the flip flops. This will feed a reset pulse to the counter during state 12 (1100) and immediately

after state 11 (1011).The flip-flops are reset and the counter starts counting again.

Clock Count

Output bit Pattern Decimal Value QD QC QB QA

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2

4 0 0 1 1 3

5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 1 0 1 0 10

12 1 0 1 1 11

13 Counter Resets its Outputs back to Zero

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4.4) A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z .

The flip-flop input equations and circuit output equation are

JA = Bx + B’y’ ; KA = B’xy’; JB = A’x; KB = A + xy’; z = Ax’y’ + Bx’y’

(a) Draw the logic diagram of the circuit.

(b) Tabulate the state table.

(c) Derive the state equations for A and B.

state table for the circuit :

Present State Input Next State Output

A B x A B z

0 0 0 1 0 1

0 0 1 1 1 1

0 1 0 1 0 0

0 1 1 1 0 0

1 0 0 0 0 1

1 0 1 0 1 1

1 1 0 1 0 1

1 1 1 1 0 1

corresponding state diagram:

4.6) Design a sequential circuit with two JK FFs A and B and two inputs E and x. If E=0, the circuit

remains in the same state, regardless of the value of x. When E = 1 and x = 1, the circuit goes

through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E = 1 and x

= 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01 and back to 00, and

repeats.

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PRESENT

STATE

INPUT NEXT

STATE

FLIP-FLOP INPUTS

A B E X A B JA KA JB KB

0 0 0 0 0 0 0 X 0 X

0 0 0 1 0 0 0 X 0 X

0 0 1 0 1 1 1 X 1 X

0 0 1 1 0 1 0 X 1 X

0 1 0 0 0 1 0 X X 0

0 1 0 1 0 1 0 X X 0

0 1 1 0 0 0 0 X X 1

0 1 1 1 1 0 1 X X 1

1 0 0 0 1 0 X 0 0 X

1 0 0 1 1 0 X 0 0 X

1 0 1 0 0 1 X 1 1 X

1 0 1 1 1 1 X 0 1 X

1 1 0 0 1 1 X 0 X 0

1 1 0 1 1 1 X 0 X 0

1 1 1 0 1 0 X 0 X 1

1 1 1 1 0 0 X 1 X 1

AB\Ex 00 01 11 10

00 01 11 10

0 0 0 1

0 0 1 0

X X X X

X X X X

JA = BEx + B’Ex ; KA = BEx + B’Ex’ ; JB = E; KB = E;

4.8) Design an 11011 Sequence Detector circuit for Moore machine (overlap sequence), draw the

state diagram using state table.

SIMILAR TO 4.7 EXCEPT OUTPUT INSIDE CIRCLE AND AN EXTRA STATE F.