Objectives: The objective of this experiment is to find out the characteristics of gates (Quad 2 AND, OR and NOT). After completing this experiment we will know: 1. About the AND, OR and NOT gates. 2. About the operation of AND, OR and NOT gates. 3. The characteristics of AND, OR and NOT gates. 4. About the truth table of AND, OR and NOT gates. 5. About the Boolean Expression of AND, OR and NOT gates. 6. We will know the Logic symbol of AND, OR and NOT gates. 7. We will know the IEEE symbol of AND, OR and NOT gates. 8. We will know the function diagram (circuit diagram) of AND, OR and NOT gates.

Theory: Gate: The element which performs logic function is called logic gate. 74LS32 (Quad 2 OR): The ‘OR’ gate is a circuit which will give a high output if one input is high. Logic symbol:

This OR gate has two inputs and one output terminal. IEEE Symbol:

Fig: IEEE Symbol of OR gate.

Fig: Function Diagram of 74LS32 (Quad 2 OR)

Objectives: The objective of this experiment is to find out the characteristics of gates (Quad 2 NAND, X-OR, NOR). After completing this experiment we will know:

1. About the NAND, X-OR, NAND, NOR gates. 2. About the operation of NAND, X-OR, NOR gates. 3. The characteristics of NAND, X-OR , NOR gates. 4. About the truth table of NAND, X-OR, NOR gates. 5. About the Boolean Expression of NAND, X-OR, NOR gates. 6. We will know the Logic symbol of NAND, X-OR, NOR gates. 7. We will know the IEEE symbol of NAND, X-OR, NOR gates. 8. We will know the function diagram (circuit diagram) of NAND, X-OR, NOR gates.

Theory:

Gate: The element which performs NAND logic function is called logic gate.

74LS00 (Quad 2 NAND): The ‘NAND’ gate is a circuit which will give a low output if both input is high. Logic symbol:

Fig: Symbol of NAND gate.

This NAND gate has two inputs and one output terminal.

Truth Table:

From this truth table we can see that ‘NAND’ gate will give a low (0) output if both inputs are high.

Boolean Expression:

Here Q is the output parameter and A, B is the input parameter. Functional Diagram:

Fig: Function Diagram of 74LS32 (Quad 2 NAND)

From the function diagram of NAND IC we can see that the IC has 14 pin NAND connection. Pin number 7 is of NAND ground connection and pin number 14 is NAND Vcc connection. Pin number 1 and 2 is NAND input and pin number 3 is output. This IC has 4 logic gates inside it.

Result: This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the 74LS00 which we attached to the Trainer. It gave me a better understanding of this chips.

Caution:

We have to very careful about the pin of this chip because they are very week. Also we have to careful about the connection of trainer board.

Discussion:

We should be careful when we connect the Ic chip. We compare the result with the truth table and the result was the expected. There are on error occurred.

74LS86 (Quad 2 X-OR): The ‘X-OR’ gate is a circuit which will give a low output if both input is same bit.

Logic symbol:

Fig: Symbol of X-OR gate.

This X-OR gate has two inputs and one output terminal.

Truth Table:

From this truth table we can see that ‘X-OR’ gate will give a high (1) output if input is same bit.

Here Q is the output parameter and A, B is the input parameter.

IEEE SYMBOLS:

Functional Diagram:

Fig: Function Diagram of 74LS86 (Quad 2 X-OR)

From the function diagram of X-OR IC we can see that the IC has 14 pin for connection. Pin number 7 is for ground connection and pin number 14 is for Vcc connection. Pin number 1 and 2 is for input and pin number 3 is output. This IC has 4 logic gates inside it. Result:

This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the 74LS86 which we attached to the Trainer. It gave me a better understanding of this chips.

74LS02 (Quad 2 NOR): The ‘NOR’ gate is a circuit which will give a high output if both inputs are low.

Logic symbol:

Fig: Symbol of OR gate.

This NOR gate has two inputs and one output terminal.

IEEE SYMBOLS:

Truth Table:

From this truth table we can see that ‘NOR’ gate will give a high (1) output if both inputs are low.Boolean Expression:

Here Q is the output parameter and A, B is the input parameter.

Functional Diagram:

Fig: Function Diagram of 74LS02 (Quad 2 NOR)

From the function diagram of OR IC we can see that the IC has 14 pin for connection. Pin number 7 is for ground connection and pin number 14 is for Vcc connection. Pin number 1 and 2 is for input and pin number 3 is output. This IC has 4 logic gates inside it. Result:

This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the 74LS02 which we attached to the Trainer. It gave me a better understanding of this chips.

Caution:

We have to very careful about the pin of this chip because they are very week. Also we have to careful about the connection of trainer board. Discussion:

We should be careful when we connect the Ic chip. We compare the result with the truth table and the result was the expected. There are on error occurred.

Objectives: The objective of this experiment is to find out the characteristics of gates (Quad 3 NAND, AND). After completing this experiment we will know:

1. About the NAND, AND gates. 2. About the operation of NAND, AND gates. 3. The characteristics of NAND, AND gates. 4. About the truth table of NAND, AND gates. 5. About the Boolean Expression of NAND, AND gates. 6. We will know the Logic symbol of NAND, AND gates. 7. We will know the IEEE symbol of ANAND, AND gates. 8. We will know the function diagram (circuit diagram) of NAND, AND gates.

74LS10 (Quad 3 NAND):

The ‘NAND’ gate is a circuit which will give a low output if all inputs are high.

Logic symbol:

Fig: Symbol of 3-input NAND gate.

This NAND gate has three inputs and one output terminal.

Truth Table:

From this truth table we can see that ‘NAND’ gate will give a low (0) output if three inputs are high. Boolean Expression:

Here Q is the output parameter and A, B, C is the input parameter.

Functional Diagram:

Fig: Function Diagram of 74LS10 (Quad 3 AND)

From the function diagram of OR IC we can see that the IC has 14 pin for connection. Pin number 7 is for ground connection and pin number 14 is for Vcc connection. Pin number 1, 2 and 13 is for input and pin number 12 is output. This IC has 3 logic gates inside it.

Result:

This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the 74LS10 which we attached to the Trainer. It gave me a better understanding of this chips.

74LS11 (Quad 3 AND):

The ‘AND’ gate is a circuit which will give a low output if all inputs are high.

Logic symbol:

Fig: Symbol of AND gate.

This AND gate has three inputs and one output terminal.

Truth Table:

From this truth table we can see that ‘AND’ gate will give a high (1) output if all inputs are high.

Boolean Expression:

Here Q is the output parameter and A, B,C is the input parameter.

Functional Diagram:

Fig: Function Diagram of 74LS11 (Quad 3 AND)

From the function diagram of OR IC we can see that the IC has 14 pin for connection. Pin number 7 is for ground connection and pin number 14 is for Vcc connection. Pin number 1, 2 and 13 is for input and pin number 12 is output. This IC has 3 logic gates inside it. Result: This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the 74LS11 which we attached to the Trainer. It gave me a better understanding of this chips.

Objectives:

The objective of this experiment is to find out the implementation of X-NOR operation using basic gates.

Theory:

The Exclusive-NOR Gate function or Ex-NOR for short, is a digital logic gate that is the reverse or complementary form of the Exclusive-OR function we look at in the previous tutorial. Basically the “Exclusive-NOR Gate” is a combination of the Exclusive-OR gate and the NOT gate but has a truth table similar to the standard NOR gate in that it has an output that is normally at logic level “1″ and goes “LOW” to logic level “0″ when ANY of its inputs are at logic level “1″.

However, an output “1″ is only obtained if BOTH of its inputs are at the same logic level, either binary “1″ or “0″. For example, “00″ or “11″. This input combination would then give us the Boolean expression of:

Simplified Equation:

Truth Table:

Circuit Diagram:

Apparatus:

1. 74LS32 (1 piece)2.74LS08 (1 piece)3. 74LS04 (1 piece)4. Connecting Wire5. Bread Board etc.

Result :

This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the ICs which we attached to the Trainer. It gave me a better understanding of this chips.

Match the result with corresponding truth table.

Study of universality of NAND & NOR gates

Objectives:

Implements basic gates with universal gates.

he objectives of this lesson are to learn about:

1. Universal gates - NAND and NOR.2. How to implement NOT, AND, and OR gate using NAND gates only.3. How to implement NOT, AND, and OR gate using NOR gates only.4. Equivalent gates.5. Two-level digital circuit implementations using universal gates only.6. Two-level digital circuit implementations using other gates.

Theory:

We have discussed about different types of logic gates in previous articles. Now coming to the topic of this article we are going to discuss about the Universal Gate. AND, NOT and OR gates are the basic gates; we can create any logic gate or any Boolean expression by combining them. Now NOR and NAND gates have the particular property that any one of them can create any logical Boolean expression if designed in a proper way. Now we will look at the operation of each gate separately as universal gates.

NOR Gate as a Universal Gate

The NOR gate is also used as a Universal Gate as the NOR Gate can be used in a combination to perform the function of a AND, OR and NOT gates.

NOT Gate Implementation

A NOT gate can be implemented using a NOR gate by connecting both the inputs of the NOR gate together. By connecting the two inputs together, the combinations with dissimilar inputs become redundant. The Function Table of the 2-input NOR Gate reduces to that of the NOT gate.

OR Gate Implementation

A NOR Gate performs the OR-NOT function. Removing the NOT gate at the output of the NOR gate results in an OR gate. The effect of the NOT gate at the output of the NOR gate can be canceled by connecting a NOT gate at the output of the NOR Gate. The two NOT gates cancel each other out. A NOT Gate implemented using a NOR gate (2) is connected to the output of a NOR gate (1).

AND Gate Implementation

An AND Gate can be implemented using a combination of three NOR gates. The implementation is based on the alternate symbolic representation of the AND gate. The AND gate is represented as an OR gate with bubbles at the inputs and outputs. The two bubbles at the input can be replaced by two NOT gates (1) & (2) implemented using two NOR gates. If the two bubbles are removed from the two inputs, the OR gate with the bubble at the output represents a NOR gate (3).

NAND Gate as a Universal Gate

The NOR gate is also used as a Universal Gate as the NOR Gate can be used in a combination to perform the function of a AND, OR and NOT gates.

NOT Gate Implementation

This is the circuit diagram of a NAND gate used to make work like a NOT gate, the original logic gate diagram of NOT gate is given beside.

OR Gate Implementation

The above diagram is of an OR gate made from combinations of NAND gates, arranged in a proper manner. The truth table of an OR gate is also given beside the diagram. Now we will see the design of an AND gate from NAND gates.

AND Gate Implementation

The above diagram is of an AND gate made from NAND gate. So we can see that all the

three basic gates can be made by only using NAND gates, that’s why this gate is called Universal Gate and it is appropriate.Result:

This lab illustrated the uses of circuits, chips, and gave a physical representation of the digital logic which I have been learning about in class. It taught me the uses of the Trainer board along with the 74LS00 which we attached to the Trainer. It gave me a better understanding of this chips.

Match the result with truth table.

To design and implementation of parity generator and parity checker

Theory:

Parity Generation and Checking:

A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker.

In even parity the added parity bit will make the total number of 1’s an even amount and in odd parity the added parity bit will make the total number of 1’s an odd amount.In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission.

Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. An error occurs during the transmission if the four bits received have an even number of 1’s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1’s. The circuit that generates the parity bit at the transmitter side is called a parity generator. The circuit that checks the parity at the receiver side is called a parity checker.

The three bits, X, Y, and Z, constitute the message and are the inputs to the even parity generator circuit whose output is the parity bit P.

For even parity, whenever the message bits (X, Y& Z) have an odd number of 1’s, the parity bit P must be 1. Otherwise, P must be 0. Therefore, P can be expressed as a three-variable exclusive-OR function: P = X Y Z ⊕ ⊕

RESULT:The design of the three bit even Parity generator and checker circuits was done and their truth tables were verified.