soldier systems center mit lincoln laboratory darpa darpa - mto 3d circuit integration technology...

Soldier Systems Center

MIT Lincoln Laboratory

DARPADARPA

DARPA - MTO

3D Circuit Integration Technology for Multiproject Fabrication

Program Kickoff

7 April 2000

L-325, MIT Lincoln Laboratory

IntroductionOriginal Program Review

New Program EffortLisa McIlrath 8:30-10:00

Break and Camera Demonstration

Advanced Photodiode Development:

150mm Wafer Transfer Effort:

Purchase of Wafer Aligner/Bonder:

3-D Via Topologies:

Introduction: New Lincoln Effort:

Schedule:

James Burns 10:45-11:00

Keith Warner 11:00-11:15

Craig Keast 10:30-10:45

Craig Keast 11:50-12:00

Peter Wyatt 11:30-11:50

Andy Loomis 11:15-11:30

Lunch and Discussion: All 12:00-1:00



DARPADARPA

DARPA - MTO

3D Circuit Integration Technology for Multiproject Fabrication

TREX Enterprises:

System Integration

New Research in 3D Architectures and Systems

Break and Camera Demonstration

New Program Overview:

High Resolution Camera Design:

Summary of Prior Results:

Algorithms for Activity Detectionwith 3D Sensors:

Lisa McIlrath 9:00-9:30

Steve Hawley 9:30-9:50

Lisa McIlrath 8:40-9:00

Victor Lum 9:50-10:05



DARPADARPA

DARPA - MTON1 Test Reticle Layout



DARPADARPA

DARPA - MTON1 3D Photodiode Active Pixel

• 10m via• 32m x 37m pixel area



DARPADARPA

DARPA - MTO3D Transfer/Via SEMs - 9/98

Deep and shallow 10m vias - top view



DARPADARPA

DARPA - MTO

Via chainsSample 13-18 B die R3C3 0.01V@100uA comp.

0

500

1000

1500

2000

2500

3000

0 100 200 300 400 500 600

# of vias

Re

sis

tan

ce

6 um deep vias

10um deep vias

6um shallow vias

10um shallow vias

N1 Via Chain Measurements - 9/98



DARPADARPA

DARPA - MTON1 Diode Measurements - 9/98Spectral Response of Native and Pwell Diodes

Illuminated Through Backside

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

400 500 600 700 800 900 1000

Wavelength (nm)

Qu

antu

m E

ffic

ien

cy

Native

Pwell



DARPADARPA

DARPA - MTON2 Test Reticle Layout



DARPADARPA

DARPA - MTO

6 m via on 150mm wafer -- 7/23/99

Adhesive

Oxide

Aluminum



DARPADARPA

DARPA - MTOPhotomicrograph of Imager

Metal-1 Pad 3D Via



DARPADARPA

DARPA - MTO

N2 2D & 3D Ring Oscillator Measurements

2D and 3D Ring Oscillator Stage DelayL=1 m, W=6, 9 m (N,PFET)

1.00E-10

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

0 1 2 3 4 5 6

Vdd (Volts)

De

lay/

Sta

ge

(s) 2D 33 Stages

2D 65 Stages

3D 17 Stages

3D 33 Stages

3D 65 Stages



DARPADARPA

DARPA - MTOFirst 3D 64x64 Imager Results - 9/99

Dark Image Room Light Bright Light



DARPADARPA

DARPA - MTONU - LL 3D Technology Transfer

• Wafer-to-wafer bonding process under development at Lincoln Laboratory

• Traveller of NU 3D process delivered to Lincoln• Complete devices from North 3 and 4 runs• Transfer Keith Warner to Lincoln - (task completed)



DARPADARPA

DARPA - MTO3D Pixel Design: Free-Running

Sampled Oscillator

1 0 0 0 0 01 1 1

CLK

t

(xmax/x) .

x max

.

A

B

V

V < B ?

A

Iph

V



DARPADARPA

DARPA - MTO3D & 2D Pixel Layouts

MOSIS HP 0.5m process30m x 30m pixel

3D SOI-CMOS 0.8m process2-layer 45m x 45m pixel



DARPADARPA

DARPA - MTOCircuits / Systems Design Status

Pixel-Parallel A/D Imager Design -- Tests / Design Revs Complete

40nW / pixel @ 3.3V, 0.1% Residual Fixed Pattern Noise

64x6448x48



DARPADARPA

DARPA - MTOCircuits / Systems Design Status

3rd Layer Design Taped Out 11/1/99

• On-chip VCO with 216 (65536) bit range• On-chip pixel-parallel 1st stage low pass filtering• Programmable resolution / dynamic range



DARPADARPA

DARPA - MTOCircuits / Systems Design

Systems Environment

• Camera demo system modified for 256 x 256 imager compatibility and interface upgrade

• Research in future smart sensor designs:– Video tracking demo (V. Lum, M-Eng thesis)

– Video feedback control architectures (A. Aina, PhD thesis)



DARPADARPA

DARPA - MTO

Testbed DemonstrationCamera System

(Demo Setup in Office)



DARPADARPA

DARPA - MTOActivity Monitoring

Current image Background model Detected objects

MIT Artificial Intelligence Laboratory

Object Tracking Using Adaptive Background Mixture Models

Courtesy Chris Stauffer & Eric Grimson



DARPADARPA

DARPA - MTOAnalog Memory with Digital

Feedback

PixelOscillator

Phase-frequencydetector Change

detector

Adaptive memory

Voltage-ControlledOscillator

A-DataStore

ChargePump



DARPADARPA

DARPA - MTOMultimode memory module

Pixel Input F.D.

VCO Charge Pump

Monitor

F.D.

VCO Charge Pump

Monitor

enable

active

enable

active

Problem: VCO tracks new values faster than monitor detects them



DARPADARPA

DARPA - MTOCompensated Memory

F.D.

VCO Charge Pump

enable

activePixel InputFilter

Solution: Integrate a low pass filter into the loop



DARPADARPA

DARPA - MTOCreating the Filter

F.D.

VCO Charge Pump

enable

active

Pixel Input

Edge Counter

Edge Counter

Edge Counter

reset

reset

reset

CompareLogic



DARPADARPA

DARPA - MTODetecting Activity

Pixel Bitstream

VCO output

Input frequencychange

Second unmatched edge

Activity is determined by the temporal distance between pairs of unmatched edges



DARPADARPA

DARPA - MTO

• Better circuit / interconnect ratio • “Unrestricted” vertical interconnections between layers• Low digital system power: P=CV2f

The Enabling Technology

High Bandwidth-Processors

Mixed MaterialSystem Integration

LargeFocal Planes

Exploiting DifferentProcess Technologies

AdvancedImaging Technologies

SOI CMOS

3D



DARPADARPA

DARPA - MTOPath to Industrialization

Phase I: Infrastructure DevelopmentPhase II: Small Volume 3D Processing

Center for Multi-Project RunsPhase III: High Volume Manufacturing

• Industry-Standard State-of-the-Art SOI/CMOS Process• Automated Wafer Align / Bonding / Interconnect Patterning

Goals:



DARPADARPA

DARPA - MTOPhase I Plan (25 months)

• Process Development– 0.8m SOI/CMOS 0.18, 0.25 m FDSOI– Reliable low temperature oxide bonding– High aspect ratio Tungsten plug fill

• Systems Development– High Definition Imager Platform– 3D-compatible near-IR imaging technique– 3D CAD tools packaging



DARPADARPA

DARPA - MTO

Systems Design Schedule



DARPADARPA

DARPA - MTO0.25m FDSOI Test Pixel

14m x 14m (or less)



DARPADARPA

DARPA - MTOHigh-Resolution Near-IR Imager

• Explore best method for III-V incorporation with automated 3D process technology– Proposal accepted from C. Fonstad, MIT, for selective

InGaAs in Si growth• Initial photodiode array lots for investigation• Imager design unchanged• Compatible with basic platform systems demo



DARPADARPA

DARPA - MTO3D CAD Tools

• Develop minimal toolset for 3D cell layout, design rule checking, netlist extraction

• Interface with commonly available tools, e.g., Magic, L-Edit, Spice

• Platform independent• Remove major obstacle for new users in Phase II• Plan:

– Build on prior work developed on Cadence tools– Negotiate distribution agreement with Si-valley software vendor(s).



DARPADARPA

DARPA - MTO

High Definition Imager Platform

• Interface 3D camera with SXGA (1024x1280) display• Identify military users• Human factors issues

soldier systems center mit lincoln laboratory darpa darpa - mto 3d circuit integration technology...

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