micro nano michigan-km-abc2-jmnano-microworkshop.com/proceedings/slides/kaiser_matin.pdf ·...

Micro/Nano Manufacturing Workshop - Michigan

Dr. Avram Bar-Cohen, PM, DARPA/MTO Dr. Kaiser Matin, System Planning Corporation

Dr. Joseph Maurer, Booz Allen Hamilton

5/22/2013

Micro and Nano Technologies for Enhanced Thermal Management of Electronic Components

Distribution Statement A, Approved For Public Release, Distribution Unlimited

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•  Introduction •  Thermal Packaging History/Trends •  DARPA’s Thermal Packaging Program •  TMT Summary •  TGP, NTI, NJTT, Advanced Studies

•  DARPA’s ICECool Program •  Limitations of Remote Cooling •  ICECool Overview •  ICECool Fun – Goals •  ICECool Apps - Goals

•  Wrap Up

Introduction and Overview


MTO leverages, counters, and transcends COTS creating an Unlevel Playing Field

The DARPA/MTO Vision

Distribution Statement A, Approved For Public Release, Distribution Unlimited 3

ü  Leverage COTS: Multiply power of COTS by aggregating, adapting and integrating components into networks and systems which benefit the warfighter

ü  Counter COTS: Defend against threats emerging from sustained advancements of cheap (i.e. consumer price-point), readily available technologies

ü  Transcend COTS: Develop high-risk, high-reward technologies outside and beyond the scope of commercial industry

Generation/Eras of Thermal Packaging

Generation 1 - HVAC: 1945-1975 •  ENIAC, IBM Mainframes •  Telephone switching equipment •  Vacuum tubes and early solid-state

transistors •  Goal: Remove heated air

from room/rack/cabinet

Generation 2 - Rack Cooling: Ø  Air Cooling Era1975-1985

•  DIP’s and SMT’s on PCB’s •  PCB’s in Card Cages •  Goal: Maximize natural and

forced convection cooling in racks

IBM Mark I Mainframe (1950's)


IBM 360 Card Cage (1982)

Generations/Eras of Thermal Packaging

Ø  Liquid/Refrig Cooling Era:1980-1990 •  Maturation of bipolar devices: ~5W Chips,

~300W Multi Chip Modules •  Honeywell, IBM, CDC, Hitachi, NEX, Fujitsu,

….mainframes/supers •  Goal: Gain control over the local

“coldplate,” “cold bar” temperature

Ø  Air Cooled Heat Sinks Era: 1985-2000 •  Thermally-engineered heat sinks for CMOS

microprocessors •  Miniaturized servers create Data Center

cooling challenge •  Goals: Reduce “case-to-air” resistance

for chip package

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Fujitusu - 8CPU 470x580x80

1600W Airflow～3.5 m/s

IBM 3081


High Power

Thermal Packaging “Triple Threat”

heat spreader

chip carrier

heat sink

heat sink

Hot Spots

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Nanoelectronics Era 2000 - :

•  GHz-level CMOS with features below 100 nanometers •  Power dissipation increasing, distinct on-chip “hot spots” on

silicon/compound semiconductors •  Emergence of homogeneous/heterogeneous “chip stacks”

denying access to back of chip for “thermal solution” Thermal Management Goals:

Remove large flux Reduce/eliminate on-chip “hot spots” Extract high heat density

3-Dimensional


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DARPA Thermal Management Programs

Heat Removal by Thermo-Integrated Circuits (HERETIC) •  1998: DARPA PM Towe •  2001: DARPA PM Radack •  2002: HERETIC ends

Micro Cryo Coolers (MCC) •  2006-2011: DARPA PM Dennis Polla

Technologies for Heat Removal in Electronics at the Device Scale (THREADS) •  2005-2006: DARPA PM Rosker •  2009-present: DARPA PM Albrecht

ACM MACE NTI

TGP

98 00 04 06 08 10 12

TMT

MCC

THREADS

THREADS

Thermal Management Technologies (TMT) •  2007-2010: DARPA PM Kenny •  2010-present: DARPA PM Bar-Cohen

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Embedded Cooling (NJTT and ICECool)

•  2011 - 2015: DARPA PM Bar-Cohen •  NJTT and ICECool explore epitaxy transfer to diamond,

microfluidics, thermal interconnects, thermal co-design

Exploratory Studies ‘98-’07 Remote Cooling ’07-’12 Embedded Cooling ’12 -


NJTT ICECool Fun

ICECool Apps

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Thermal Management Technologies Program (TMT)

Goals: Reduce each resistance in the heat flow path to remote coolant with nanostructured materials, active structures, and integrated manufacturing

MACE Goal: Base Resistivity = 5 cm2K/W; COP = 20

NTI Goal: Interface Resistivity = 0.01 cm2K/W

GE: Copper Nanosprings

TGP Goal: Thermal conductivity =

10,000 W/mK – 20,000 W/mK

Raytheon: Patterned CNTs on Cu wick

Heat Sink (MACE)

TIM (NTI)

Chip Junction (NJTT)

Spreader (TGP)

TEC (ACM)

ACM Goal: COP=2 ΔT=15oC for q”=25W/cm2

UTRC: Thin-film superlattice materials

MIT: 3D vapor chamber; fan/fin

integration


Vision : A new 2-D, thin, lightweight MCM substrate incorporating modern and nanostructured materials to achieve vastly superior thermal conduction & possessing all mechanical properties necessary for hard-mounting ICs.

Heat Sources

Flexible, CTE-matched Casing

Nanostructured Wick Vapor Cavity

Thermal Ground Plane (TGP)

5/29/13 9

TGP Goals •  Extreme lateral thermal conduction, 100X above current MCM substrates •  Large 2-D area, <1 mm thick, Operation up to 20g •  Nanostructured wick for enhanced heat transfer and fluid transport •  Structural, flexible, thin, & light-weight materials that match the CTE of Si, GaAs, or GaN •  2-phase heat transfer to eliminate load-driven thermal non-uniformity across substrate

Approved for Public Release, Distribution Unlimited

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TGP Approaches and Performance

U Colorado: flexible/conformal case with Cu nanomesh wick

UC Berkeley: two phase flow with coherent porous

silicon wick

UC Santa Barbara: large scale titanium TGP

UCLA: metallic powder + biporous wick/posts

Teledyne: CNT/Si wick

structures

GE: nanostructured super hydrophobic/philic wick

Northrop Grumman: SiC oscillating heat pipe

Raytheon: Patterned CNTs on

Cu wick


Typical thickness: 2~4 mm, Area: 9 ~ 300 cm2

•  TIM Resistance – thermal bottleneck in all DoD systems.

•  TMT Success requires x10 reduction in TIM Resistance

•  Success in TGP and MACE will shift focus to this layer.

•  Existing solutions (grease, epoxy, solder, In) Limit allowable chip heat dissipation

TGP

MACE

Thermal Interface Material (TIM)

5/29/13 11

NTI Goals: •  Lower Thermal Resistance (0.1 cm2 C/W typical. 10x reduction in NTI ~ 0.01 cm2 C/W)


Nano Thermal Interface (NTI)

NTI Sample Evaluation (NREL) 10 mm x 10 mm Samples •  Samples were received from three teams: Georgia Tech, Teledyne, and GE •  TIM stand and xenon flash equipment characterized thermal resistances of the

materials –  Results vary due to the point measurement technique of the xenon flash and the

averaging technique of the TIM stand –  Uncertainty is present in material properties needed for diffusivity calculations

(α=k/ρcp) for xenon flash

Typical thickness: 0.01 mm ~ 1 mm, Area: ~ 1 cm2

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Remote cooling paradigm: Heat rejection to a remote fluid involving thermal conduction and spreading in substrates across multiple material interfaces with associated thermal parasitics

Limitations of Remote Cooling Heat

•  Accounts for a large fraction of SWaP-C of advanced high power electronics, lasers, and computer systems

•  Stymies attempts to port advanced systems to small form-factor applications •  Frustrates attempts to reach SWaP-C targets for electronic systems

Limitations:

•  Incapable of effectively limiting the device “junction” temperature rise •  Can not selectively target the thermally-critical devices •  Can not extract heat efficiently from 3D package


Towards Gen3 Thermal Packaging

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Challenges: •  Complete the Inward Migration of Thermal Packaging •  Extract heat directly from device, chip, and package •  Place thermal management on an equal footing with functional design and

power delivery

Benefits: •  Allow electronic systems to reach material, electrical, optical limits •  Reduce SWaP-C for comparable performance •  Lead the way to integrated, intelligent system co-design

Enabling Technologies: •  Microfluidics – convective and evaporative •  Thermal interconnects – active/passive •  Microfabrication – channeling, hermeticity •  Thermal Co-Design

Integrated

microchannels with

evaporative flow

Coolant

In

Coolant

Out

Solder

Bumps

Thermal

Vias

Microvalve


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Liquid Cooling Team: General Electric Challenge: • Eliminate impact on device electrical properties due

to time varying dielectric constant of liquid

High Thermal Conductivity Diamond Teams: TriQuint, BAE, Raytheon, RFMD, NGAS Challenges: •  Integrate lattice-mismatched heat spreaders • Minimize thermal boundary resistance (TBR) • Match coefficient of thermal expansion of electronic material

Substrate

Drain

Gate

Source

Electronic Junction

Near-Junction Thermal Transport (NJTT)

NJTT Vision: Provide localized thermal management within 100 µm of the device substrate to increase Output Power from GaN PAs by >3x

DARPA’s Near-Junction Thermal Transport (NJTT) is an effort inside DARPA’s Thermal Management Technology (TMT) portfolio •  Start Date: Fall 2011 •  Teams: TriQuint, BAE, Raytheon, RFMD, NGAS, GE

NJTT Approaches

Schematic of NJTT HEMT Device


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BAE Group4, Stanford, IPG, IQE

TriQuint Group4, Bristol, Lockheed Martin

RFMD Group4, Stanford, Georgia Tech, Boeing

Raytheon Group4, Stanford, Georgia Tech

GE RFMD

Diamond

GaN

GaN

Al based Transition

Layer

Silicon

Diamond

Raytheon Approach: Diamond Substrate

achieves 3-5x reduced thermal resistance

TriQuint Approach: Remove Si substrate and transition/buffer layers and bond

diamond to AlGaN/GaN layers at optimized distance from device channel

RFMD Approach: Remove transition layers, employ super-thin adhesive between GaN and Diamond, GaN thinned to sub 1 µm GE Approach: Cooling through

autonomous fluid routing via shape-memory alloy valves

BAE Approach: High thermal conductivity diamond bonding at low temperatures (<200°C) on thinned GaN to minimize

impact of CTE mismatch on device performance and reliability

NGAS NRL, ADI, Stanford

NGAS Approach: Utilize high k diamond vias in

etched GaN on SiC


NJTT Approaches to 3X

Die area ~ 1.1 ~ 4.3 mm2

Die thickness ~ 0.1 mm

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Smaller drop volumes with higher frequency à Thinner liquid films à Higher heat transfer

Concept Embedded Thermal Management using EWOD DMF (You, UT-Dallas)

q  Evaporative microfluidics is following the Moore’s law q  Nano-manufacturing is taking off q  Potential embedded cooling on-a-chip thermal management q  No pumps required q  SWaP-C alignment with DoD needs

Courtesy: S.M. You , Professor of Mechanical Engineering Associate Department Head, Mechanical Engineering, UT Dallas.

3D cross section of embedded cooling (Georgia Tech)

5/29/13 18

a) Conventional Air Cooling Technology b) Integrated microfluidic technology c) On demand microfluidic cooling technology

3D Stacked Microfluidic Cooling for High-Performance 3D ICs Yue Zhang, Ashish Dembla, Yogendra Josh, Muhannad S. Bakir School of Electrical & Computer Eng., School of Mechanical Eng., Georgia Institute of Technology, Atlanta, USA [email protected]

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ICECool Technologies and Challenges

Thrust 1: Integrated Microfluidics & Thermal Interconnects

Thrust 2: Thermal Co-Design

Evaporative Microfluidic Cooling

Thermal Vias and Integrated TECs

Microchannels and Microvalves

Design of ICECool Active Chips

Evaporative Microchannel Flow

Serizawa and Feng (2001)

Thin-film Thermoelectrics

Integrated high k vias

Challenges:

•  Highly conductive thermal vias •  k > 1000 W/mK •  n > 1000 temp cycles

•  TECs for hot spot cooling

•  ΔT < 5 0C rise •  CoP > 2.5 •  n > 1000 temp cycles

Challenges: •  > 90% vapor in exiting flow •  ΔT < 5 0C across chip •  CoP > 30 (Coefficient of

Performance)

•  Pressure drop < 10% Psat

SiC Microchannels

MEMS Valves

Challenges: •  Walls, channels in SiC and

diamond •  < 50 micron thick •  >10:1 aspect ratio

•  Microvalves: •  10% to 90% control of

maximum flow •  n > 1000 temp cycles

ICECool Design Schematic

Challenges: •  Evaluate impact of ICECool

techniques on device performance

•  Optimize placement and efficiency of thermal and electronic/RF features

•  Achieve 10x in MMIC and microprocessor performance

CoP is defined as the ratio of heat removed to the power required to deliver the cooling.

Balandin (1999)

Source: Nextreme

Source: Texas Tech

Carter et al(2009)


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ICECool Fundamentals (ICECool Fun)

Intrachip: Flowing cooling fluid through microchannels fabricated directly into the chip

Interchip: Flowing cooling fluid through the microgap between chips in 3D stacks

Program Objective: Provide the fundamental thermofluid building blocks for the utilization of Intra and Interchip evaporative cooling in DoD electronics


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ICECool Applications (ICECool Apps)

Conceptual ICECool Apps Wafer

Program Objective: ICECool Apps will enhance the performance of RF MMIC power amplifiers and embedded high performance computing systems

through the application of chip-level heat removal with kW-level heat flux and heat density with thermal control of local submillimeter hot spots.


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Thank You !!!


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