SoC, PSoC, & SoPC Design

J. Hamblen

SoC, PSoC, & SoPC Design

Design a single chip solution Recent option for Embedded Systems System on a Chip (SoC) – one chip replaces a embedded system board System on a Programmable Chip (SoPC) is an SoC that uses a large FPGA Intellectual Property (IP) cores are used to provide processors and common hardware for SoPC designs. IP cores are drop in design elements purchased from another vendor

eBox 2300- SoC Embedded PC

eBox 2300 – SoC example

Same I/O features as a standard PC motherboard Uses a Vortex 86 SOC X86 Processor Motherboard Chipset is in the Processor chip Boots from Flash memory – Notebook disk optional No cooling fan needed and small size 4.5 by 4.5

inch X86 processor is slower than PC’s processor Low cost $150 and runs Windows XP and CE Used in ECE 4180, several 4007 design projects

and Windows Embedded student design contest

SoC ASIC Design

Design an single chip Application Specific Integrated Circuit (ASIC) solution for the product

ASIC Advantages Faster clock speed Lowest cost for very high volume parts

1,000,000 transistors for <$.25

ASIC Disadvantages

Long lead time to develop an ASIC Several months or perhaps years Requires complex Legal Agreements with ASIC fab house

and for any IP cores needed Can increase time to market

Designer must develop complete testing methods Increasing Mask and Design Costs

Up to $50,000,000 for a state-of-the-art submicron ASIC High product volume needed to support mask and large

engineering development cost – need up to $250,000,000 in chip sales to recover these costs (5X development cost)

PSoC Design

Programmable System on a Chip (PSoC) A small low-cost microcontroller with on chip

memory, some programmable logic, and mixed signal hardware (A/D) – single chip solution

Tools provided to configure hardware, and then write software in assembly or C

Also has a new Labview type development tool Limited to just tens of KBs of on chip memory – so

no OS or full networking support PSoC is a trademark of Cypress PSoC II – new 32-bit ARM based processor core

Low Cost Cypress PSoC Board

SoPC Design

Use a large Field Programmable Gate Array (FPGA) with a processor IP core

In a Soft IP core logic elements from the FPGA are used to build the processor.

In a Hard IP core a full custom VLSI layout for the processor is placed in the FPGA

Soft cores more flexible, but have slower clock rates

Processor Cores for SoPC Soft Processor Cores for FPGAs

NIOS II - Altera Microblaze, Picoblaze, 8051 - Xilinx

Hard Processor Cores for FPGAs MIPS Altera, also ARM but not on newest FPGAs PowerPC Xilinx, but not on newest FPGAs S5 Tensilica Xtensa - Stretch

Largest FPGAs can support several processors on a single FPGA chip

Cost as low as $.35 per processor

Software for SoPC Design

Traditional FPGA tools (VHDL & Verilog) FPGA also used to build additional hardware

Processor Configuration Tool (Soft Cores) C/C++ Compiler for Processor Program Code Tools to debug code and load memories Optional OS support for Processor Board Support Package (BSP) provides OS

I/O device drivers for a specific board design

FPGA-based SOPC CAD Tool Flow

FEATURES OF COMMERCIAL

SOFT PROCESSOR CORES

Feature Nios 3.1 MicroBlaze 3.2

Datapath 16 or 32 bits 32 bits

Pipeline Stages 5 3

Frequency up to 150 MHz up to 150 MHz

Gate Count 26,000–40,000 30,000–40,000

Register File up to 512 32 general purpose

(window size: 32) and 32 special purpose

Instruction Word 16 bits 32 bits

Instruction Cache Optional Optional

Hardware Multiplier Optional Optional

This clock speed is not achievable on all devices. Some devices limit the maximum frequency to as low as 50 MHz.

Processor IP Core configuration tool for Altera’s Nios Processor

SOPC Memory Organization

Volatile Memory(for Application

Program Execution)

Non-volatile Memory(for Application

Program Storage)

ProcessorCore

On-chip Memory(Initialized with

bootloader)

To PC(via Serial Interface)

FPGA

Non-volatile (Flash) Memory is used both to boot processor software at power on and to configure the FPGA hardware

SoPC Design Space

Solution Time

Alg. Complexity

Not Obtainable

Hardware Software Tradeoffs

Solution Time

Alg. Complexity

Combining both approaches

Add custom co-processor for main processor Add custom instructions to processor Perform high data rate calculations in

hardware and the rest in software Automatic C compilers that transform critical

inner loop code to hardware are available – Stretch Inc (www.stretchinc.com) and recently from major FPGA Vendors.

Nios II C-to-Hardware Acceleration Compiler – C2H

Automatic acceleration of ANSI/ISO C code GHz performance possible with mW power

consumption  Tight integration with software design flow Direct connection of hardware accelerators to CPU's

memory map Seamless support for pointers and arrays Efficient latency-aware scheduling and pipelining of

memory transactions

Hardware Accelerator Design Flow

Block Diagram of example Mandelbot Processor System

Effect of Adding Hardware Accelerators on System Performance (left) and Power Consumption (right)

Effects of Reducing System Clock Frequency

Other C2H Benchmarks

Algorithm Speedup Hardware Increase

Autocorrelation 41.0x 115 Mhz 124%

Bit Allocation 42.3x 110 Mhz 152%

Convolution 13.3x 95 Mhz 133%

FFT 15.0x 85 Mhz 208%

High Pass Filter 42.9x 110 Mhz 181%

Matrix Rotate 73.6x 95 Mhz 106%

RGB to CMYK 41.5x 120 Mhz 84%

RGB to YIQ 39.9x 110 Mhz 158%

Recent SoPC OS Developments

FPGA processors initially did not have an MMU for Virtual Memory – Limits OS choices (Xilinx & Altera have just announced an MMU core and full Linux should soon follow)

Linux, Nucleus PLUS, NORTi, Wind River VxWorks AE X, OSE RTOS, and KROS are available for Altera’s FPGAs

Linux, QNX Neutrino, Wind River, & uC/OS-II RTOS are available for Xilinx’s FPGAs

Recent Trends

Increased mask costs and long product development times are making ASICs very expensive

Fewer ASIC Design Starts for last 10 years An industry survey in 2009 showed 30X more

FPGA-based design starts than ASICs

SoPC Technology Tradeoffs

Feature SOPC ASIC Fixed-Microprocessor

S/W Flexibility H/W Flexibility Reconfigurability Development Cost Peripheral Costs Performance Production Cost 11[ Power Efficiency

Legend: – Good; – Moderate; – Poor

[1] In very large quantities.

Altera’s SoPC UP 3 board contains a 200,000 gate FPGA with Flash and SRAM memory. It can run a soft Nios II RISC processor IP core

Xilinx SOPC FPGA Board

Xilinx SOPC Board Features

Xilinx Virtex-2 Pro FPGA with 3M Logic Gates, 136 18-bit multipliers for DSP applications, 2,448Kb of internal SRAM, and two PowerPC Microprocessors

DDR SDRAM DIMM that can accept up to 2Gbytes of RAM 10/100 Ethernet port & USB 2.0 port Non-volatile Flash memory & Compact Flash card slot VGA Video port & PC Audio Codec Serial ATA, PS/2, & RS-232 ports High and Low Speed I/O expansion connectors with a large

collection of available expansion boards Low cost: Board is $299 for Universities Xilinx SOPC Development tools are free for Universities

Altera’s SoPC DE2 board contains a large FPGA with hardware multiply, 4MB Flash, and 8MB SDRAM memory. It

can run C code on a soft Nios II RISC processor IP core

This R/C hobbyist Hummer was converted to an autonomous robot with

vision tracking capabilities using a SOPC board and a CMUCAM

This Amigobot commercial robot was originally designed to be remotely controlled using a PC with a serial cable. An FPGA-based

SOPC board was added to control the robot autonomously .

Altera DE2 board running uClinux on NIOS II processor (uClinux has no MMU)

A student designed FPGA-based SOPC board with FLASH and SRAM inside a modified toy front loader used as a robot.

A small SOPC-based aircraft autopilot system that contains an FPGA with a Nios processor core, a DSP processor, and memory. The bottom sensor board contains a GPS receiver, an A/D converter, MEMS gyros and accelerometers for all three axes, an airspeed sensor, and an altitude sensor. Photograph ©2004 Henrik Christophersen

Autopilot bottom sensor I/O board contains a GPS receiver, an A/D converter, MEMS gyros and accelerometers for all three axes, an airspeed sensor, and an altitude sensor. Photograph ©2004 Henrik Christophersen

Seismic Mine Detection System

SoPC Prototype with Sensorsin Laboratory Experimental Model

Analog Sensors

Digital Sensors

FPGA SoPC Board Seismic

Source

Conclusions

SoPC is at the leading edge of electronic systems design

Opportunities exist for innovative design approaches using processors, memory, and programmable FPGA logic

OS support is available for FPGA processors New approaches and new tools are needed

to explore and develop designs