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New SoC Integration Strategies for Multi-million Gate, Multi-power/Voltage Domain Designs Mayank Jindal, RTL Designer, TI [email protected] Gokulkrishnan Manoharan, RTL Designer, TI [email protected] Ayon Dey, RTL Designer, TI [email protected] Sarveswara Tammali, RTL Lead, TI [email protected] Dave Matt, SMTS, TI [email protected] Bernard Murphy, CTO, Atrenta [email protected]

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  • NewSoC IntegrationStrategiesforMulti-millionGate,

    Multi-power/VoltageDomainDesigns

    MayankJindal,RTLDesigner,[email protected]

    Gokulkrishnan Manoharan,RTLDesigner,[email protected]

    AyonDey,RTLDesigner,[email protected]

    SarveswaraTammali,RTLLead,[email protected]

    DaveMatt,SMTS,[email protected]

    BernardMurphy,CTO,[email protected]

  • 2AgendaSoC designchallengesTrendsofSoC integration pastandcurrentArchitecturebasedintegrationPowermanagementinsertionDesignreuseinneweraChallengesandkeybenefitsMetricsFutureworkConclusions

  • 30

    1

    2

    3

    4

    5

    6

    7

    8

    2005 2007 2009 2011

    Requiredproductivityfornewdesigns Requiredproductivityforreuseddesigns

    ProductivityChallenge (SourceITRS2005)

    Productivitymustincrease4Xin6years

    Designreuse2Xmore

    productive

  • 4SoC DesignChallenges

    IntegrateSoC (IP>100)withminimumdesignresources Productivitychallenge

    AccelerateSoC developmentcycle Timetomarket

    ThirdpartyIPs areusedtomeetproductgoals Timetomarket

    Complexityduetohigherintegration- Increasedverificationcyclesduetoincreasedbugs

  • 5SoC Integration- Past

    Challenges DesignbugsduetoIP

    incompatibility Activelowinterruptsource

    connectedtoactivehighinterruptdestination

    AHB/APB/OCPbussignalsareconnectedfrommasterslaveportbyport

    Localscripts/flowsspecifictoSoC teamsresultinginadhocSoC integrationflows

    HardwareIPLibrary

    Specification

    IPSelection

    XLS2HDL

    HDLfile

  • 6SoC Integration- Today TIAutogen TIwrappers+1Team-Genesis 1Team-Genesisprovides

    Underlyingdatabase IPdata(IP-XACT)Connectivityinformation

    ProvidesAPIstoaccess ProvidesGUI

    Whatarethebenefits? IPInformation Automaticallyloadsarchtables Performsautomatedchecks

    SoC testcases,Clibrary

    SoC toplevelnetlist RTL

    TIAutogenIPlibrary

    (IP-XACT,etc.)

    etc.

    SoC designer

    1Team-GenesisGUI

    IPinfo

    Chipw/IPinstanceInfo

    1Team-GenesisDB

    Reviewviews

    TIarchitecturetables

    Translators

    Files(RTL,etc)

    xml

    Generators

  • 7IP-XACT Adoption@TI IP-XACTreferstoasetofXMLschemasdefinedbyt heSPIRIT

    Consortium( www.spiritconsortium.org)

    IPXACTDescribes IPboundary(ports,direction,width,defaultvaluee tc) Registers

    Usercanextendwithattributesandparameterstod escribeIPconfiguration E.g.UART_RX_INTisanactive-low,levelinterrupt

    WithinTI,IP-XACTisusedtohelpautomateRTLhoo k-up,generationofregisterinfo(docs,CAPIs,testcases) IPteamsprovideIP-XACTfilestoSoC teams

    1Team-GenesisprovidesseveralwaysofcreatingIP- XACTfiles ImportRTLentity/excel OtherformatsofIP-XACT

  • 8ArchitectureBasedIntegration(1/2) Definition:

    Hook-upofIPs withinSoC,basedonknowledgeofpor tcharacteristicsembeddedinIP-XACT

    Allassociatedportsaregroupedintoabusdef basedonarchitecturalrelatione.g,OCP,DFT,powermanagemen t

    Enablescorrectbyconstructionhook-up

    1Team-Genesistoolwillerror-outifhook-upisforcedagainstarchitecturalrules Activelowinterruptsourceconnectiontoactiveh ighinterrupt

    controller

  • 9ArchitectureBasedIntegration(2/2)

  • 10

    PowerManagementInsertion(1/2)InanSOCwithtensofthousandsofsignalswiththousandsofcells,thisefforthastobeautomated

  • 11

    PowerManagementInsertion(2/2) TheuserdescribestheSoCs voltage&powerdomains,andassignstheIPinstancestothem

    TI-developedutilitiesuse1Team-GenesisAPIstodeterminealltheconnectionsbetweenIPs thatcrosspowerand/orvoltagedomainboundaries.Theseconnectionswillneedisolationcellsandlevelshifters

    Powermanagementblocksholdingtheseisolationcells&levelshifterswillbecreatedandaddedtothedesign

    Insteadofspecifyingthousandsoflow-leveldetails,thedesignerfillsoutafewhigh-leveltablesdescribingthedomainsandassignstheIPblockstothem

  • 12

    DesignRe-use Designre-useiscriticalfactorinthisSoC era

    Fastertime-to-market Addingfeaturestoexistingdesigns(Derivatives)

    The1Team-Genesisflowprovidesasmoothplatformt ore-useconnections ConnectiondatabetweenIPs iscapturedinTcl formatwh ichiseasyto

    process

    Design-1

    Re-using th

    e comm

    on

    connecti

    ons

    IP1 IP2

    IP3

    Design-2

    Re-using

    the common

    connections

    Design3

    IP1 IP2

    IP1

    IP3

  • 13

    ChallengesofNewIntegrationMethodology

    IPmodelingandIPpackaging Whichsetofsignalsneedtobegroupedasabusdef? Busdefs arenotbackwardcompatible InconsistencybetweenIPXACTandentityduetoprocessim maturity

    Designersview,paradigmshift UnderstandingtheexistingIPmodelsandtheirbusdefs Understandingthegroupingtobefollowedincaseofcr eatingnew

    busdefs Modelingcustomand3 rd partyIPs withtheexistingbusdefs andnewly

    createdbusdefs WorkingwithTcl asagainstHDL/xls (Easierthough!)

  • 14

    ChallengesofNewIntegrationMethodology(Continued)

    Handlingmultiplehierarchiesinasingledesign Instantiationofadesigncreatedinthetoolinane wdesignthroughIP-Model

  • 15

    KeyBenefitsoftheFlow

    Designre-use ConnectiondatabasecanbereusedforderivativeS oCs

    RTLhealthchecks Providesconnectionstatusofeachport/interfac e Providesmulti-drivers,floatinginputs ProvidesdatainExcelscsv format

    Usageof1Team-Genesisdatabaseforverification RTLhealthcheckdatabaseusedtocreateconnectiv itytestcases

    Easesphasewiseintegrationstrategy Easesthejoboftheintegrationengineerbyauto- insertionof

    defaultvaluestounconnectedinputs

  • 16

    IntegrationMetrics(1/2) SoCs

    Applicationprocessor Imageco-processor

    ProfileofSoC CortexARMprocessor Hardwareaccelerators Sophisticatedpower,clockmanagementmodule Lowcost,lowDPPMDFTsub-system Emulationsub-system Securitycontroller Peripherals(I2C,SPI,UART,GPIOetc.) DDRcontroller MIPIPHYs

  • 17

    IntegrationMetrics(2/2)

    Sl.No SoC Total#ofconnections

    (K)

    Total#ofreused

    connections

    #ofinstances

    MMeffort

    Savings(MM)

    1 SoC1 35 12 112 24MM 12MM

    2 SoC2 50 34 180 14MM 7MM

    3 SoC3 58 34 192 26MM 15MM

    Savingsinmanmonths(MM)

    Sl.No IP Ports #ofbusdefs

    1 IP1 1200 145

    2 IP2 890 115

    3 IP3 645 43

    BenefitsofusingIP-XACTandbusdef inSoC integrati on

  • 18

    FutureWork

    SingleflowforSoC integrationandRTLqualitychecks

    AutoECOportsadditionforsubchip hierarchies

    Handlinghierarchiesbetter

  • 19

    Conclusions Complexity,gapinproductivity,cycletimesareke y

    challengesofSoC design IP-XACTandarchitecturebasedintegrationhelpedT Ito

    addressabovechallenges 1Team-GenesistogetherwithTIwrappershaveenable dTIto

    pioneerinthisneweraofintegration KeychallengesincludeIPmodelingandbusdef alignm ent NewintegrationstrategystartedshowingR&Deffici encybut

    morepositiveimpactwillbeseeninnextcycleof designs Numberofintegrationbugsreducedsignificantlyov erpast

    designs Opportunityseentoreducedesignverificationeffo rt

  • 20

    AcknowledgementsAcknowledgestoteamwhosupportedflow

    SatyamPentakota(TII) SubashC(TII) Nitesh(TII)

    OtherRTLleadwhoisinvolvedindiscussion VincentLeRoy (TIF)


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