soc clock & timing closurecadlab.cs.ucla.edu/icsoc/...2010/steve_yang_2010.pdfsoc clock &...
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SoC Clock & Timing ClosureClosure
2010年8月19日
IndexIndex
HudaEmpyrean Software Co Ltd
SOC Implementation Challenges
HudaEmpyrean Software Co., Ltd.
ClockExplorer
TimingExplorer
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Company ProfileCompany Profile
• HES ( Huada Empyrean Software) was spinoff from Huada Electronics Design (HED) and founded in June 2009• HES is the largest EDA vendor in China
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Business ModelBusiness Model
Customized
Design Service
Customized EDA Tool
Service
EDA P d tProduct
EDA ProductsEDA Products
AetherAether Full-Custom IC Design Platform
AeolusSimulation Platform
ArgusPh i l ifi ti Pl tfPhysical verification Platform
SkipperChip-finishing Platform
ICExplorer ( ClockExplorer, TimingExplorer, RCExplorer…)SOC Design Optimization Platform
Chip finishing Platform
Design Service
QualChip (国奇科技)
Design Service
Team will grow to ~60 by the end of 2010
NRE and Turn-Key (RTL-GDSII-CHIP）Design Size: > 10 Million GateDesign Technology: 28nm ~ 180nmComplete IP Integration SolutionLow Power Design Flow One-time tape-out success and production ready
10+ successful tape-outs in one time
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Fast Growing TeamFast Growing Team
~150 employees at present, will be ~180 by the end of y2010
Representative CustomersRepresentative CustomersChina：
More than 40 customers in China, such as Solomon Systechsuch as Solomon Systech
Overseas:
Fairchild Imagining , US
Micro Encoder USMicro Encoder, US
Marvell, US
Hendon Semiconductors, AUS
T S GTesat-Spacecom, Germany
…
ParternsParterns
Marvell Semiconductor Inc US 晶门科技有限公司 香港Marvell Semiconductor Inc. USFairchild Imaging, USAgate Logic, USNHK JPN
晶门科技有限公司，香港
中芯国际集成电路制造有限公司（SMIC）
雅格罗技科技有限公司
国民技术股份有限公司NHK, JPNSteady Design, JPNNanyang Technological University, Singapore
国民技术股份有限公司
北京中电华大电子设计有限公司
北京中科联创科技有限公司
大连连顺电子有限公司University, Singapore……
大连连顺电子有限公司
清华大学
东南大学
……
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IndexIndex
HudaEmpyrean Software Co Ltd
SOC Implementation Challenges
HudaEmpyrean Software Co., Ltd.
ClockExplorer
TimingExplorer
- 10 -
SoC Design Methodology ChallengesSoC Design Methodology Challenges
Integrating existing IPs to SoC designs can bridge the productivity gap significantlysignificantlyMajor challenges
Design productivity Complexity / design sizeComplexity / design sizeFunctional Verification Analog/RF integration ( noise, mixed signal verification etc.)
Power consumption ( Dynamic power management, leakage power reduction)Manufacturability ( Yield, Reliability, Testability)
Complex design rulesAdvanced DFT
C t ( ft IP d i l k t t t )Cost ( software, IP, design cycle, mask, test etc)
Design houses are revising the SoC design MethodologySystem, logic, circuit, physical
Analog-RF IP Integration ChallengesAnalog RF IP Integration Challenges
More analog/RF IPs are integrated into wireless SoCsCoupling noise from digital portion to analog/RF IPs
Ad-hoc layout isolation rules verification Differential designDifferential design Frequency allocation Separate power-supply pads
Mixed-signal verificationModelingCapacity memory, run timeDifferent time steps run time
HES SoC Design Survey 2010HES SoC Design Survey 2010
The survey was conducted in 2010/08 basedThe survey was conducted in 2010/08 based on ~60 design engineers ( ~20 design companies ) in Beijing and Shenzhencompanies ) in Beijing and Shenzhen
NOTE: The data accuracy is for reference only d t li it d l d tdue to limited sample data
~30% using < 65nm technologies30% using 65nm technologies
40nm
65nm
90nm90nm
130nm
>180nm
SoC Design SizeSoC Design Size
>10M instance
5M-10M Instance
<500K i t
1M -5M instance
instance
SoC Back-end ImplementationSoC Back end Implementation
3-6 Months
1-3 Months
< 1 Months
Implementation BottleneckImplementation Bottleneck
Function ECO
Routing
Timing ECO
Function ECO
Ti i
Clock
Routing
placement
Timing Optimization
Floorplan
Timing ECOTiming ECO
> 4 weeks
1 2 k
2 - 4 weeks
< 1 week
1 – 2 weeks
Clock DesignClock Design
> 2 weeks
< 1 week
1 week- 2 week
< 3 days
Clock DomainsClock Domains
> 50
20-50
5-20
< 5
SoC Clock Synthesis ChallengesSoC Clock Synthesis Challenges
Clock design quality are strongly dependent on logic structure, modes, constraints ( SDC, clock synthesis pin exceptions)
Cl k l it d d l di t h lClock complexity and modes are exploding as technology down to 65nm and below
In-efficient communication between front-end/DFT andIn efficient communication between front end/DFT and back-end
Long CTS TAT (Turn-Around-Time)Long CTS TAT (Turn Around Time)Many iterations needed (weeks and even months)
Tremendous effort in manual debugging
SoC Clock Design IterationsSoC Clock Design Iterations
Front End Designer
Back End Designer
Front End Designer
SDC for Synthesis
Clock Module
Synthesis
Top Module Placement
Floor plan
IterationsVT Assignment
Gate CD Biasing
SDC for Top
Clock Information VT Assignment
G t CD Bi i
Constraint for CTS
CTS
CTO
Iterations
IterationsGate CD BiasingCTO
Long Turn-Around-Time (TAT)
Not Satisfied Quality-of-Results (QoR)Q y (Q )
ClockExplorer in a Design FlowClockExplorer in a Design Flow
Front End Designer
Netlist, SDC, Timing Lib, CTS constraints , SPEF,
LEF/DEF, Milkyway, OA,SDC for Synthesis
Clock ModuleBack End Designer
Cl k E lCl k E l
LEF/DEF, Milkyway, OA, etc.Synthesis
Top Module Placement
Floor plan
Clock ExplorerConstraint
Clock ExplorerConstraint
VT Assignment
Gate CD Biasing
SDC for Top
Clock Information
VT AssignmentClockExplorer MCMM CTS
Reduced Turn-Around-Time (TAT) Improved Quality-of-Results (QoR)Reduced Turn-Around-Time (TAT) Improved Quality-of-Results (QoR)
Successful Story (I) Reduce Clock Insertion delaySuccessful Story (I) Reduce Clock Insertion delay
Reduce clock insertion delay up to 50%Reduce significant effort in timing fix due to much lessReduce significant effort in timing fix due to much less On-Chip-Variation (OCV) caused clock uncertaintyReduce clock power and utilization
Saving weeks of design iteration timeg g
OriginalWith
Constraints
Insertion Delay (2.509, 2.884) (1.095, 1.440)NAND Flash Controller, ~500K instance,
65nmSkew (ns) 0.375 0.346
Logic Level 41 14
Buffer Count 328 91
ClockNetCap(pf) 14.15 10.675
Clock Structure W/O ClockExplorerClock Structure W/O ClockExplorer
invalid clock paths
real clock pathpower control registers
Simplified Clock Structure with ClockExplorerSimplified Clock Structure with ClockExplorer
Successful Story (II) Enable Multiple-Mode CTS
o Cell phone chip, 6.5M instance, ~80 master clocks, ~100 generated clocks 40nmclocks, 40nm
o Reduced significant iteration time in synthesizing multiple-mode ( 7 modes) clock
o Reduced CTS complexity dramatically due to much simplified clock structurestructure
o Reduced On-Chip-Variation significantly with reduced clock latency
Case 3: Multi-Mode Clock Constraint Auto-MergeCase 3: Multi Mode Clock Constraint Auto Merge
31 SDC files (modes)200 master clocks and 300 generated clocks in total
Manual merge7 days to merge and 1 month to finalize7 days to merge and 1 month to finalize24 master clocks, ~50 generated clocksWorst skew in all scenarios: 500ps, WNS in all scenarios: -70ps70ps
Auto merge20 min run time + Engineering review time < 1 day24 t l k 70 t d l k24 master clocks, ~70 generated clocksWorst skew in all scenarios: ~300ps, WNS in all scenarios: -10ps
IndexIndex
HudaEmpyrean Software Co Ltd
SOC Implementation Challenges
HudaEmpyrean Software Co., Ltd.
ClockExplorer
TimingExplorer
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Nightmare in Multi-Scenario Timing ClosureNightmare in Multi-Scenario Timing Closure
- Primetime lacks of physical information
- Correlation between implementation tools and timing sign-off tools
ECO Commands
MCMM TimingViolations
- Overwhelming effort of manual data mining, scripting and hand calculations spent in debugging timing problems and generating ECO scripts
PhysicalImplementation
Tools
- Hard to cover all scenarios
- Hard to predict or estimate physical impact
No
PrimeTimeAnalysis
- Many iterations to achieve closure- Long TAT and Low productivity
Analysis
Signoff
Yes
Long TAT and Low productivity
TimingExplorer Feature HighlightsTimingExplorer Feature Highlights
Multi-Scenario Physical-aware Timing ECO fix with Si ff Q litSign-off Quality
Improve physical correlation with built-in ECO placement, ECO routing, ECO extraction, and incremental timing updateECO timing fix flow integrated with PrimeTimeECO timing fix flow integrated with PrimeTime Enable multi-scenario ECO fixes for hold time and setup time.Auto-generate 3rd party ECO scripts
Interactive Multi-Scenario Timing DebuggingInteractive Multi-Scenario Timing Debugging EnvironmentMulti-Scenario Physical-aware Clock Latency OptimizationOptimizationSupport Hierarchical Design Style
Timing Fix FlowTiming Fix Flow
Timing ReportNetlist, TimingLibs, LEF/DEF,
or Sign-Off STA Timing Graph Data
Netlist, TimingLibs, SPEF/SDF, Milkyway
TimingExplorerTimingExplorer
PrimeTimeECO Script,
Incr SDF
Implementation:ECO Script,
Physical ChangesIncr SDF y g
Successful Story ISuccessful Story I
XXX Family ECO Comparison
XXX 1.0 XXX 2.0
(Using Ti i E l )TimingExplorer)
Timing ECO P i d
~4 Weeks ~2 Weeks
Period
ECO Iterations 11 ECOs to fix hold
4 ECOs on the 3 ECO to fix hold
1 ECO to fixsame group of setup time violations
1 ECO to fix setup
Successful Story IISuccessful Story II
25000
30000
35000 Results are verified with Physical implementation tool and golden sign-off tools
10000
15000
20000Hold Violations
tools
0
5000
10000
Original 1st ECO 2nd ECO 3rd ECO
40nm design, ~3M instance, hierarchical design, 3 setup
g
scenarios, 9 hold scenarios