simulating processors with elan(wrs’02)1 on applying elan strategies in simulating processors over...

Simulating Processors with ELAN(WRS’02) 1

On Applying ELAN Strategies in Simulating Processors over

Simple Architectures

R. M. Neto1, M. Ayala-Rincón1, R. P. Jacobi1, C. Llanos1, R. Hartenstein2

1Instituto de Ciências ExatasUniversidade de Brasília, Brasília D. F. Brasil

2Fachbereich InformatikUniversität Kaiserslautern, Kaiserslautern Germany

WRS’02 Copenhagen 21-07-2002


Overview

• Applying rewriting techniques in hardware design [Arvind et al]– specification of correct processors; formulation

of simple logical digital circuits; cache protocols over memory systems

– Correct specification of new features to processors

• Reorder buffers - ROB

• Speculative execution


Overview

• In Arvind’s approach rewriting is neither applied for simulation nor for verification. Proposal Translate to Verilog!

• Simulation and performance estimations using a rewriting-logic environment – logic plus rewriting allows for:

• Discrimination of architectural components

• Execution of assembly programs descriptions


Overview

• Once correctness is proved, simulations allow for a statistical analysis of different implementations.


Rewriting

Rewrite rules:

l => r if C

Operational semantics:

a rule is applied to a term, when its left-side matches a sub-term, replacing the matched sub-term with the corresponding right-side of the rule. All that, whenever the premise C of the rule holds.


Rewriting

l

l => r if C

C r t[s ] t[ ] whenever

One-step rewriting relation:

Important rewriting properties: termination and confluence

Notation: * “ zero or more steps of rewriting” relation;

s “normal or canonical form” of s;

! rewriting to a normal form;


Rewriting

In the context of processors specification:

• terms represent states and

• rewrite rules transformations between states, according to the instruction set of the processors.

• Beginning from an initial state and applying these rules we simulate the behavior of processors.


Specifying Processors

• AX ArchitectureInstruction set:

r:=Loadc(v) r:=Loadpc

r:=Op(r1,r2) Jz(r1,r2)

r:=Load(r1) Store(r1,r2)

• Basic Processor– Single cycle, non pipelined, in-order execution

• SYS := Sys(MEM,PROC)• PROC := Proc(ia, rf, prog)

Specifying ProcessorsBasic Processor

+1

RegisterFile

Int MemPC ALU

Data Mem

PROC(ia,rf,prog)

SYS(mem,Proc)


Specifying Processors

Jz(r1,r2)• Defining instructions as rules

[Jz] Sys(m,Proc(iaia,rf,prog)) => Sys(m,Proc(niania,rf,prog)) where instIa:=() selectinst(prog, ia) if isinstJz(instIa) where r1:=()reg1ofJz(instIa) where r2:=()reg2ofJz(instIa) choose try where nia:=()ia+1 if valueofReg(r1,rf)!=0if valueofReg(r1,rf)!=0

try where nia:=()valueofReg(r2,rf) if valueofReg(r1,rf)==0if valueofReg(r1,rf)==0 end end


Specifying ProcessorsSet of rewrite rules RB

[Loadc] Sys(m,Proc(ia,rf,prog)) => Sys(m,Proc(ia+1,insertRF(rf,r,v),prog))

where instIa :=() selectinst(prog,ia)

if isinstLoadc(instIa)

where r :=() nameofLoadc(instIa)

where v :=() valueofLoadc(instIa)

end

[Loadpc] Sys(m,Proc(ia,rf,prog)) => Sys(m,Proc(ia+1,insertRF(rf,r,ia),prog))


if isinstLoadpc(instIa)

where r :=() nameofLoadpc(instIa)

end

[Op] Sys(m,Proc(ia,rf,prog)) => Sys(m,Proc(ia+1,insertRF(rf,r,v),prog))


if isinstOp(instIa)

where r1 :=() reg1ofOp(instIa)

where r2 :=() reg2ofOp(instIa)

where r :=() nameofOp(instIa)

where v :=() valueofOp(r1,r2,rf)

end

[Jz] Sys(m,Proc(ia,rf,prog)) => Sys(m,Proc(nia,rf,prog))


if isinstJz(instIa)

where r1:=() reg1ofJz(instIa)

where r2:=() reg2ofJz(instIa)

choose try where nia:=()ia+1

if valueofReg(r1,rf) != 0

try where nia:=()valueofReg(r2,rf)

if valueofReg(r1,rf) == 0

end

end

[Load] Sys(m,Proc(ia,rf,prog)) => Sys(m,Proc(ia+1,insertRF(rf,r0,v0),prog))

where inst :=() selectinst(prog,ia)

if isinstLoad(inst)

where r0 :=() nameofLoad(inst)

where v0 :=() getMem(inst,rf,m)

end

[Store] Sys(m,Proc(ia,rf,prog)) => Sys(insertMEM(m,valueofReg(rA,rf),

valueofReg(rB,rf)),Proc(ia+1,rf,prog))

where inst :=() selectinst(prog,ia)

if isinstStore(inst)

where rA :=() nameofStoreR1(inst)

where rB :=() nameofStoreR2(inst)

end


Specifying ProcessorsSpeculative Processor

• To avoid waste of cycles/empty pipeline stages

• Reorder Buffer - ROB– Holds partially executed instructions– Renaming Tags/Register correspondence

• Speculative execution:– Branch Target Buffer - BTB


RegisterFile

Int Mem

PC

Data Mem

Reorder BufferROB

ALUs

BTBbranch

pmb

mpb

Commit

Fetch/Decode/Rename

Kill

Execute

Kill/Update BTB

PROC(ia,rf,itb,btb,prog)

SYS(mem,Proc)



• Basic Processor– Single cycle, non

pipelined, in-order execution

SYS := Sys(MEM,PROC)

PROC := Proc(ia, rf, prog)

• Speculative Processor– Pipelined, out-of-order execution

SYS := Sys(MEM,PROC)

PROC := Proc(ia, rf, itb, btb, prog)



Set of rewrite rules RSArithmetic Operation and Value

Propagation Rules:

[PsOp] [PsValueForward]

[PsValueCommit]

Branch Completion Rules [PsJumpCorrectSpec]

[PsJumpWrongSpec][PsNoJumpCorrectSpec][PsNoJumpWrongSpec]

Instruction Issue Rules

[PsLoadcIssue] [PsLoadpcIssue] [PsOpIssue] [PsJzIssue] [PsLoadIssue]

[PsStoreIssue]

Memory Access Rules [PsLoad][PsStore]

RITBF



[PsOp] Sys(m,Proc(ia,rf,ITB(ia1,k,t(k)|-Op(v,v1),t(k)|-Op(v,v1), wf,sf).itbs2, btb, prog)) => Sys(m,Proc(ia,rf,ITB(ia1,k,t(k)|-execOponval(v,v1t(k)|-execOponval(v,v1)),wf,sf).itbs2, btb,prog))end

[PsJzIssue] Sys(m, Proc(iaia,rf,itbsitbs,btb,prog)) => Sys(m, Proc(piapia,rf, insEndITBs(ITB(ia,k,Jz(k0,k1),ITB(ia,k,Jz(k0,k1),NoWreg,Spec(pia)),itbs), btb,prog)) where instIa :=() selectinst(prog,ia)

if isinstJz(instIa)

where r1 :=() reg1ofJz(instIa) where r2 :=() reg2ofJz(instIa) where k :=() lengthof(itbs)+1 where k0 :=() searchforLastTag(r1,rf,itbs) where k1:=()searchforLastTag(r2,rf,itbs) where pia:=()getbtb(ia,btb) end



[PsJumpCorrectSpec]

Sys(m,Proc(ia,rf,ITB(ia1,k,Jz(0,nia),Jz(0,nia),wf,Spec(pia)).itbs,btb,prog)) =>

Sys(m,Proc(ia,rf,itbsitbs,btb,prog))

if pia==niaif pia==nia

end

Specifying Processors Reorder Buffer

t1:=Op(v’,v’’) t2:=Load(t’) t3:=Op(t2,t1)

Program:...ro:=Op(r1,r2)r3:=Load(r4)r5:=Op(r3,r1)...

Issue Rules

Execution in the buffer

Memory Register FileValues Commited

t0:= v ...

Ps_Op_Issue: Proc(ia,rf,itbs,btb,[...(ia,r5:=Op(r3,r1)...])

Proc(ia+1,rf,itbs+ITB(ia,t3:=Op(t2,t1)),btb,prog)

Ps_Value_Commit:Proc(ia,tf,ITB(t:=v)+itbs,...)

Proc(ia,tf,itbs,...)

Specifying Processors Reorder Buffer

Jz(0,nia),Spec(pia) t2:=Load(t’) t3:=Op(t2,t1)

Program:...r3:=Load(r4)r5:=Op(r3,r1)...

Issue Rules

Execution in the buffer

Memory Register FileValues Commited

t0:= v ...

Ps_Jump_WrongSpec: Proc(ia,rf,itbs1+ITB(ia,Jz(0,nia),Wreg, Spec(pia))+itbs2, btb, prog)

Proc(nia,rf,itbs1, btb’, prog)

20Simulating Processors with ELAN(WRS’02)

Correctness of the specifications

• RS simulates RB:

• RB simulates RS:

The speculative processor simulates the basic one: in fact, a basic processor term can be “upgraded” to one of the speculative processor simply by adding an empty ITB and an arbitrary BTB to the processor.

During some time of the execution over an speculative processor, if no instruction is issued then the ITB will soon become empty. Only instruction issue rules can further expand the ITB. Thus, we can define another rewriting system, RITBF, which consist of all rules in RS except the instruction issue rules.


Correctness of the specifications

• RB simulates RS: RS

Terms of the speculative processor s * t

RITBF ! !

Terms of the basic processor ITBF( s ) * ITBF( t ) RB

Notation ITBF(s) result of eliminating the empty ITB and the BTB


Implementation in ELAN

Philosophy of “Rewriting-logic”: combination of possibilities of rewriting and of logic strategies for controlling application of rewrite rules. Also, rewriting logic plus meta-logic.

Well-known programming environments like – Maude [J. Meseguer, SRI Int. CSL, Menlo Park CA] – ELAN [C. kirchner, LORIA/INRIA, Nancy France] and– Cafe-OBJ [JAIST, Japan] are available.

23Simulating Processors with ELAN(WRS’02)


Logic andstrategies

Rewrite basedspecification

Super user

programmer

Computationalsystem

rewriteengine

Initial State:Assembly Code with Current Memory State

Query

ResultFinal State:

Processor State After Exec

Instructions, predictions

Control of BUFFERS

TransformationsTransformations



Rewrite rules

• used for specifying the instruction set

• used for specifying the method of branching prediction



Branch Taken Branch Not Taken

Prediction Method(1-Bit)

Taken

Not taken

Not takenTaken



• Branching prediction:BTB : (1,2).(2,3). ... .(n,m). ...

nth instruction: Jz(r1,r2)[PsJumpWrongSpec] Sys(m,Proc(ia,rf,ITB(ia1,k,Jz(0,nia),wf,Spec(pia)).itbs,btb,prog))

=> Sys(m,Proc(nia,rf,nilitb,btb1,prog))

if pia != niapia != nia where btb1 := ()changebtb(ia1,nia,btb)changebtb(ia1,nia,btb)

end



Rewriting-logic/strategies

Control how to apply rules.

Aspects as size and the way of working with the ROBs may be determined by rewrite strategies.



select one( {issue rules} );

select one( {issue rules}{id} );

repeat * n-1

select one( {issue rules}{id} );

normalize( select one( {non issue rules} )

Size control of the ROB by strategies.

RITBF


Issue Rules

ITB ITB ITB ITB

1234

NormalizeArithmetic Op

Memory Access

Value Forward

Value Commit


Estimating Processors Performance

ELAN statistics number of applied rules

Analyzing eventual performance of processor implementations.

Example:

Number of correct and wrong predictions when running the same processor with different method of speculation.

counting the number of applications of rules:

PsJumpCorrectSpecPsNoJumpWrongSpecPsJumpWrongSpecPsNoJumpWrongSpec


Estimating Processors Performance

• One Bit Vs Two Bit Speculative Prediction

Length 10 20 30 40 50

Correctpredictions

60 225 490 855 13201-bit

Wrongpredictions

34 74 114 154 194

Correctpredictions

73 258 543 928 14132-bit

Wrongpredictions

21 41 61 81 101


Conclusions and Future Work• Rewriting-logic is useful for specifying

correctly processors, but also for testing their performance.

• Going down more levels

– Execution stages: fetch-decode-execute by atomizing the current implemented rules. Describing in this way more accurately processors behavior.

• Going down more levels:

– Logic circuit layout design.


Conclusions and Future Work• Important natural aspects of rewriting

theory, nowadays hard to resolve and implement in programming and proof assistants environments, may be useful for testing accurately new proposed technologies:

Like a real non deterministic out-of-order execution.


Cronograma para Conclusão

Atividade Junho Julho Agosto Setembro OutubroElaboração deDissertaçãoDefesa


Further Reading• M. Ayala-Rincón, R. Hartenstein, R. P. Jacobi and C. Llanos,

Designing Arithmetic Digital Circuits via Rewriting-Logic, http://www.mat.unb.br/~ayala/publications.html

• M. Ayala-Rincón, R. Maya Neto, R. P. Jacobi, C. Llanos and R. Hartenstein, Architectural Specification and Simulation Through Rewriting-Logic, http://www.mat.unb.br/~ayala/publications.html

• Prototypes: http://www.mat.unb.br/~ayala/Tcgroup

• Talk: http://www.mat.unb.br/~ayala/ publications.html

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