simple finite state machines
TRANSCRIPT
Simple Finite State Machines
Last updated 8/3/20
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Simple FSMs
These slides review the basics of HDL based Finite State Machines
Upon completion: You should be able to design and simulate basic FSMs
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Simple FSMs
• Finite State Machine
• Moore Machine
• Outputs depend only on the current state(S)
Next StateLogic
Register(D-FFs)
k kinputs
outputs
SS’M
OutputLogic
N
clk
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Simple FSMs
• Finite State Machine
• Mealy Machine
• Outputs depend on the current state(S) and the inputs
Next StateLogic
Register(D-FFs)
kk
inputs
outputs
SS’M
OutputLogic
N
clk
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Simple FSMs
• Finite State Machine
• To create an FSM in VHDL you combine• Enumerated types
• Simple register logic
• Combinatorial logic process
• Reset
• An abstraction of the FSM is used for RTL simulation
• Ensure that all states have entry and exit conditions
• Ensure that all states are covered in the code
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Simple FSMs
• Sequence detector - CD
• Detecting 11001101
rst
detect = 0resetb
A
detect = 0
1
0
B
detect = 0
1
0
C
detect = 0
0
1
D
detect = 0
0
1
det
detect = 1
G
detect = 0
1 F
detect = 0
0 E
detect = 0
1
10
01 0
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Simple FSMs
• Sequence detector - CD
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Simple FSMs
• Sequence detector - CD
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Simple FSMs
• Sequence detector - CD
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Simple FSMs
• Sequence detector - CD
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Simple FSMs
• Sequence detector - CD
repeat B Back to start Back to startBack to A
full sequence re-start
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Simple FSMs
• Priority Stoplight
ST0
NS: greenEW: red
ST1
NS: yellowEW: red
ST3
NS: redEW: yellow
ST2
NS: redEW: green
reset
TNS
TEW
TNS
TEW
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Simple FSMs
• Priority Stoplight
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Simple FSMs
• Priority Stoplight
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Simple FSMs
• Priority Stoplight
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• Priority Stoplight
Simple FSMs
normal cycle N/S Priority