silicon technology leadership and the new scaling paradigm paolo
TRANSCRIPT
Silicon Technology Leadership Silicon Technology Leadership and the and the
New Scaling ParadigmNew Scaling Paradigm
Paolo GarginiPaolo GarginiDirector of Technology Strategy Director of Technology Strategy
and Intel Fellowand Intel FellowSr. Member, IEEESr. Member, IEEE
Chairman of the ITRSChairman of the ITRS
Santa ClaraSanta ClaraJune 20, 2007June 20, 2007
Key MessagesKey Messages
Intel’s R&D pipeline will sustain Moore’s Law for the foreseeable future
45 nm high-k + metal gate is the most significant innovation in transistor technology in 40 years
Intel has removed 100 percent of the lead across its Intel has removed 100 percent of the lead across its entire portfolio of packages in its 45nm family of entire portfolio of packages in its 45nm family of microprocessorsmicroprocessors
Intel continues its unwavering commitment to support R&D for future technologies and to deliver the benefits of Moore’s Law to our customers
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
Lower cost per transistor
Smaller dimensions
Delivering MooreDelivering Moore’’s Laws Law
0.01
0.1
1
10
1970 1980 1990 2000 2010 2020
Feature Size (um)
1970 1980 1990 2000 2010 2020
Cost per Transistor ($)
10-3
100
10-6
10-9
1970 1980 1990 2000 2010 2020
Transistor Count
103
106
109
Enables more transistors and increased performance
Moore’s Law = Transistor Budget +
Lowest Power and Lowest Cost
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
Research Development Manufacturing
Continuous flow of new technologies from research to development to manufacturing
22 nm22 nm 32 nm32 nm 45 nm45 nm 65 nm65 nm
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
–– Strained SiliconStrained Silicon
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
Transistor Trade-offs
FMax= IDSat / VDDCox
IDSat~1 µCox(W)(VDD –VT)2
2 Lg
Power= VDD2 Cox FMax
S D
G
LgW
Increase Cox=>Reduce tox
Reduce Lg
Reduce VDD
εo εstox tox
Gate Oxide ScalingGate Oxide Scaling
1
10
1990 1995 2000 2005
Gate Oxide Thickness
(nm)
1
10
1.2 nm90nm
.13um
.18um
.25um
.35um
Generation
IDSat 1 µ (VDD –VT)2
2 LgWεo εs 1
tox~
90 nm crossover occurred in Q3 ’04
Intel Ramped Production Ahead of Intel Ramped Production Ahead of Industry on 90 nm Technology Generation Industry on 90 nm Technology Generation
Q1 ’04 Q3 ’04 Q1 ’05
130nm130nm
90nm90nm
0%
25%
100%
75%
50%
Q2 ’04 Q4 ’04
Total CPU Shipments
Geometrical Scaling Limitations
Substrate
Gate
Source Drain
Gate Leakage
Channel Leakage
Source and DrainResistance
0
50
100
150
200
250
1 1.2 1.4 1.6 1.8 2 2.2 2.4Electric Field (MV/cm)
Mob
ility
(cm
2 /Vse
c)Universal Mobility
µ = (qτ/2m*)
•S/D Leakage•Gate Leakage•S/D Resistance•Decreased Mobility
New Transistor Trade-off
IDSat~1 µCox(W)(VDD –VT)2
2 Lg
S D
G
LgW
Increase CoxReduce Lgµ
Increase µεo κs
tox
New Material
Gate Oxide ScalingGate Oxide Scaling
1
10
1990 1995 2000 2005
Gate Oxide Thickness
(nm)
1
10
1.2 nm
Gate oxide scaling is reaching its limitsGate oxide scaling is reaching its limits
90nm.13um
.18um
.25um
.35um
Generation Silicon substrate
1.2nm SiO2
Gate
65nm
Mobility InnovationMobility Innovation
SiGeSiGe
Strained Strained PP--Channel Channel TransistorTransistor
High Stress Film
Strained Strained NN--Channel Channel TransistorTransistor
Source: Intel
1
10
100
1000
0.2 0.4 0.6 0.8 1.0 1.2ION (mA/um)
IOFF
(nA/um)
PMOS NMOS
90 nm20022004
65 nm 2004
1.0 V
Improved Transistor PerformanceImproved Transistor Performance
65 nm transistors increase drive current 1065 nm transistors increase drive current 10--15% with enhanced strain15% with enhanced strain
1
10
100
1000
0.2 0.4 0.6 0.8 1.0 1.2ION (mA/um)
IOFF
(nA/um)
PMOS NMOS
90 nm20022004
65 nm2004
1.0 V
Improved Transistor PerformanceImproved Transistor Performance
65 nm transistors can alternatively provide ~4x leakage reductio65 nm transistors can alternatively provide ~4x leakage reductionnNo other company has matched these performanceNo other company has matched these performance--leakage capabilitiesleakage capabilities
Power Saving Feature
Defect Density
(log scale)
0.13 um 90 nm 65 nm 45 nm
2000 2001 2002 2003 2004 2005 2006 2007
65 nm Yield Improvement Trend65 nm Yield Improvement Trend
65 nm is Intel’s highest yielding process ever
Intel Only: Intel Only: Process + Products + ProductionProcess + Products + Production
65 nm crossover occurred in Q3 ’06>120 million units shipped so far
Total CPU Shipments
FORECASTFORECAST
0%0%
25%25%
50%50%
75%75%
100%100%
Q1Q1’’0606 Q2Q2’’0606 Q3Q3’’0606 Q4Q4’’0606 Q1Q1’’0707
65 nm
90 nm
65 nm Summary65 nm Summary
Intel has been shipping 65 nm processors since October 2005, more than one year ahead of the competition
Intel has shipped >120 million 65 nm
Only Intel has three 65 nm / 300 mm fabsshipping in volume
Logic Technology EvolutionLogic Technology Evolution
Process Name P860 P1262 P1264 P1266 P1268
Lithography 130 nm 90 nm 65 nm 45 nm 32 nm
1st Production 2001 2003 2005 2007 2009
Wafer (mm) 200/300 300 300 300 300
ManufacturingManufacturing
DevelopmentDevelopment
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
–– Strained SiliconStrained Silicon
–– HighHigh--k+ Metal gate for 45nm technologyk+ Metal gate for 45nm technology
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
1010November 4th, 2003November 4th, 2003
HighHigh--k Dielectric reduces leakage k Dielectric reduces leakage substantiallysubstantially
Silicon substrate
Gate
3.0nm High-k
Silicon substrate
1.2nm SiO2
Gate
Far coolerFar cooler> 100x reduction> 100x reductionGate dielectric Gate dielectric leakageleakage
Much faster Much faster transistorstransistors60% greater60% greaterCapacitanceCapacitance
BenefitBenefitHighHigh--k vs. SiOk vs. SiO22
Benefits compared to current process technologiesBenefits compared to current process technologies
33November 4th, 2003November 4th, 2003
Continuation of MooreContinuation of Moore’’s Laws Law
Strained Strained SiSi
Strained Strained SiSi
Strained Strained SiSi
Strained Strained SiSi
Strained Strained SiSiSiSiSiSiSiSiChannelChannel
P1270P1270P1268P1268P1266P1266P1264P1264P1262P1262Px60Px60P858P858P856P856Process NameProcess Name
300300300300300300300300300300200/300200/300200200200200Wafer Size Wafer Size (mm)(mm)
MetalMetalMetalMetalMetalMetalPolyPoly--siliconsilicon
PolyPoly--siliconsilicon
PolyPoly--siliconsilicon
PolyPoly--siliconsilicon
PolyPoly--siliconsiliconGate electrodeGate electrode
HighHigh--kkHighHigh--kkHighHigh--kkSiOSiO22SiOSiO22SiOSiO22SiOSiO22SiOSiO22Gate dielectricGate dielectric
??CuCuCuCuCuCuCuCuCuCuAlAlAlAlInterInter--connectconnect
22 nm22 nm32 nm32 nm45 nm45 nm65 nm65 nm90 nm90 nm0.130.13µµmm0.180.18µµmm0.250.25µµmmProcess Process GenerationGeneration
20112011200920092007200720052005200320032001200119991999199719971st Production1st Production
Introduction targeted at this timeIntroduction targeted at this time Subject to change Subject to change
Intel found a solution for High-k and metal gateIntel found a solution for HighIntel found a solution for High--k and metal gatek and metal gate
45 nm benefits compared to 65 nm
45 nm Technology Benefits45 nm Technology Benefits
~2x improvement in transistor density, for either smaller chip size or increased transistor count
~30% reduction in transistor switching power
>20% improvement in transistor switching speed or >5x reduction in source-drain leakage power
>10x reduction in gate oxide leakage power
These performance and leakage improvements would not be possible without high-k + metal gate
Mark Bohr1-26-2007
45nm High45nm High--k Performance/Power k Performance/Power BenefitsBenefits
Transistor Performance vs. LeakageTransistor Performance vs. Leakage
Transistor Drive Current (rel.)
>5xLower Leakage
20%Higher Drive
65 nm 45 nm
10
100
1000
0.5 1.0 1.5
Leakage Current(nA/um)
Source: Intel Internal
Gate Oxide LeakageGate Oxide Leakage
0.01
0.1
1
10
100
1000
32nm
45nm
65nm
90nm
.13um
.18um
.25um
.35um
.50um
Technology Generation
Gate Leakage
(rel.)
1
10
PhysicalTox (nm)
Gate oxide scaling stopped due to leakage
SiO2
Gate Oxide LeakageGate Oxide Leakage
0.01
0.1
1
10
100
1000
32nm
45nm
65nm
90nm
.13um
.18um
.25um
.35um
.50um
Technology Generation
Gate Leakage
(rel.)
1
10
PhysicalTox (nm)
Hi-k
Hi-k
High-k dielectric breaks through this barrier
SiO2
HighHigh--k + Metal Gate Transistorsk + Metal Gate Transistors
HK+MG Transistor
Silicon substrate
Metal Gate
Increases the gate field effect
High-k Dielectric
Increases the gate field effect
Allows use of thicker dielectric to reduce gate leakage
S D
Low resistance layer
Metal gateDifferent for
NMOS and PMOS
High-k gate oxideHafnium based
High-k + Metal Gate CombinedTransistor drive current increased >20%
Or source-drain leakage reduced >5xGate oxide leakage reduced >10x
Integrated 45 nm CMOS process
High performance
Low leakage
Meets reliability requirements
Manufacturable in high volume
HighHigh--k + Metal Gate Transistorsk + Metal Gate Transistors
HK+MG Transistor
Silicon substrate
S D
Metal Gate
High-k
“The implementation of high-k and metal gate materials marks the biggest change in transistor technology since the introduction
of polysilicon gate MOS transistors in the late 1960s”— Gordon Moore
0.1
1
10
100
1992 1994 1996 1998 2000 2002 2004 2006 2008
Cell Area (µm2)
0.1
1
10
100
1992 1994 1996 1998 2000 2002 2004 2006 2008
Cell Area (µm2)
Density Scaling on TrackDensity Scaling on Track
0.5x every 0.5x every 2 years2 years
SRAM Cell SizeSRAM Cell Size
45 nm
0.35 um
65 nm90 nm
0.13 um
0.18 um
0.25 um
0.346 µm2 Cell 193 nm Dry Lithography
Cost-effective 193 nm dry lithography extended to 45 nm generation
HighHigh--k + Metal Gate Transistorsk + Metal Gate Transistors
Low Resistance Layer
High-k + metal gate is the biggest improvement in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s
Integrated 45 nm CMOS process
High performance
Low leakage
Meets reliability requirements
Manufacturable in high volume
High-k Dielectric Hafnium based
Silicon Substrate
Work Function MetalDifferent for NMOS and PMOS
This technology was already developed on January 2006!!!!0.346 0.346 µµmm22 cell cell
153 153 MbitMbit densitydensity
119 mm119 mm22 chip sizechip size
>1 billion transistors>1 billion transistors
Functional silicon in Jan Functional silicon in Jan ‘‘0606
45 nm SRAM test vehicle includes all transistor 45 nm SRAM test vehicle includes all transistor and interconnect features to be used on 45 nm and interconnect features to be used on 45 nm
microprocessormicroprocessor
January, 2006
45 nm SRAM Chip45 nm SRAM Chip
Logic Technology EvolutionLogic Technology Evolution
ManufacturingManufacturing
DevelopmentDevelopment
Process Name P860 P1262 P1264 P1266 P1268
Lithography 130 nm 90 nm 65 nm 45 nm 32 nm
1st Production 2001 2003 2005 2007 2009
Wafer (mm) 200/300 300 300 300 300
Source: Intel Internal
45 nm45 nm
65 nm65 nm
Q1Q1’’0808
2020
3030
4040
5050
6060
7070
8080
9090
00
1010
Q2Q2’’0808 Q3Q3’’0808 Q4Q4’’0808
CPU Shipments (65nm vs. 45nm)CPU Shipments (65nm vs. 45nm)
Forecast2H2H’’0707
100%100%
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
Design for manufacturing (DFM)Design for manufacturing (DFM)
MooreMoore’’s Law depends on scaling physical dimensionss Law depends on scaling physical dimensions
Small variations in dimensions and doping can Small variations in dimensions and doping can cause significant variation in function, power and cause significant variation in function, power and performanceperformance
““DFMDFM”” is a set of Designis a set of Design--Process methodologies that Process methodologies that reduces and mitigates reduces and mitigates ““variabilityvariability””
DFM is the solution to the variability challenge
Rounding in transistor layoutsRounding in transistor layouts
Drawn Printed
GS D GS D
Leff
Leff errorLonger channelSlower transistor
PolyRounding
DiffusionRounding
W errorLonger widthWaste of powerW
Litho DFM solution:Litho DFM solution:Advanced APSM masks w/ Litho DFMAdvanced APSM masks w/ Litho DFM
65nm Logic65nm Logic
Intel was first to ramp Alternating Phase Shift Masks (APSM) with litho DFM for65nm gate patterning and Leff control
65nm SRAM65nm SRAM
LithographyLithography
Enhancements have extended 193 nm dry lithography to the 45 nm generation
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm
193 nm248 nm
LithographyWavelength
65 nm
32 nm45 nmFeature
Size
Optical proximity correctionHigher numerical aperture
Phase shift masks
LithographyLithography
Immersion lithography will extend 193 nm at least to the 32 nm generation
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm
193 nm248 nm
LithographyWavelength
65 nm
32 nm45 nmFeature
Size
Optical proximity correctionHigher numerical aperturePhase shift masksImmersion lithography
0.10.1
11
1010
100100
19921992 19941994 19961996 19981998 20002000 20022002 20042004 20062006 20082008
Cell Area Cell Area (um(um22 ))
0.5x every 0.5x every 2 years2 years
Committed to Provide the Best Total Committed to Provide the Best Total Cost at 45nm Cost at 45nm
45nm Cell45nm Cell0.346 um20.346 um2
Density reduction at Density reduction at Lowest cost and TTMLowest cost and TTM
Exceptional Gate control through Exceptional Gate control through PSM and Double PatterningPSM and Double Patterning
SRAM SRAM -- Functional silicon in Jan Functional silicon in Jan ‘‘0606
Critical Layer Lithography Cost ComparisonCritical Layer Lithography Cost Comparison45nm Node assuming equal yield45nm Node assuming equal yield
0.90.9
11
1.11.1
1.21.2
1.31.3
193nm Dry193nm Dry 193nm Immersion193nm Immersion
ForecastForecast
Intel DFM advantage: Intel DFM advantage: Collaboration of diverse disciplinesCollaboration of diverse disciplines
Design ToolsDesign Tools
ManufacturingManufacturing
PackagingPackagingMasksMasks
ProcessProcess ProductProduct
Diverse disciplines collaborate under one roof to co-optimize DFM solutions
45 nm Manufacturing 45 nm Manufacturing FabsFabs
D1D Oregon - 2H ‘07 Fab 32 Arizona - 2H ‘07
Fab 11X New Mexico - 2H ‘08Fab 28 Israel - 1H ‘08
Defect Density
(log scale)
0.13 um 90 nm 65 nm 45 nm
2000 2001 2002 2003 2004 2005 2006 2007
45 nm defect reduction trend at expected 2 year offset 45 nm on track for production in 2H ‘07
45 nm Yield Improvement Trend45 nm Yield Improvement Trend
2 years
WorldWorld’’s First Working 45 nm CPUss First Working 45 nm CPUs
SilverthorneSilverthorne45 nm Hi-k new low power
microarchitecture
Mobile Internet Devices and Ultra-Mobile PCs
PenrynPenryn45 nm Hi-k Intel® Core™2 and Intel Xeon™ processors
Mobile, Desktop, Workstation, and Server Optimized
20102007 2008 2009
PenrynPenryn NehalemNehalem Sandy Sandy BridgeBridge
WestmereWestmere
NEWMicroarchitecture
45nm
NEWMicroarchitecture
32nm
Compaction/Derivative45nm
Compaction/Derivative32nm
Tick/Tock: Our Model for Tick/Tock: Our Model for Sustained Microprocessor Sustained Microprocessor
Leadership Leadership
2006
IntelIntel®®CoreCore™™
NEWMicroarchitecture
65nm
Forecast
Driving Down Power and SizeDriving Down Power and SizeCPU + CHIPSET
2006 2008 2009/2010
SIZEmm2
AVERAGEPOWER
Watts
1/91/20
SYSTEMON A CHIP
1/4 1/4
Source: Intel Internal
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
SummarySummary–– Intel has removed 100 percent of the lead (Pb) across its Intel has removed 100 percent of the lead (Pb) across its
entire portfolio of packages in its 45nm family of entire portfolio of packages in its 45nm family of microprocessors microprocessors –– …… 65nm chipsets will transition to 100% lead65nm chipsets will transition to 100% lead--free in 2008free in 2008
–– IntelIntel’’s 45nm His 45nm Hi--k metal gate process technology represents a k metal gate process technology represents a dramatic transition to new materials that enable energy dramatic transition to new materials that enable energy efficient performance microprocessorsefficient performance microprocessors
–– IntelIntel’’s family of 45nm microprocessors will begin production s family of 45nm microprocessors will begin production in second half of 2007in second half of 2007
–– IntelIntel’’s effort to eliminate lead in our products is part of s effort to eliminate lead in our products is part of broader strategy to support an environmentally sustainable broader strategy to support an environmentally sustainable futurefuture
Reduced Environmental FootprintReduced Environmental Footprint
Recent SuccessesRecent Successes–– Launched IntelLaunched Intel®® CoreCore™™2 Duo processors: for desktops up to 40% 2 Duo processors: for desktops up to 40%
faster and 40% more energy efficient faster and 40% more energy efficient –– Transitioned IntelTransitioned Intel®® StrataFlashStrataFlash®® Cellular Memory packages to Cellular Memory packages to
halogenhalogen--free technology. free technology. –– Saved over 9 billion gallons of fresh water through our water reSaved over 9 billion gallons of fresh water through our water reuse use
and recycling practices and recycling practices –– Recycled more than 70% of our chemical and solid wastesRecycled more than 70% of our chemical and solid wastes–– Reduced our global warming gas emissions the equivalent of Reduced our global warming gas emissions the equivalent of
removing 50,000 cars from the roadremoving 50,000 cars from the road–– Named Technology Super Sector Leader by Dow Jones Named Technology Super Sector Leader by Dow Jones
Sustainability Index for the 6Sustainability Index for the 6thth year runningyear runningIntel 2006 Corporate Social Responsibility report recently posteIntel 2006 Corporate Social Responsibility report recently posted d
online online http://www.intel.com/intel/cr/gcr06/overview.htmhttp://www.intel.com/intel/cr/gcr06/overview.htm
Eliminating the Eliminating the Lead (Lead (PbPb) in Intel Components) in Intel Components
Lead
Lead
Flip-Chip Ball Grid Array (FC-BGA)
socketsocket
Flip-Chip Pin Grid Array (FC-PGA)
Lead
Lead
Capacitors
Solder Balls
CapacitorsFlip-Chip
Bump
Printed Circuit Board
Lead
Flip-Chip Bump
X
X
X
^RoHS Exempt
^RoHS Exempt
**95% of the Lead Content Removed from 95% of the Lead Content Removed from FlipFlip--chip Packages in 2004chip Packages in 2004
*Percentage based on weight
Pin GridLeadX
LeadLead--Free Solder Properties Affect LowFree Solder Properties Affect Low--K K Inter Layer DielectricInter Layer Dielectric
At reflowtemperature
HeatingHeating
At room temperature
CoolingCooling
Silicon DieCTE* 2.8 ppm/ºC
Flip Chip Bump
PackageCTE* 17 ppm/ºC(Copper Laminate)
150 C
170 C
190 C
210 C
230 C
Lead-Tin 183 C
Lead-Free>220 C
Melting Point
Lead-free solder increases stress
The Package shrinksmore than the chip
* CTE = Coefficient of Thermal Expansion *PPM= Parts Per Million
LowLow--K Silicon & LeadK Silicon & Lead--free Package free Package Integration ChallengeIntegration Challenge
Successful Integration of Silicon & LeadSuccessful Integration of Silicon & Lead--Free Flip Chip Free Flip Chip Package Technologies requires a significant reduction Package Technologies requires a significant reduction
in in Inter Layer Dielectric (ILD) StressInter Layer Dielectric (ILD) Stress
example silicon cross-section
ILD Strength
Joul
es/m
2
SiO2 Low-K
SiO2= Silicon Dioxide K = “dielectric constant” which measures the relative permittivity of a material.
Flip Chip BGA Package
LeadLead--free Flipfree Flip--Chip Package Technology Chip Package Technology ChallengesChallenges
Many Challenges had to be overcome to remove the remaining 5% of Lead (Pb)
DiePassivation
SubstrateSubstrateSolder Resist
Flip-Chip Bump
Solder Joint Cracking
Silicon Protection
Die Under Fill Process
Low-K ILD Cracking
Bump to Bump Bridging
Solders containing lead have been replaced with a copper column and lead-free solder
Traditional High-Lead Bumps Lead-free Advanced Bump Metallurgy
Introducing IntelIntroducing Intel’’s 45nm 100% Leads 45nm 100% Lead--Free Free TechnologyTechnology
Tin-Silver-CopperSolder
Copper Bump
Copper PadCopper Pad
Lead-TinSolder
Lead Elimination SummaryLead Elimination Summary
–– Intel has removed 100 percent of the lead across its entire Intel has removed 100 percent of the lead across its entire portfolio of packages in its 45nm family of microprocessors portfolio of packages in its 45nm family of microprocessors –– …… 65nm chipsets will transition to 100% Lead65nm chipsets will transition to 100% Lead--free in 2008free in 2008
–– IntelIntel’’s 45nm His 45nm Hi--k metal gate process technology represents a k metal gate process technology represents a dramatic transition to new materials that enable energy dramatic transition to new materials that enable energy efficient performance microprocessorsefficient performance microprocessors
–– IntelIntel’’s family of 45nm microprocessors will begin production in s family of 45nm microprocessors will begin production in second half of 2007second half of 2007
–– IntelIntel’’s effort to eliminate lead in our products is part of broader s effort to eliminate lead in our products is part of broader strategy to support an environmentally sustainable futurestrategy to support an environmentally sustainable future
For further information on Intel's lead free For further information on Intel's lead free technology, please visittechnology, please visit
www.intel.comwww.intel.com/technology/silicon/technology/silicon
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
Improving on a Planar TransistorImproving on a Planar Transistor
In planar devices onIn planar devices on--current current is mostly carried in a thin top is mostly carried in a thin top layerlayer
Body current is a source of Body current is a source of leakage when the device is leakage when the device is offoff
MainCurrent
BodyCurrent
An ideal transistor would have An ideal transistor would have a gate surround a very thin a gate surround a very thin channelchannel
This gives the highest on to off This gives the highest on to off ratio & therefore ratio & therefore highest highest power efficiencypower efficiency
DrainSource
Gate Gate Insulator
Tsi
GATE
Source Drain
LG
Bulk or Thick SOI
Gate Insulator
Fully Depleted Transistor Structures Fully Depleted Transistor Structures
Fully depleted thinFully depleted thin--body devices improve SCE performance.body devices improve SCE performance.TriTri--Gate is the most favorable architecture for LGate is the most favorable architecture for LGG scaling.scaling.
LG
HSi
Gate
GateGateSource
Drain
WSi
Non Planar Tri-Gate
1. FIN WSi is wider than planar TSi
2. Self-Aligned gates3. Bulk-Si or SOI
1. Ultra thin Tsi2. Limited to SOI
Planar Single Gate(FDSOI)
1. Wider Tsi than planar2. Non Self-aligned
Planar Double-Gate
TriTri--Gate Critical DimensionsGate Critical Dimensions
LeffN+ N+
Weff
WSi
Top Gate
Side
Gat
e
Side
Gat
e
High - k
LG
Hig
h-k
Hig
h-k
STI STI
HSi
IIDSATDSAT is normalized by Zis normalized by ZT T = W= WSiSi+ 2*H+ 2*HSiSi
TriTri--gate electrostatics strongly depend on the ratio of Lgate electrostatics strongly depend on the ratio of Leffeff / W/ Weffeff as defined by: as defined by: L L effeff = L= LGG –– 2 2 * X* XUDUD
WWeffeff = W= WSiSi + 2(+ 2(εεSiSi/ / εεOXOX)*T)*TOXOX
Metal Gate XUD
Insulator
High-k
InsulatorSiliconSilicon
TriTri--Gate Transistor:Gate Transistor:““A template for the futureA template for the future””
SOURCEDRAIN
GATE
Technical details presented at:Technical details presented at:ISSDM Conference, Japan, Sept 17, 2002ISSDM Conference, Japan, Sept 17, 2002
By Robert ChauBy Robert Chau
Source: IntelSOURCE
DRAIN
CHANNEL- Si, nanotubes, nanowires …
GATE
TriTri--Gate FIN Critical DimensionsGate FIN Critical Dimensions
HfO2 High-kDielectric
Near Mid-GapMetal Gate
HSi
WSi
SiFIN
CVD Poly
ZTotal
VLSI Symposium, 6-2006
TriTri--Gate OnGate On…………..
LeffN+ N+
Weff
WSi
Top Gate
Side
Gat
e
Side
Gat
e
High - k
LG
Hig
h-k
Hig
h-k
STI STI
HSi
IIDSATDSAT is normalized by Zis normalized by ZT T = W= WSiSi+ 2*H+ 2*HSiSi
TriTri--gate electrostatics strongly depend on the ratio of Lgate electrostatics strongly depend on the ratio of Leffeff / W/ Weffeff as defined by: as defined by: L L effeff = L= LGG –– 2 2 * X* XUDUD
WWeffeff = W= WSiSi + 2(+ 2(εεSiSi/ / εεOXOX)*T)*TOXOX
Metal Gate XUD
Insulator
High-k
InsulatorSiliconSilicon
Silicon
TriTri--Gate On Bulk!Gate On Bulk!
TriTri--Gate OnGate On…………..
LeffN+ N+
Weff
WSi
Top Gate
Side
Gat
e
Side
Gat
e
High - k
LG
Hig
h-k
Hig
h-k
STI STI
HSi
IIDSATDSAT is normalized by Zis normalized by ZT T = W= WSiSi+ 2*H+ 2*HSiSi
TriTri--gate electrostatics strongly depend on the ratio of Lgate electrostatics strongly depend on the ratio of Leffeff / W/ Weffeff as defined by: as defined by: L L effeff = L= LGG –– 2 2 * X* XUDUD
WWeffeff = W= WSiSi + 2(+ 2(εεSiSi/ / εεOXOX)*T)*TOXOX
Metal Gate XUD
Insulator
High-k
SiliconSilicon
1. Tri-gate gives better off current and therefore less wasted power2. High k – metal gate gives both higher speed and less wasted power3. Strained Si produces higher speed and less wasted powerThe sum of all these pieces is once again world leading transistors
The Key is Optimizing the IntegrationThe Key is Optimizing the Integration
Wrap aroundGate
Source-drainFin
Column III Column V
•• Silicon in transistor channel is replaced by Silicon in transistor channel is replaced by ““IIIIII--V compound V compound semiconductorsemiconductor””
•• Result is much higher electron mobility, meaning significant Result is much higher electron mobility, meaning significant performance and power improvementsperformance and power improvements
Compound SemiconductorsCompound Semiconductors
Si = SiliconAl = AluminumGa= GalliumIn = IndiumP = PhosphorousAs = ArsenicSb = Antimony
Increasing Electron MobilityIncreasing Electron MobilityIncreased mobility in the transistor channel leads to higher Increased mobility in the transistor channel leads to higher performance and less energy consumptionperformance and less energy consumption
505033338811
InSbInSbInAsInAsGaAsGaAsSiSi
Compound SemiconductorsCompound Semiconductors
Relative mobilityRelative mobility
Compound semiconductors have higher electron mobility Compound semiconductors have higher electron mobility than Si; InSb (indium antimonide) is highest of all than Si; InSb (indium antimonide) is highest of all
OXDSAT CLWI ⋅⋅∝ µ
III/V is a 2015 Transistor option• 3x faster or 10x lower power• Integration with silicon key
CMOS to continue for 15CMOS to continue for 15--20 years or more;20 years or more;MooreMoore’’s Law could be extended indefinitely via new s Law could be extended indefinitely via new
architectures, heterogeneous integration, 3Darchitectures, heterogeneous integration, 3D
0.2um InSb 0.2um NMOSPo
wer
Con
sum
ptio
n
0.2um InSb 0.2um NMOS
Tran
sist
orS
peed
(standard transistor) (standard transistor)
Looking ahead
IEDM 2004
Depletion and Enhancement ModeDepletion and Enhancement Mode
A novel gate recess process is used to fabricate A novel gate recess process is used to fabricate enhancement mode InSb enhancement mode InSb QWFETsQWFETs
InSb QW
Semi-insulating GaAs substrate for epitaxial growth
AlxIn1-xSb barrier
Source Drain
Gate
Depletion mode Depletion mode (Normally ON)(Normally ON)
Semi-insulating GaAs substrate for epitaxial growth
AlxIn1-xSb barrier
RecessedGate
Source Drain
Enhancement mode Enhancement mode (Normally OFF)(Normally OFF)
Etch Stop Layer
IEDM 2005
Speed, Power, PerformanceSpeed, Power, Performance
InSb InSb QWFETsQWFETs show > 10x reduction in active power show > 10x reduction in active power dissipation compared to Si MOSFETsdissipation compared to Si MOSFETs
50
100
150
200
250
300
350
10 100 1000
DC Power Dissipation [µW/µm]
Cut-
off Fr
eque
ncy,
f T [
GH
z]
InSb E-mode QWFET (LG = 85nm) VDS = 0.3V, 0.5V, 0.6V
Silicon MOSFET (LG = 60nm)VDS = 0.5V, 0.7V, 0.9V, 1.2V
50
100
150
200
250
300
350
10 100 1000
DC Power Dissipation [µW/µm]
Cut-
off Fr
eque
ncy,
f T [
GH
z]
InSb E-mode QWFET (LG = 85nm) VDS = 0.3V, 0.5V, 0.6V
Silicon MOSFET (LG = 60nm)VDS = 0.5V, 0.7V, 0.9V, 1.2V
10X power 1.5X
spe
ed
Benchmarking InSb Benchmarking InSb QWFETsQWFETs
InSb transistors show significant improvement in intrinsic gaInSb transistors show significant improvement in intrinsic gate delay and te delay and energyenergy--delay product over Si MOSFETs at equivalent gate lengthdelay product over Si MOSFETs at equivalent gate length
1E-23
1E-22
1E-21
1E-20
1E-19
1E-18
1E-17
1 10 100 1000 10000
Gate Length LG [nm]En
ergy
x D
elay
/ W
idth
[Js
/m]
Si MOSFETsDepletion mode InSbEnhancement InSb
0.1
1
10
100
1 10 100 1000 10000Gate Length, LG [nm]
Intr
insi
c G
ate
Del
ay,
CV/
I [
ps] Si MOSFETs
Enhancement mode InSb
Depletion mode InSb
20
Integration on Si PlatformIntegration on Si Platform
Current research on incorporation of new transistor onto Current research on incorporation of new transistor onto the existing Si platformthe existing Si platform
III-V semiconductor (InSb)
Buffer
Si substrate
source drain
90 nm65 nm
45 nm32 nm
20032005
20072009
2011+
Manufacturing Development Research
InnovationInnovation--Enabled Enabled Technology PipelineTechnology Pipeline
Future options subject to change
Tri-Gate
S
G
D
III-V
S
Carbon Nanotube FET
50 nm35 nm
SiGe S/DStrained Silicon
SiGe S/D2nd generation
Strained Silicon
20 nm 10 nm
5 nm
Nanowire
Metal Gate
High-k
High-kMetal gate
Moore’s Law = Transistor Budget +
Lowest Power and Lowest Cost
OutlineOutline
IntelIntel’’s Silicon R&D Pipelines Silicon R&D Pipeline
From Geometrical Scaling to Equivalent ScalingFrom Geometrical Scaling to Equivalent Scaling
DFMDFM
Getting the Lead outGetting the Lead out
Future Technology OptionsFuture Technology Options
SummarySummary
SummarySummaryIntel’s R&D pipeline will sustain Moore’s Law for the foreseeable future
45 nm high-k + metal gate is the most significant innovation in transistor technology in 40 yearsIntel has removed 100 percent of the lead across its Intel has removed 100 percent of the lead across its entire portfolio of packages in its 45nm family of entire portfolio of packages in its 45nm family of microprocessors microprocessors
–– …… 65nm chipsets will transition to 100% Lead65nm chipsets will transition to 100% Lead--free in 2008free in 2008
Intel continues its unwavering commitment to support R&D for future technologies and to deliver the benefits of Moore’s Law to our customers
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