sigda publications on cd-rom: 1996 international symposium...
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SIGDA Publications on CD-ROM:
1996 International symposium onLow Power Electronics and Design
Doubletree Hotel at Fisherman’s WharfMonterey, CA
August 12-14, 1996
ISLPED‘96 Proceedings © 1996 by IEEE. All rights reserved. No part of this material may be reproduced in any form, nor may it be stored in a retrievalsystem or transmitted in any form without written permission of IEEE.
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ISLPED96:
Cover Page Front Matter Table of Contents Session Index Author Index
Session Index
Session 1: Low Power Integrated SystemsSession 2: Power MetricsSession 3: Low Power Memory Design TechniquesSession 4: Power Estimation TechniquesSession 5: PostersSession 6: Technologies for Low PowerSession 7: Synthesis Techniques for Low PowerSession 8: Low Power Systems and Integrated ToolsSession 9: PostersSession 10: Manufacturing Variability IssuesSession 11: Low Power ConvertersSession 12: Clock-Related Power OptimizationSession 13: PostersSession 14: Analog TechniquesSession 15: Power Estimation, Coding, and TestabilitySession 16: Digital Signal ProcessingSession 17: Low Voltage and Adiabatic Design
CONTENTS
Session 1: Low Power Integrated SystemsChair.- Jan Rabaey, University of California at Berkeley
Keynote Paper:High Performance, Low Power Processor Design
Dan Dobberpuhl, Digital Equipment Corp ..............................................................................11
Low Power Systems for Wireless MicrosensorsK. Bult, A. Burstein, D. Chang, M. Dong, M. Fielding, E. Kruglick, J. Ho, F.Lin, T. Lin, W. Kaiser, H. Marcy, R. Mukai, P. Nelson, F. Newburg, K.
Pister, G. Pottie, H. Sanchez, 0. Stafsudd, K. Tan, S. Xue, J. Yao, K. Sohrabi, G. Yung, University of California at Los Angeles...................................................................17
A Low Power Architecture for Wireless Multimedia Systems: Lessons Learned From Building aPower Hog
W. Mangione-Smith, P. Ghang, S. Nazareth, P. Lettieri, W. Boring, R. Jain, University of California at Los Angeles...................................................................................23
Session 2: Power MetricsChair:. Massoud Pedram, University of Southern California
Invited Paper:High-Level Power Estimation
Paul Landman, Texas Instruments.............................................................................................29
A Power Metric for Mobile SystemsT. Martin, D. Siewiorek, Carnegie Mellon University................................................................37
Lower Bounds on Power Dissipation for DSP Algorithms N. Shanbhag, University of Illinois at Urbana..........................................................................43
Session 3: Low Power Memory Design TechniquesChair: Katsuro Sasaki, Hitachi America, Ltd.
A 0.5V/100 MHz Over-Vcc Grounded Data Storage (OVGS) SRAM Cell Architecture withBoosted Bit-line and Offset Source Over-Driving Schemes
H. Yamauchi, T. Iwata, H. Akamatsu, A. Matsuzawa, Matsushita ElectricIndustrial Co.............................................................................................................................49
Energy Recovery for the Design of High-Speed, Low-Power Static RAMsN. Tzartzanis, W. Athas, USC/ISI ...........................................................................................55
A 1-V 1-Mb SRAM for Portable EquipmentH. Morimura, N. Shibata, NTT LSI Laboratories.....................................................................61
Session 4: Power Estimation TechniquesChair: Farid Najm, University of Illinois at Urbana
A Novel Methodology for Transistor-Level Power EstimationS. Huang, K. Cheng, K. Chen, T. Lee, University of Califomia at Santa Barbaraand Fujitsu Laboratories of America .......................................................................................67
Statistical Estimation of Average Power Dissipation in CMOS VLSI Circuits UsingNonparametric Techniques
L. Yuan, C. Teng, S. Kang, University of Illinois at Urbana....................................................73
Switching Activity Analysis for Sequential Circuits Using Boolean Approximation MethodT. Uchino, F. Minami, M. Murakata, T. Mitsuhashi, Tosbiba Corp.........................................79
Session 5: PostersChair: Suresh Rajgopal, Intel Corp.
Transition Reduction in Carry-Save Adder Trees P. Larsson, C. Nicol, Bell Laboratories.....................................................................................85
250-600 Mhz 12b Digital Filters in 0.8-0.25um Bulk and SOI CMOS TechnologiesL. Thon, G. Shahidi, W. Rausch, G.Coleman, D. Tang, D. Schepis, R. Schulz,F. Assadaragin, IBM Almaden Research Center and IBM Microelectronics ...........................89
A Comparison of CMOS Implementations of an Asynchronous Circuits Primitive: the C-elementM. Shams, J. Ebergen, M. Elmasry, University of Waterloo....................................................93
Design Techniques for High Performance, Energy Efficient Control Logic U. Ko, A. Hill, P. Balsara, Texas Instruments..........................................................................97
Energy-Recovery CMOS for Highly Pipelined DSP DesignsW. Athas, W. Liu, J. Svensson, USC/ISI...............................................................................101
A Sub-CV2 Pad Driver with 10 ns Transition TimeL. Svensson, W. Athas, R. Wen, USC/ISI..............................................................................105
Gate-Level Current Waveform Simulation of CMOS Integrated CircuitsA. Bogliolo, L. Benini, G. De Micheli, B. Ricco, Stanford University..................................109
Effects of Correlations on Accuracy of Power Analysis - An Experimental StudyP. Schneider, S. Krishnamoorthy, Technical University of Munich and Synopsys Inc..........113
Basic Experimentation on Accuracy of Power Estimation for CMOS VLSI CircuitsT. Ishihara, H. Yasuura, Kyushu University...........................................................................117
Simulation Based Architectural Power EstimationS. Katkoori, R. Vemuri, University of Cincinnati..................................................................121
Short Circuit Power Consumption of GlitchesD. Rabe, W. Nebel, University of Oldenburg.........................................................................125
Session 6: Technologies for Low PowerChair: Hans Stork, HP Labs
A Graded-Channel MOS (GCMOS) VLSI Technology for Low Power DSP ApplicationsJ. Ma, H. Liang, M. Kaneshiro, C. Kyono, R. Pryor, K. Papworth, S. Cheng,Advanced Custom Technologies, Motorola Inc ....................................................................129
Fabrication and Performance of Mesa InterconnectL. Carley, D. Guillou, S. Santhanam, Carnegie Mellon University........................................133
Floating Body Effects in Partially-Depleted SOI CMOS CircuitsP. Lu, J. Ji, C. Chuang, L. Wagner, C. Hsieh, J. Kuang, L. Hsu, M. Pelella, S.Chu, C. Anderson, IIBM T. J. Watson Research Center .......................................................139
An Investigation of the Impact of Technology Scaling on Power Wasted as Short Current inLow Voltage CMOS
A. Chatterjee, M. Nandakumar, I. Chen, Texas Instruments..................................................145
Session 7: Synthesis Techniques for Low PowerChair: Jason Cong, University of California at Los Angeks
Concurrency-Oriented Optimization for Low-Power Asynchronous SystemsL. Plana, S. Nowick, Columbia University.............................................................................151
Energy Minimization Using Multiple Supply VoltagesJ. Chang, M. Pedram, University of Southern California.......................................................157
Symbolic Computation of Logic Implications for Technology-Dependent Low-Power SynthesisR. Bahar, M. Burns, G. Hachtel, E. Macii, H. Shin, F. Somenzi, BrownUniversity and University of Colorado at Boulder.................................................................163
Integrated Resynthesis for Low Power0. Coudert, R. Haddad, Synopsys Inc.....................................................................................169
Evening Panel SessionOrganizers: Sayfe Kiaei, Motorola Inc. and Srinivas Devadas, MIT
Topic: Which Has Greater Potential Power Impact: High-Level Design and Algorithms orInnovative Low Power Technology?
James Burr, Sun Micro Systems, Laszlo Gal, Motorola Inc., Ramsey Haddad,Synopsys Inc., Jan Rabaey, University of Califomia at Berkeley, Bruce Wooley,Stanford University................................................................................................................175
Session 8: Low Power Systems and Integrated ToolsChair: Mark Horowitz, Stanford University
Invited Paper:How to Design Low-Power Digital Cellular Phones
K. Mashiko, Mitsubishi Electric Corp....................................................................................177
Invited Paper:What Is the State of the Art in Commercial CAD Tools for Low Power?
K. Keutzer, 0. Coudert, R. Haddad, Synopsys Inc.................................................................181
Session 9: PostersChair: Anantha Chanrakasan, MIT
Accurate Evaluation of the CMOS Short-Circuit Power Dissipation for Short-Channel DevicesL. Bisdounis, O. Koufopavlou, S. Nikolaidis, University of Patras.......................................189
Circuit Techniques for Low-Power CMOS GSIA. Bhavnagarwala, V. De, D. Austin, J. Meindl, Georgia Instituteof Technology........................................................................................................................193
Device Design for Low Power Electronics with Accurate Deep Submicrometer MOSFET ModelsK. Chen, Y. Cheng, C. Hu, University of California at Berkeley...........................................197
Energy Delay Analysis of Partial Product Reduction Methods for Parallel MultiplierImplementation
R.V.K. Pillai, D. Al-Khalili, A. J. Al-Khalili, Concordia University .....................................201
Low-Power Radix-4 DividerA. Nannarelli, T. Lang, University of California at Irvine..................................................... 205
Power Comparisons for Barrel ShiftersK. Acken, M. Irwin, R. Owens, Pennsylvania State University.............................................209
Interlaced Accumulation Programming for Low Power DSPH. Kojima, A. Shridhar, Hitachi America, Ltd ......................................................................213
Low-power Adaptive Filter Architecture via Strength ReductionM. Goel, N. Shanbhag, University of Illinois at Urbana........................................................217
Leap Frog MultiplierS. Mahant-Shetti, C. Lemonds, P. Balsara, Texas Instruments...............................................221
Session 10: Manufacturing Variability IssuesChair: Paul Solomon, IBM T.J. Watson Research Center
Invited Paper:Manufacturability of Low Power CMOS Technology Solutions
A.J. Strojwas, M. Quarantelli, J. Borel, C. Guardiani, G. Nicollini, G. Crisenza,B. Franzini, J. Wiart, Carnegie Mellon University.................................................................225
Effects of Random MOSFET Parameter Fluctuations on Total Power ConssumptionX. Tang, V. De, J. Meindl, Georgia Institute of Technology..................................................233
The Impact of Intra-Die Device Parameter Variations on Path Delays and on the Design forYield of Low Voltage Digital Circuits
M. Eisle, J. Berthold, D. Schmitt-Landsiedel, R. Mahnkopf, Siemens AG............................237
Session 11: Low Power ConvertersChair: Lou Williams, Texas Instruments
12-b 125 MSPS CMOS D/A Designed for Spectral PerformanceD. Mercer, L. Singer, Analog Devices Semiconductor...........................................................243
Implementation of a Micro Power 15-bit Floating-Point A/D ConverterL. Grisoni, A. Heubi, P. Balsiger, F. Pellandini, University of Neuchatel..............................247
Micro Power "Relative Precision" 13 bits Cyclic RSD A/D ConverterA. Heubi, P. Balsiger, F. Pellandini, University of Neuchatel................................................253
Session 12: Clock-Related Power OptimizationChair: Chi-Ying Tsui, Hong Kong Univesity of Science and Technology
Mixed-Phase Retiming for Low Power DesignM. Papaefthymiou, K. Lalgudi, Yale University....................................................................259
Clock Skew Optimization for Peak Current ReductionP. Vuillod, L. Benini, A. Bogliolo, G. DeMicheli, Stanford University.................................265
Simultaneous Buffer and Wire Sizing for Performance and Power OptimizationJ. Cong, C. Koh, K. Leung, University of Califomia at Los Angelesand Intel Corporation .............................................................................................................271
Session 13: PostersChair: David Allstot, Oregon State University
A Low Power High Performance Switched-Current MultiplierD.M.W. Leenaerts, G.H.M. Joordens, J.A. Hegt, Eindhoven University ofTechnology ............................................................................................................................277
Low-Power Frequency Multiplier With One Cycle Lock-in Time and 100ppm FrequencyResolution, for Systern Power-Management
R. Fried, Z. Azmanov, Swiss Federal Institute of Technology...............................................281
A 1.5V Class AB Output BufferF. You, S. Embabi, E. Sanchez-Sinencio, Texas A&M University........................................285
Low-Power Mapping of Behavioral Arrays to Multiple MemoriesP. Panda, N. Dutt, University of California at Irvine..............................................................289
Logic Synthesis Using Power-Sensitive Don't Care SetsC. Lennard, P. Buch, A. Newton, University of California at Berkeley.................................293
lmplication-Based Gate-Level Synthesis for Low PowerD. Pradhan, M. Chatterjee, M. Swarna, W. Kunz, Texas A&M University...........................297
Controller Re-Specification to Minimize Switching Activity in Controller/Data Path CircuitsA. Raghunathan, S. Dey, N. Jha, K. Wakabayashi, C&C Research Laboratories,NEC........................................................................................................................................301
Session 14: Analog TechniquesChair: Bruce Woole, Stanford University
A 200 uA, 78 MHz CMOS Crystal-Oscillator Digitally Trimmable to 0.3 PPMQ. Huang, P. Basedau, Swiss Federal Institute of Technology...............................................305
Substrate Noise Influence on Circuit Performance in Variable Threshold-Voltage SchemeT. Kuroda, T. Fujita, S. Mita, Y. Hamura, T. Mori, K. Matsuo, M. Kakumu,T. Sakurai, Toshiba Corp........................................................................................................309
A Low Power Switching Power Supply for Self-Clocked SystemsG. Wei, M. Horowitz, Stanford University.............................................................................313
Design of a Programmable Temperature Monitoring Device for Tagging Small FishG. Fischer, J. Daly, C. Yang, C. Recksiek, K. Friedland, University of RhodeIsland .....................................................................................................................................319
Session 15: Power Estimation, Coding, and TestabilityChair: M. Fujita, Fujitsu Laboratories of America, Inc.
Entropic Bounds on FSM SwitchingA. Tyagi, Iowa State University.............................................................................................323
High-Level Power Estimation and the Area Complexity of Boolean FunctionsM. Nemani, F. Najm, University of Illinois at Urbana...........................................................329
Two Dimensional Codes for Low PowerM. Stan, W. Burleson, University of Massachusetts at Amherst............................................335
Low Power, Testable Dual Edge Triggered Flip-FlopsR. Llopis, M. Sachdev, Philips Research Laboratories...........................................................341
Session 16: Digital Signal ProcessingChair: Mary Jane Irwin, Pennsylvania State University
Invited Paper:Data Driven Signal Processing: An Approach for Energy Efficient Computing
A. Chandrakasan, V. Gutnik, T. Xanthopoulos, MIT.............................................................347
Stage-Skip Pipeline: A Low Power Processor Architecture Using a Decided Instruction BufferM. Hiraki, R. Bajwa, H. Kojima, D. Gorny, K. Nitta, A. Shridhar, K. Sasaki,K. Seki, Hitachi Central Research Lab. and Hitachi America, Ltd.........................................353
Power Exploration for Data Dominated Video ApplicationsS. Wuytack, F. Catthoor, L. Nachtergaele, H. De Man, IMEC...............................................359
Session 17: Low Voltage and Adiabatic DesignChair:. Peter Verhofstadt, SRC
Invited Paper:Practical Performance/Power Alternatives within an Existing CMOS Technology Generation
K. Bernstein, J. Bertsch, W. Clark, T. Ellis-Monaghan, L.Heller, E. Nowak,IBM Microelectronics Division..............................................................................................365
A Dynamic Energy Recycling Logic Family for Ultra-Low-Power Gigascale Integration (GSI)V. De, J. Meindl, Georgia Institute of Technology................................................................371
Comparison of High Speed Voltage-Scaled Conventional and Adiabatic CircuitsD. Frank, IBM T. J. Watson Research Center........................................................................377
Static Power Driven Voltage Scaling and Delay Driven Buffer Sizing in Mixed Swing QuadRailfor Sub-IV 1/0 Swings
R. Krishnamurthy, I. Lys, L. Carley, Carnegie Mellon University.........................................381
AUTHOR INDEX
Acken 209 Cong 271Akamatsu 49 Coudert 169,181A.J. Al-Khalili 201 Crisenza 225D. Al-Khalili 201 Daly 319Anderson 139 V.K. De 193,233,371Assadaraghi 89 De Man 359Athas 55,101,105 De Micheli 109,265Austin 193 Dey 301Azmanov 281 Dobberpuhl 11Bahar 163 Dong 17Bajwa 353 Dutt 289Balsara 97,221 Ebergen 93Balsiger 247,253 Eisele 237Basedau 305 Ellis-Monaghan 365Benini 109,265 Elmasry 93Bernstein 365 Embabi 285Berthold 233 Fielding 17Bertsch 365 Fischer 319Bhavnagarwala 193 Frank 377Bisdounis 189 Franzini 225Bogliolo 109,265 Fried 281Borel 225 Friedland 319Boring 23 Fujita 309Buch 293 Gal 175Bult 17 Ghang 23Burleson 335 Goel 217Burns 163 Gorny 353Burr 175 Grisoni 247Burstein 17 Guardiani 225Carley 133, 381 Guillou 133Catthoor 359 Gutnik 347Chandrakasan 347 Hachtel 163D. Chang 17 Haddad 169,181J. Chang 157 Hamura 309A. Chatterjee 145 Hegt 277M. Chatterjee 297 Heller 365K-T. Cheng 67 Heubi 247,253S. Cheng 129 Hill 97Y. Cheng 197 Hiraki 353K-C. Chen 67 Ho 17I-C. Chen 141 Horowitz 313K. Chen 197 Hsieh 139Chu 139 Hsu 139Chuang 139 Hu 197Clark 365 S-Y. Huang 67Coleman 89 Q. Huang 305
Irwin 209 Matsuo 309Ishihara 117 Matsuzawa 49lwata 49 Meindl 193,233,371Jain 23 Mercer 243Jha 301 Minami 79Ji 139 Mita 309Joordens 277 Mitsuhashi 79Kaiser 17 Mori 309Kakumu 309 Morimura 61Kaneshiro 129 Mukai 17Kang 73 Murakata 79Katkoori 121 Nachtergaele 359Keutzer 181 Najm 329Ko 97 Nannarelli 205Koh 271 Nandakumar 145Kojima 213,353 Nazareth 23Koufopavlou 189 Nebel 125S. Krishnamoorthy 113 Nelson 17R. Krishnamurthy 381 Nemani 329Kruglick 17 Newburg 17Kuang 139 Newton 293Kunz 297 Nicol 85Kuroda 309 Nicollini 225Kyono 129 Nikolaidis 189Lalgudi 259 Nitta 353Landman 29 Nowak 365Lang 205 Nowick 151Larsson 85 Owens 209Lee 67 Panda 289Leenaerts 277 Papaefdiymiou 259Lemonds 221 Papworth 129Lennard 293 Pedram 157Lettieri 23 Pelella 139Leung 271 Pellandini 247,253Liang 129 Pillai 201F. Lin 17 Pister 17T.H. Lin 17 Plana 151Liu 101 Pottie 17Llopis 341 Pradhan 297Lu 139 Pryor 129Lys 381 Quarantelli 225Ma 129 Rabaey 175Macii 163 Rabe 125Mahant-Shetti 221 Raghunathan 301Mahnkopf 237 Rausch 89Mangione-Smith 23 Recksiek 319Manne 165 Ricco 109Marcy 17 Sachdev 341Martin 37 Sakurai 309Mashiko 177 Sanchez 17
Sanchez-Sinencio 285Santhanam 133Sasaki 353Schepis 89Schmitt-Landsiedel 237Schneider 113Schulz 89Seki 353Shahidi 89Shams 93Shanbhag 43,217Shibata 61Shin 163Shridhar 213,353Siewiorek 37Singer 243Sohrabi 17Somenzi 163Stafsudd 17Stan 335Strojwas 225Svensson 101,105Swarna 297Tan 17D. Tang 89
X. Tang 233Teng 73Thon 89Tyagi 323Tzartzanis 55Uchino 79Vemuri 121Vuillod 265Wagner 139Wakabayashi 301Wei 313Wen 105Wiart 225Wooley 175Wuytack 359Xanthopolous 347Xue 17Yamauchi 49Yang 319Yao 17Yasuura 117You 285Yuan 73Yung 17