september 8-14, 20027 th workshop on electronics for lhc1 channel control asic for the cms hadron...

September 8-14, 2002 7th Workshop on Electronics for LHC 1

Channel Control ASIC for the CMS Hadron Calorimeter Front

End Readout Module

Ray Yarema, Alan Baumbaugh, Ahmed Boubekeur, John Elias,

Theresa Shaw

September 12, 2002


CCA Use in CMS

• CCAs are used for processing both HPD and PMT signals

• CCA provides control and interface for QIE ASICs which digitize charge input signals.

• CCAs and QIEs are mounted on the CMS Hadron Calorimeter Front End Readout Module

• CCAs and QIEs were designed at Fermilab


Front End Readout Module

• Two QIE chips interface to one CCA chip

• There are 3 CCA chips on a Front End Readout Module

• 3 CCAs feed data to 2 GOLs

QIE

CCA

QIE

QIE

QIE

QIE

QIE

CCA

CCA

Front End Readout ModuleFromHPD orPMT

VCSEL

VCSEL

GOL

GOL VCSEL


Hadron Calorimeter Front End Module


What is a QIE?(Charge Integrator and Encoder)

• QIE digitizes input signal over a wide dynamic range

• QIE operates in a 4 step pipeline mode

• The data is output as a 2 bit exponent and 5 bit mantissa along with the time slice information which is referred to as Cap ID

• QIE can be programmed to accept either positive (PMT) or negative (HPD) input charge

HPD Input

PMT InputQIE

Exponent

Mantissa

Cap ID

2

5

2

QIE Clock


Primary Functions of CCA

• Send individually programmable delayed clocks to each of the QIEs, to correct for time differences within the hadron calorimeter (58 nsec max)

• Accept exponent and mantissa information from 2 QIEs, align the data and send the data to a gigabit serializer that drives an optical link


Other CCA Features

• Provide RBX serial interface, similar to I2C, for programming features

• See that QIEs are operating in sync by checking QIE capacitor IDs

• Force QIE into fixed range instead of autoranging for test purposes

• Adjust QIE pedestal level to correct for HPD leakage

• Reset QIEs

• Place QIE in calibration mode

• Issue test pulse triggers of programmable polarity for either HPD or PMT

• Flag zero crossing counter check error

• Test pattern registers to check operation of DAQ


CCA Connections

• Figure on the right shows connections for 1 QIE feeding ½ of a CCA followed by the GOL

• Chip address lines RBX_A are programmed by 6 hard wire connections on circuit board

QIE EXPaQIE MANTaQIE CAPIDa

QIE CLKaQIE RESETaPED_DACa

QIE_RANGECALIB_MODE

EN_QIE_RANGE

To second QIE

1/2CCA

QIEwithIntegratedFADC

FromHPDor PMT

TEST PULSEa

RBX_CLK

LHC ClockBC_Zero

One setCCAControlSignals

TX_DATA

DATACNTRL

SEND_FF18

2

2

2

2

5

4

RBX_DATA

RBX_A 6

Repeatedfor 2nd QIE


Operation of CCA Blocks

• RBX interface and registers

• Delay Lock Loop for QIE clock adjustment

• QIE data alignment and data formatting for GOL

• Other miscellaneous circuits


RBX Interface and Registers

• CCA chip address is set by 6 hard wire connections on PCB

• RBX bus is a 2 wire communication interface which is similar to I2C

• All data is down loaded, 8 bits at a time, through RBX_DATA line with each RBX bus cycle

• RBX clock is intended to run at 100Kbits/sec

• RBX data is transferred either to or from the 1)Pointer Register or the 2) Data Register

• The Pointer Register points to 1 of 28 eight bit internal registers.

• Data Register contains data to be written or read from pointer address location

• The Pointer Register automatically increments after each data transfer to reduce chip communication overhead

• All registers designed with SEU tolerant latches to reduce SEU effects


Control Register Space and QIE Clock Adjustment

Address

DataRBX_Pointer

RBX_DATA

RBX Bus Interface Control Register SpaceRBX CLK

RBX_DATA

CCA Internalcontrols

Control Register(8 differentcontrols)

CALIB_MODE

EN_QIE RANGE

QIE_RANGE

AlignmentRegisters

Pedestal DACRegister

4

DLL Tap SelectRegister QIEa

DLL Tap SelectRegister QIEb

QIEaCLK mux

PED_DACaPED_DACb

QIECLKa

QIEbCLK mux

QIECLKb

Test Pulse BunchMatch Register

Test PatternRegisters (20)

DelayLockLoop

LHCclock

Signal to QIEs

6

2

2

2

4

4

5

5

CCA addressis set by 6hard wireconnectionson PC board

RBX_A


CCA Internal Control Registers

• Control register – 1 register – sets various internal CCA controls and control settings for QIEs

• Alignment Control registers – 2 registers, 1 for each of 2 QIEs – selects various timing options to permit channel operation with timing differences up to 58 ns.

• Pedestal DAC Register – 1 register for 2 QIEs – 4 bits of adjustment for each of 2 QIE’s to correct for HPD leakage current changes

• DLL Tap Select 0 Register – 1 register – choose clock delay for QIE0 in 1 ns increments from 0 to 25 ns

• DLL Tap Select 1 Register – 1 register – choose clock delay for QIE1 in 1 ns increments from 0 to 25 ns


CCA Internal Control Registers(continued)

• Test Bunch Counter Match Register -1 register - contains the Bunch Count at which a test pulse should be fired for the 2 QIEs, providing the “Enable Test Pulse” bit has been set in the Control Register

• Test Pattern Registers – 20 registers – contains data or test patterns that are sent from the CCA through the GOL for 2 reasons:– To verify proper DAQ communication

– To load data to a specific chip location and verify that the optical cable has been connected to the correct channel


Typical Download to CCA Via RBX Bus

A7:A2 (Chip address) A1=0 (Pointer) A0=0 (Write)

A7:A2 (Internal register address loaded into Pointer Register)

A7:A0 (Data to be loaded into nth Internal Register)

A7:A2 (Chip address) A1=1 (Data) A0=0 (Write)

A7:A0 (Data to be loaded into n+1 Internal Register)

Word #

1

2

3

4

5

6Pointerregisterincrementsautomatically


Delay Locked Loop

• Delay Locked Loop has 25 one nsec taps to provide fine control of QIE clocks

• Each tap stage is comprised of 2 inverters

1 25

25 to 1 Multiplexer

PhaseDetector

ChargePump

LoopFilter

QIEClock4

Delayselect

Control voltage

Inputclock


QIE Data Alignment and Transmission

• Bits from Control Register set 4 muxs in Data Alignment block for proper data alignment

• Cap IDs are checked for proper synchronization

• Data Mux sends either Orbit message or QIE data at 40 MHz

QIE_EXPa

QIE_MANTa

QIE_CAPIDa

QIE_EXPb

QIE_MANTb

QIE_CAPIDb

FromQIEa

FromQIEb

LHC_CLOCK

QIE DataAlignment

DataMux

QIECap IDCheck

Sync_CapIDa

Sync_CapIDb

CapIDerror

QIE DATA 18

TX_DATA

SEND FF

CNTRL

DATA

Signalsto GOL

LHC_CLOCK

Mux controls

Orbit message

Controls from alignment register 7

18

18

2

2

2

2

2

2

5

5


Typical Data Transmission

• When Bunch Crossing Zero is received, an Orbit Message is sent and at the same time the QIEs are reset with Cap ID=0.

• QIE data is sent after the Orbit Message

C a p ID e rro r(1 ) B u n ch e rro r(1 )C ro s s in g n u m b e r(1 2 )F ill F ra m e (1 8 o n e s )

D a ta (1 8 b its )

D a ta (1 8 b its )

Ir re le v a n t(4 )

F i ll F ra m e (1 8 o n e s )

D a ta (1 8 b its )

0

1

6970

35623563

Next Orbit MessageOrbitmessage

QIE Data

Orbitmessage

Word Count


Other CCA Circuits

• Bunch Counter – 12 bit counter that starts at 0 and increments with the LHC clock. Before reset at next Bunch Crossing=0, counter value is compared to expected value in the Event Checker. Any errors are flagged. The BC value is also stored for transmission in Orbit Message

• Test Pulse Trigger Comparator – Produces a Send_Test_Pulse signal when number in the Test Pulse Bunch Count Match Register equals the Bunch Counter number. Pulse is 1 cycle long. Polarity is settable through a bit in the Control Register.

• Synchronizer – Synchronizes test pulses for the 2 QIE which have different clock delays so the test pulse occurs in the same time slice. Also Syncs QIE reset pulses.


QIE

_EX

Pa

QIE

_MA

NTa

QIE

_CA

PID

a

QIE

_EX

Pb

QIE

_MA

NT

b

QIE

_CA

PID

b

Fro

mQ

IEa

Fro

mQ

IEb

LH

C_C

LO

CK

QIE

Dat

aA

lign

men

t

Dat

aM

uxQ

IEC

apID

Che

ck

Syn

c_C

apID

a

Syn

c_C

apID

b

Cap

IDer

ror

QIE

DA

TA18

TX

_DA

TA

SE

ND

FF

CN

TR

L

DA

TA

Sig

nals

toG

OL

LH

C_C

LO

CK

Mux

cont

rols

Con

trol

sfr

omal

ignm

entr

egis

ter

7

18

Add

ress

Dat

aR

BX

_Poi

nter

RB

X_D

AT

A

RB

XB

usIn

terf

ace

Con

trol

Reg

iste

rS

pace

RB

XC

LK

RB

X_D

ATA

Con

trol

Reg

iste

r(8

diff

eren

tco

ntro

lfun

ctio

ns)

CA

LIB

_MO

DE

EN

_QIE

RA

NG

E

QIE

_RA

NG

E

Ali

gnm

ent

Reg

iste

rs

Ped

esta

lDA

CR

egis

ter

4

DL

LTa

pS

elec

tR

egis

ter

QIE

a

DL

LTa

pS

elec

tR

egis

ter

QIE

b

QIE

aC

LK

mux

PE

D_D

AC

a

PE

D_D

AC

b

QIE

_CL

Ka

QIE

bC

LK

mux

QIE

_CL

Kb

Tes

tP

ulse

Bun

chM

atch

Reg

iste

rs

Tes

tPat

tern

Reg

iste

rs(2

0)D

elay

Loc

kL

oop

LH

Ccl

ock

Orb

itM

essa

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Bun

chC

ount

er(1

2bi

ts)

Eve

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ync

Che

ck

BC

_ZE

RO

Bun

chC

ount

Syn

cE

rror

Tes

tPul

seT

rigg

erC

ompa

rato

r

12S

end

test

puls

e

QIE

RE

SE

Ta

QIE

RE

SE

Tb

TE

ST

PU

LS

Ea

TE

ST

PU

LS

Eb

LH

C_C

LO

CK

BC

_Zer

o

Synchronizer

Ena

ble

Pol

arit

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BC

_Zer

oS

end

Fil

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Sel

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rbit

Mes

sage

sour

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7

2 4 4

5 5

RB

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ddre

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2 5 2 2 5 2

2 2

18

6

2 2

Sig

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to QIE

s

CC

Aad

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hard

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PC

boar

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CCA chip

• Aligent 0.5 u CMOS process

• 3.4 x 4.0 mm die

• 128 QFP, 14 x 20 mm

• Production run of 11400 parts (22800 channels)


Test Data

• 500 parts packaged for testing• 21 separate tests in test program• 200 parts measured to set cuts in test

program for power supply current (+/-15%) and delay time (+/- 2 ns)

• 227 parts were tested with cuts• 222 good parts for yield of 97.8%• Remaining 10, 900 parts to be packaged


Conclusion

• Production quantity of CCA has been received for the Hadron Calorimeter

• All performance specifications have been met

• The CCA has been successfully run on a Front End Module with the QIEs

• The yield from testing the first 200 parts is very high.


Acknowledgements

• The authors want to thank – Abder Mekkaoui for significant contributions

throughout the development of the CCA– William Wester and Christian Gingu in the

ASIC test group at Fermilab for the yield information that was used

– Jim Hoff and Alpana Shenai for layout assistance

– Al Dyer for his test assembly assistance

september 8-14, 20027 th workshop on electronics for lhc1 channel control asic for the cms hadron...

Documents

data formatting

data line

data transfer

i2call data

kbitssecrbx data

data registerthe pointer

qie capacitor idsforce

qie asics