valerio re, massimo manghisoni università di bergamo and infn, pavia, italy jim hoff, abderrezak...

Valerio Re, Massimo Manghisoni

Università di Bergamo and INFN, Pavia, Italy

Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema

Fermi National Accelerator Laboratory

Lodovico Ratti

Università di Pavia and INFN, Pavia, Italy

IEEE Nuclear Science Symposium, Puerto Rico, October 24 – 27, 2005

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors


V. Re: “FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors”

The FSSR2 chipThe FSSR2 chip Mixed-signal integrated circuit for the readout of silicon strip detectors Final step of R&D effort begun with the design of the prototype chip

FSSR

TSMC 0.25 µm CMOS technology with enclosed NMOS for radiation tolerance

128 analog channels, address, time, and magnitude information for all hits

Fast, self-triggered readout architecture with no analog storage, very similar to the FPIX2 chip (front-end for pixels in the BTeV experiment)

Designed for the BTeV Forward Silicon Tracker, FSSR2 is suitable for a wide range of applications with microstrip detectors

Mixed-signal integrated circuit for the readout of silicon strip detectors Final step of R&D effort begun with the design of the prototype chip

FSSR

TSMC 0.25 µm CMOS technology with enclosed NMOS for radiation tolerance

128 analog channels, address, time, and magnitude information for all hits

Fast, self-triggered readout architecture with no analog storage, very similar to the FPIX2 chip (front-end for pixels in the BTeV experiment)

Designed for the BTeV Forward Silicon Tracker, FSSR2 is suitable for a wide range of applications with microstrip detectors



Major requirementsMajor requirements

Data driven architecture – no trigger Operation at 132 ns (2% strip occupancy), 264, or 396 ns

(6 % strip occupancy) beam crossing Tolerance to total ionizing dose (5 Mrad) and single event

effects (SEU) Equivalent Noise Charge (ENC) < 1000 e rms @ CD = 20 pF

Threshold dispersion < 500 e rms Power < 4 mW/channel



The FSSR2 chipThe FSSR2 chip

7.5 mm x 5 mm, input pads with 50 m pitch 7.5 mm x 5 mm, input pads with 50 m pitch

Data outputInterface

ProgrammingInterface

Pixel Core Logic

Front-End



FSSR2 block diagramFSSR2 block diagram

• FSSR2 Core– 128 analog channels– 16 sets of logic, each

handling 8 channels– Core logic with BCO

counter (time stamp)• Programming Interface (slow

control)– Programmable registers– DACs

• Data Output Interface– Communicates with core

logic– Formats data output– Same as BTeV FPIX2 chip

• FSSR2 Core– 128 analog channels– 16 sets of logic, each

handling 8 channels– Core logic with BCO

counter (time stamp)• Programming Interface (slow

control)– Programmable registers– DACs

• Data Output Interface– Communicates with core

logic– Formats data output– Same as BTeV FPIX2 chip

128 cha nne ls of a na log c ircuits

16 se ts of logic e a chha ndling 8 a na log cha nne ls

Core Logic

To s ilicon s trip de te c tors

P rogra mming Inte rfa ce

DACs P rogra mma bleRe gis te rs

S te e ring LogicWord S e ria lize r

ClockControlLogic

Ne xtBlockWord

Co

reD

ata

Ou

tpu

tIn

terf

ace

BCO clock I/O Re a doutclock

High S pe e dO utput

BCO ctr

1 16



Analog channelsAnalog channels

+

CD

Cf

GfShaper

Preamplifier

Bias

BLR

CAC

Cinj

Cf1

Programmable Peaking time

Test Input(from Internal Pulser)

-

Programmable Gain

CR-(RC)2

Programmable BaselineRestorer

To 3-bit Flash ADC

Hit/NoHit Discriminator

Single-ended/Differentialconversion

Comparator

+

DAC

Threshold circuit

-Vth

Kill



Analog channelsAnalog channels

• Preamplifier– NMOS input device, W/L = 1500/0.45, ID = 500 A– Programmable charge sensitivity

• Integrator and shaper– Unipolar 2nd order semigaussian shaper– Four programmable shaping times (65, 85, 100, 125 nsec)

• Base Line Restorer– Cancellation of the baseline shift due to the tail in the shaper output signal – The BLR is selectable, so that it can be used only when signal occupancy

is high• Discriminator

– Binary information (hit / no hit)– Programmable differential threshold (chip wide)

• 3 bit Flash ADC– Pulse amplitude information for detector monitoring and calibration

• Preamplifier– NMOS input device, W/L = 1500/0.45, ID = 500 A– Programmable charge sensitivity

• Integrator and shaper– Unipolar 2nd order semigaussian shaper– Four programmable shaping times (65, 85, 100, 125 nsec)

• Base Line Restorer– Cancellation of the baseline shift due to the tail in the shaper output signal – The BLR is selectable, so that it can be used only when signal occupancy

is high• Discriminator

– Binary information (hit / no hit)– Programmable differential threshold (chip wide)

• 3 bit Flash ADC– Pulse amplitude information for detector monitoring and calibration



Digital sectionDigital section

Programming Interface• Accepts commands and data from serial input bus• Programmable registers hold input values for DACs

providing reference currents and voltages to the core (discriminator thresholds, test signal amplitude,…)

Data Output Interface• Serializes data from the core and transmits data off chip• Programmable number of output LVDS lines (1, 2, 4, 6)• Maximum data transmission rate 840 Mb/s• Output data word includes 3 bits for ADC pulse amplitude

information, 5 bits for the logic set number, 4 bits for strip number and 8 bits for hit BCO number (time stamp)



Test resultsTest results• The chip is fully functional and meets all specifications

• Power dissipation is 4 mW/channel

• The chip has been operated with a 70 MHz readout clock to provide 840 Mb output data rate.

• Threshold dispersion = 300 e rms (with BLR, high gain setting)

• ENC = 800 e rms

(CD = 20 pF, peaking time = 85 nsec, with BLR)



Shaper output responseShaper output response

Charge sensitivity at Charge sensitivity at shaper output:shaper output:

Low gain: 120 mV/fCLow gain: 120 mV/fC

High gain: 160 High gain: 160 mV/fCmV/fC

-0.1

-0.05

0

0 100 200 300 400 500 600 700 800

Low gain setting

tP = 65 ns

tP = 85 ns

tP = 100 ns

tP = 125 ns

Sha

per

outp

ut (

V)

Time (ns)

65 ns

125 ns



Baseline restorer Baseline restorer

-0.15

-0.1

-0.05

0

0 0.5 1 1.5 2 2.5 3

tP = 85 ns

High gain setting

shaper output

BLR output

VO

UT (

V)

Time (s)



Equivalent Noise ChargeEquivalent Noise Charge

0

500

1000

1500

2000

0 10 20 30 40 50

tp=65 ns tp=85 nstp=125 ns

EN

C [

e rm

s]

CD

[pF]

BLR deselected

ENC = 220 + 31 e/ pFENC = 200 + 25 e/ pFENC = 190 + 21 e/ pF



Equivalent Noise ChargeEquivalent Noise Charge

0

500

1000

1500

2000

0 10 20 30 40 50

BLR selected

BLR deselected

EN

C [

e rm

s]

CD

[pF]

Peaking time 85 ns

ENC = 230 + 28 e/ pF

ENC = 200 + 25 e/ pF The BLR improves The BLR improves the threshold the threshold

dispersion dispersion (AC coupling), but (AC coupling), but

increases noise increases noise

However, ENC is well However, ENC is well below the spec value below the spec value of 1000 e rms at of 1000 e rms at

CCDD = 20 pF. = 20 pF.



Radiation toleranceRadiation tolerance

FSSR prototype Irradiation with 27 MeV protons to a 1.9x1013 cm-2 fluence,

corresponding to a total ionizing dose of 5 MRad

After irradiation the chip remains fully functional with very little (< 10 %) degradation of critical parameters such as ENC and threshold dispersion

FSSR2 Irradiation with 60Co -rays to a total ionizing dose of 20 Mrad

(no bias applied during irradiation)

Chip fully functional after irradiation; noise and charge sensitivity are not affected

Threshold dispersion with BLR selected increases by about 15 % (remains below the spec value of 500 e rms)

FSSR prototype Irradiation with 27 MeV protons to a 1.9x1013 cm-2 fluence,

corresponding to a total ionizing dose of 5 MRad

After irradiation the chip remains fully functional with very little (< 10 %) degradation of critical parameters such as ENC and threshold dispersion

FSSR2 Irradiation with 60Co -rays to a total ionizing dose of 20 Mrad

(no bias applied during irradiation)

Chip fully functional after irradiation; noise and charge sensitivity are not affected

Threshold dispersion with BLR selected increases by about 15 % (remains below the spec value of 500 e rms)



ConclusionsConclusions

The 128-channel chip FSSR2 was designed and successfully tested. The device is fully functional and meets demanding specifications in terms of noise and threshold dispersion Because of its low noise, radiation tolerance and high data output bandwidth and of the flexibility provided by the various programmable features, FSSR2 can operate in different experimental environments and applications FSSR2 is being evaluated in view of its possible operation for detector readout in a tracking system providing information to a first level trigger for both fixed target and collider experiments

The 128-channel chip FSSR2 was designed and successfully tested. The device is fully functional and meets demanding specifications in terms of noise and threshold dispersion Because of its low noise, radiation tolerance and high data output bandwidth and of the flexibility provided by the various programmable features, FSSR2 can operate in different experimental environments and applications FSSR2 is being evaluated in view of its possible operation for detector readout in a tracking system providing information to a first level trigger for both fixed target and collider experiments

Backup slides



Baseline restorerBaseline restorer

Shaper output has small overshoot. Overshoot causes unwanted variable offset at discriminator input. BLR removes variable offset.

0

20

40

60

80

100

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

Channel 2, tp=85 ns

without baseline shift1% occupancy2% occupancy

Co

mp

ara

tor

firi

ng

eff

icie

nc

y (%

)

Injected charge [fC]

0

20

40

60

80

100

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

Channel 1, tp=85 ns

without baseline shift1% occupancy2% occupancy

Co

mp

ara

tor

firi

ng

eff

icie

nc

y (%

)

Injected charge [fC]

Input signal discriminator scan without BLR

Input signal discriminator scan with BLR



__

++

Shaper outputShaper output

COMPCOMPVREFVREF

II

2I2I

Threshold circuit inputThreshold circuit input

Baseline restorerBaseline restorer



Threshold dispersionThreshold dispersion Peaking

time [ns]Threshold dispersion

[e rms] Low

GainHigh Gain

Channels with BLR deselected

65 580 460

85 600 470

125 615 485

Channels with BLR selected

65 440 295

85 440 290

125 490 280



b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12

(a) One output pair

b5 b4 b3 b2 b1 b0

b11 b10 b9 b8 b7 b6

b17 b16 b15 b14 b13 b12

b23 b22 b21 b20 b19 b18

b3 b2 b1 b0

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

b19 b18 b17 b16

b23 b22 b21 b20

(b) Two output pairs

(c) Four output pairs

(d) Six output pairs

Output data formatOutput data format

valerio re, massimo manghisoni università di bergamo and infn, pavia, italy jim hoff, abderrezak...

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