sensor signal processor ic w. sent and analog … signal processor ic w. sent and analog output...

Sensor Signal Processor IC w. SENT and Analog Output 520.44 PRELIMINARY INFORMATION – Apr 18, 2016

Features• Optimized for resistive sensor bridges without

external trim components• Configurable input signal range with 16-step coarse

analogue gain trimming; full scale span: 3...300mVpp

• Low noise input amplifier 10nV/sqrt(Hz) and 14-bit ADC for high resolution sensor signal acquisition

• Configurable digital low pass filter (0.13 ... 4.7 kHz) allows excellent SNR at smallest input span

• Compensation of thermal offset drift and gain drift up to 3rd order in the digital domain

• Digital correction of sensor gain non-linearity• Selectable temperature sensor: Internal sensor or

input for external sensor diode• Configurable output for− Ratiometric voltage output through 12-bit DAC, or− SENT mode (acc. SAE J2716, JAN2010)

• Over-voltage (OVP) and reverse voltage protections (RVP) at output and supply pins

• EEPROM (32 * 16-bit) for storage of digital calibra-tion and configuration data

• Single-wire programming interface supports 3-wire sensor assembly and end-of-line calibration

• Diagnostic features for sensor surveillance and built-in self test routines (BIST) for IC surveillance

• 5V-supply with over-voltage and reverse polarity pro-tection

• Operating temperature: -40 to +150°C• Automotive qualification according to AEC-Q100

Applications• Automotive Resistive Bridge Sensors• Pressure, Strain, Torque, Force

General DescriptionThe IC E520.44 is a sensor signal processor (SSP) designed to amplify and treat the signal of piezoelectric resistive bridges. It comprises wide programming range and comprehensive diagnostic features.A low-noise instrumentation amplifier with gain and off-set tuning capability amplifies the input from the bridge to a level which fits the input range of a 14-bit delta-sigma AD-converter. The digitized input after low-pass filtering is compensated for thermal drifts of offset and gain in the digital domain. A temperature signal from an on-chip sensor or an external T-sensor is employed for this and its digitized output is fed to the compensation calculator, too. Besides compensation of thermal drifts of offset and gain, the correction engine also can com-pensate non-linearity in the signal to 3rd order. The out-put from the calculator engine is fed into a DA-converter driving an analogue voltage buffer at OUT providing a ratiometric output signal. Alternatively, a digital SENT output can be used instead of the analogue output.In configuration or diagnostic modes the OUT pin is used as a single-wire serial data interface for in-system calibration with only 3 wires to the outside. Calibration and configuration data for a specific sensor are stored inEEPROM. The IC includes also self-test and diagnosticsof the sensor bridge attached and of the SSP itself. If faults occurs, they are indicated at the sensor output as failure states.

Ordering InformationOrder Code Temperature Range Package

E520.44A62C -40°C to +150°C QFN20L5

E520.44A52C -40°C to +150°C QFN20L4

E520.44A24Y -40°C to +150°C die 1)

1) Contact factory for bare die specifications

Typical Operating Circuit - Analogue Output Mode

E52

0.44

.

VS

.

.

VSSA

VSSD

VDDA

VDDD

EXHI

TSEN

INP

INN

EXLO

OUTSensorBridge

Input Channel

Analog In

VSS

VS5 regulated

Sensor module ECU

* Pin OUT: Shared by analog output, serial calibration interface (SIO), and SENT-interface

.

..

.

.

This document contains information on a pre-production product. Elmos Semiconductor AG reserves the right to change specifications and information herein without notice.

Elmos Semiconductor AG Data Sheet 25DS0144e.04


Functional Diagram

CompensationCalculator

Digital Control

SensorExcitation

MU

X

Piezo-resistive Bridge

E²PROM

DAC Buffer

VoltageRegulators

Over Voltage /Reverse Polarity

Protection

Test PortSensorGround

INP

INN

TSEN

EXHI

EXLO

OUT

VS

Serial I/O

VD

DA

VD

DD

TE

N

VS

SA

VS

SD

Coarse Offset

PGA

Coarse Gain

SensorDiagnosis

InternalTemp.Sensor

OV / Rev. Pol.Protect.

I/O Control

SSP4Sensor Signal

Processor

ADC14-bit

ADC

OUTPUTDiagnosis

TD

IT

DO

TC

KT

MS

TA

A

D1

D1 is an optional external temperature sensor diode

SENT

TestControl

Pin Configuration

n.c.

n.c.

INP

EXLO

INN

resv

d.T

SE

N

EX

HI

resv

d.

VD

DA

VS

SA

VDDD

VSSD

n.c.

VS

OUT

resv

d.

resv

d.

resv

d.

resv

d.

21

1

2

3

4

5

6 7 8 9 10

20 19

18

15

14

13

17 16

12

11

E520.44

Note: Top view, not to scale


Elmos Semiconductor AG Data Sheet 25DS0144e.04 2 / 79


Pin DescriptionNo Name Type Description

1 n.c. not connected


3 INP A_I Sensor voltage input, positive

4 EXLO S Sensor ground terminal (negative excitation)

5 INN A_I Sensor voltage input, negative

6 TSEN A_I External temperature sensor input

7 EXHI A_O Sensor excitation voltage output

8 resvd. reserved pin: Leave open in application!

9 VDDA S Regulated voltage analogue

10 VSSA S analogue ground

11 OUT A/D_IO Analogue voltage output / One wire programming interface / SENT-inter-face

12 VS S Main supply input (5V)


14 VSSD S digital ground

15 VDDD S Regulated voltage digital

16 resvd. reserved pin: Leave open in application!

17 resvd. reserved pin: Connect to VSSD or leave open!




21 EP S exposed die pad: Connect to VSSA on PCB

Note: A = Analogue, D = Digital, S = Supply, I = Input, O = Output, B = Bidirectional, HV = High Voltage

(EXLO and VSSA are internally connected by metal wiring)




1 Absolute Maximum RatingsStresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages referred to VSSA. Currents flowing into terminals are positive, those drawn out of a terminal are negative.

No. Description Condition Symbol Min Max Unit

1 Ground, digital VVSSD -0.3 +0.3 V

2 Supply voltage VVS -28 +40 V

3 Regulated voltage output VVDDA -0.3 4.2 V

4 Current at pin VDDA IVDDA -5 +5 mA

5 Regulated digital supply VVDDD -0.3 4.2 V

6 Current at pin VDDD IVDDD -5 +5 mA

7 Analogue voltage output (pin OUT) VOUT -28 +40 V

8 Current at output (pin OUT) IOUT -20 +20 mA

9 Voltage at sensor inputs VINP/N -0.3 4.2 V

10 Current at sensor inputs IINP/N -5 +5 mA

11 Sensor excitation voltage VEXHI -0.3 4.2 V

12 Current at EXHI-output IEXHI -12 +5 mA

13 Voltage at sensor ground terminal VEXLO -0.3 +0.3 V

14 Current at EXLO-terminal IEXLO -5 12 mA

15 Voltage at temperature sensor input VTSEN -0.3 4.2 V

16 Current at temperature sensor input ITSEN -5 +5 mA

17 voltage at reserved pins VTxxx -0.3 4.2 V

18 current at reserved pins ITxxx -10 +10 mA

19 Junction Temperature TJ -40 155 °C

20 Storage Temperature 1) not supplied TST -40 150 °C1) For moisture sensitive devices refer to JEDEC standard J-STD-033 for details of handling and usage. Storage at temperatures > 90°C for more than 96 h may affect the solderability of the devices. Storage is not considering any packing materials such as tapes, reels, dry packs, foils etc.

2 ESD

Description Condition Symbol Min Max Unit

ESD HBM protection;at system level pins (supply, output)

1) VESD(HBM),SYS -4 +4 kV

ESD HBM protection 2) VESD(HBM) -2 +2 kV

ESD CDM protection at all Pins 3) VESD(CDM) -500 +500 V

ESD CDM protection at Edge Pins 3) VESD(CDM),C -750 +750 V1) According to AEC-Q100-002 (HBM) chip level test; system level pins OUT, VS2) According to AEC-Q100-002 (HBM) chip level test; all other pins3) According to AEC-Q100-011 (CDM) chip level test




3 Recommended Operating Conditions

No. Description Condition Symbol Min Typ Max Unit

1 Supply voltage at VS VVS 4.5 5.0 5.5 V

2 Sensor sensitivity1) SIN 0.8 50 mV/V

3 Common mode sensor input voltage VIN(CM) 40% 50% 60% VEXHI

4 Sensor bridge resistance(EXHI to EXLO)

REXHI(BR) 1.0 20 kΩ

5 Operating temperature2) TOPR -40 150 °C1) Sensitivity of resistive bridge defined relative to bridge supply voltage. With SSP E520.44 the bridge supply is VEXHI .2) The device shall not be operated at maximum temperature permanently. Contact ELMOS for a permissible thermal mission profile including ensured EEPROM data retention.




4 Electrical Characteristics(VVS = 4.5V to 5.5V, TAMB=-40°C to + 150°C, unless otherwise noted. Typical values are at VVS= 5.0V and TAMB=+25°C. Positive currents flow into the device pins.)

4.1 Power SupplyNo. Description Condition Symbol Min Typ Max Unit

1 Quiescent current IEXHI = 0, IOUT = 0 IVS,q 8 10 mA

2 digital regulator output - normal operation 4.5 < VVS < 5.5V VDDD 3.15 3.45 V

3 digital regulator output - in case of Over-voltage

5.5 < VVS < 40V VDDDmax 3.15 3.8 V

4 current limitation ILIM,D -40 -20 mA


5 analogue regulator output -normal operation

4.5 < VVS < 5.5V VDDA 3.15 3.3 3.45 V

6 analogue regulator output -in case of over-voltage

5.5 < VVS < 40V VDDAmax 3.15 3.8 V

7 current limitation ILIM,A -40 -20 mA

4.2 OscillatorNo. Description Condition Symbol Min Typ Max Unit

1 Master clock frequency fCLK 9.7 10.24 10.8 MHz

4.3 Modes of OperationNo. Description Condition Symbol Min Typ Max Unit

1 Internal configuration (Copy of EEPROM data to RAM and configuration register)*)

tINIT 900 945 µs

2 SIO-1st-Byte command window*) tWIN,SIO-BYTE 1.20 1.60 ms

3 SIO command window*) tWINDOW 4.76 5.00 ms

4 Power-up Time*) Disable anyPower-Up BIST

tPWRUP,short 1.80 2.00 ms

5 Power-up Time Power-Up BISTsenabled, Signal Path BIST = off

tPWRUP,short 2.8 3.00 ms

6 Power-up Time*) All Power-Up BISTs enabled

tPWRUP,long 29.76 30.00 ms

*) Not tested in production

4.4 Signal Path

4.4.1 Sensor Excitation EXHINo. Description Condition Symbol Min Typ Max Unit

1 voltage drop to VDDA: VEXHI = VDDA - ΔVEXHI

IEXHI ≤ 3.3mA ΔVEXHI 60 100 mV

2 current limitation ILIM,EXHI -15 -7 mA




4.4.2 Sensor Path4.4.2.1 Sensor Amplifier Section

4.4.2.1.1 Sensor Offset Compensation


1 min. achievable residual offset after com-pensation*)

max. PGA gain(SENSPGA[3:0]=15)

VOS,RESI_15 -0.3 0.3 mV

2 min. achievable residual offset after com-pensation*)

min. PGA gain(SENSPGA[3:0]=0)

VOS,RESI_0 -0.6 0.6 mV

3 Offset compensation range max. PGA gain(SENSPGA[3:0]=15)

VOS,RANGE_15 -200 200 mV

4 Offset compensation range min. PGA gain(SENSPGA[3:0]=0)

VOS,RANGE_0 -380 380 mV

5 Offset voltage compensation DAC bits*) NOS,DAC 11 Bit*) Not tested in production

4.4.2.1.2 Programmable Gain Amplifier (PGA)


1 maximum full scale differential input voltage*) 1)

VINP - VINN 3 150 mV

2 Common-mode reference voltage*) VVCM 1.65 V

3 Input referred voltage noise density*) max PGA gain(SENSPGA[3:0]=15)

en,th 10 20 nV/

4 PGA input referred offset VOS,PGA 0.5 1.5 mV

5 common mode input voltage (VINP +VINN) / 2 40 % 60 % VEXHI

6 min. input voltage at VINP and VINN*) min{VINP, VINN} 0.9 V

7 max. input voltage at VINP and VINN*) max{VINP, VINN} 2.4 V

8 chopper frequency of the PGA*)

[ fCLK,TYP ]fchop 1/512

[20kHz]fCLK

*) Not tested in production1) For optimum SNR, the full-scale PGA input should be minimum 50% of the maximum PGA input range.

4.4.2.2 ΔΣ-Modulator for Sensor Signal Chain


1 Resolution*) RESSENS 14 Bits*) Not tested in production

4.4.3 Temperature PathNo. Description Condition Symbol Min Typ Max Unit

1 Input voltage (EXHI - TSEN)*) Internal refer-ence

VTEMP 0.2 0.9 V

2 Temperature ADC resolution*) RESTEMP 14 Bits

3 Pull-down current for external diode ITSEN,PD 15 20 25 µA

4 Allowed ADC range without indicating ADC-error (signed value)*)

ADC range 0 7700 LSB

5 ADC integral non-linearity*) INL -4 4 LSB*) Not tested in production




4.4.4 Output StageNo. Description Condition Symbol Min Typ Max Unit

1 Linear output voltage range (DAC and pos-itive and negative output buffer)*)

|IOUT| ≤ 3.5 mA, Analogue Voltage Output Mode

VOUT 0.05 0.95 VVS

2 Output resistance in diagnostic mode, low level selected

VOUT ≤ 0.04 VVS ROUT,DIAL 100 Ω

3 Output resistance in diagnostic mode, high level selected

VOUT ≥ 0.96 VVS ROUT,DIAH 100 Ω

4 Sink current limitation in analogue mode IOUTsink,LIM,ana 7 11 14 mA

5 Source current limitation in analogue mode IOUTsource,LIM,ana -14 -11 -7 mA

6 Leakage current at supply loss VS: open,VOUT = 5.5 V

IOUT,LossVS 45 70 μA

7 Leakage current at ground loss*) GND: open,VOUT = 0 V

IOUT,LossGND -100 -60 μA

8 Leakage current when OUT is HiZ short of OUT to GND, VDDD <VDDDTH,on

IOUT,HiZGND -120 -80 μA

9 Leakage current when OUT is HiZ short of OUT to VS, VDDD <VDDDTH,on

IOUT,HiZ,VS 115 160 μA


4.4.4.1 Analogue Voltage Mode


1 Ratiometric error*) 1) VVS,MIN .. VVS,TYP .. VVS,MAX

REOUT -0.1 +0.1 %FSR

2 OUT stage error from DAC-input to ana-logue output *) 1)

VVS,TYP EOUT < 0.4 %FSR

*) Not tested in production1) Full Scale Range (FSR) = 90 % VVS (range: 5 % VVS ... 95% VVS )

4.4.4.1.1 12-bit Output DAC


1 Reference voltage VREF,DAC 0.50 VVS

2 Resolution RESDAC 12 bit

3 Update rate (output)*) [ fCLK,TYP ] fDAC 1/3[6.7kHz]

fchop

4 Integral non-linearity*) 1) 5% to 95% of DAC input range

INL -4 4 LSB

*) Not tested in production1) In production larger test limits of 10 LSB will be used




4.4.4.2 SENT Mode

4.4.4.2.1 SENT Physical Interface


1 Signal fall time (Figure 6.5.5.2.1-1) *) at tTICK = 3µs,measured at SENT-wire, receiver connec-ted

tFALL 6.5 µs

2 Signal rise time (Figure 6.5.5.2.1-1)*) at tTICK = 3µs,measured at SENT-wire, receiver connec-ted

tRISE 18 µs

3 Low state output voltage IOUT < 0.1 mA, measured at SENT-wire

VOUTSENT,OL 0.5 V

4 High state output voltage IOUT > -0.1 mA,measured at SENT-wire

VOUTSENT,OH 4.1 V

5 Sink current limitation IOUTSENT,SINK 7 14 mA

6 Source current limitation IOUTSENT,SRC -14 -7 mA

7 Low state duration (Figure 6.5.5.2.1-1)*) at tTICK = 3µs,measured at SENT-wire, receiver connec-ted, pulse low for5 clock ticks

tSTABLE,LOW 6 µs

8 High state duration (Figure 6.5.5.2.1-1)*) at tTICK = 3µs,measured at SENT-wire, receiver connec-ted, pulse high for 7 clock ticks

tSTABLE,HIGH 6 µs


4.4.4.2.2 SENT Protocol


1 SENT clock tick selection range*) SENTCON-F.TICKSEL[3:0]

tTICK 3 12 90 µs

2 Nibble pulse length represents decimal value between 0 and 15*)

NLENGTH 12 27 tTICK

3 Synchronisation Frame*) SFRAME 56 tTICK

4 Messages length with pause pulse*) SENTCON-F.NPP=0b

MLENGTH 282 tTICK





4.4.4.3 SIO Mode (Serial Input Output)


1 Data baudrate*) DATABAUDRATE 14.4 kbit/s

2 Recovery Time from ANAOUT-Cmd to communicate SIO*)

tRX,HI-Z(SIO) 200 μs

3 SIO bit cycle time, transmitting*) tC,TX(SIO) 66.6 70.4 74.4 μs

4 SIO bit low time, transmitting*) tW,TX(SIOL) 0.45 0.5 0.55 tC,TX(SIO)

5 SIO bit cycle time, receiving*) tC,RX(SIO) 54.0 69.4 90.0 μs

6 SIO bit cycle time, receiving*) tW,RX(SIOL) 0.45 0.5 0.55 tC,RX(SIO)

7 SIO input low level at pin OUT VIL(SIO) 0.3 VVS

8 SIO input high level at pin OUT VIH(SIO) 0.75 VVS

9 SIO output low level at pin OUT IOL(SIO) ≤ 2 mA VOL(SIO) 0.1 VVS

10 SIO output high level at pin OUT IOL(SIO) ≥ -2 mA VOH(SIO) 0.9 VVS*) Not tested in production

4.5 Diagnostics

4.5.1 Supply DiagnosisNo. Description Condition Symbol Min Typ Max Unit

1 threshold for VS too low diagnosis error VStooLO 3.8 4.45 V

2 threshold for VS too high diagnosis error VStooHI 5.55 6.3 V

3 min. threshold for power-on-reset, rising VDDDTH,on 2.7 V

4.5.2 Sensor DiagnosisNo. Description Condition Symbol Min Typ Max Unit

1 High threshold at INP, INN Short to EXHI VIN,DIAG,HI 75 % 85 %

2 Low threshold at INP, INN Short to EXLO VIN,DIAG,LO 15 % 25 %

3 Threshold of EXHI short circuit to EXLO VEX,DIAG,short 75% 85%

4.5.3 Output DiagnosisNo. Description Condition Symbol Min Typ Max Unit

1 1. comparator reference level VOUT,REF1 80 85 92 %VS




5 Period of output error indication*) analogue output mode

tOUTERR,PWD 33 1/fDAC

6 Output error indication active(for current limit diagnosis or analogue out-put diagnosis)*)

analogue output mode

tOUTERR,ON 31 1/fDAC

7 Output error indication inactive(for current limit diagnosis or analogue out-put diagnosis)*)

analogue output mode

tOUTERR,OFF 2 1/fDAC





4.5.4 BIST (Built In Self Test)No. Description Condition Symbol Min Typ Max Unit

1 Power-up Signal Path BIST elapsed time ENERR.ENSP-BERR = 1b

tSPBIST 3.65 ms

2 Low level time of BCS (BIST Completion Sequence)

ENERR.ENSP-BERR = 1b

tBCS,LOW 10 ms

3 High level time of BCS (BIST Completion Sequence)

ENERR.ENSP-BERR = 1b

tBCS,HIGH 10 ms

4.6 EEPROM Delivery StateNo. Description Condition Symbol Min Typ Max Unit

1 64 Byte Address of EEPROM*) EECONF 0x72 0xB1 Hex

2 Enable Error Diagnosis: Hi-Byte*) Addr. 0x73 ENERR_H 0x00 Hex

3 Enable Error Diagnosis: Mid-Byte*) Addr. 0x74 ENERR_M 0x00 Hex

4 Enable Error Diagnosis: Lo-Byte*) Addr. 0x75 ENERR_L 0x00 Hex

5 Sensor Offset Compensation*) Addr. 0x76 - 0x77

SENSOFF 0x0000

Hex

6 Sensor PGA Configuration*) Addr. 0x78 SENSPGA 0x00 Hex

7 Sensor Low pass Filter Coefficient*) Addr. 0x7A SENSLP 0x02 Hex

8 Temperature Path Configuration*) Addr. 0x7B TEMPIF 0x00 Hex

9 Sensor Upper-/Lower Clipping Value*) Addr. 0x7C - 0x7D

LIMSENS 0xFF00

Hex

10 Mode Configuration*) Addr. 0x7E MODECONF 0x00 Hex

11 SENT Configuration*) Addr. 0x7F SENTCONF 0x00 Hex

12 Temperature Coefficient of 2nd order non-linearity*)

Addr. 0x80 - 0x81

C10 0x0000

Hex

13 3rd Order non-Linearity Coefficient*) Addr. 0x82 - 0x83

C9 0x0000

Hex

14 2nd order non-linearity coefficient*) Addr. 0x84 - 0x85

C8 0x0000

Hex

15 Temperature Coefficient of Sensor Gain 3rd

order*)Addr. 0x86 - 0x87

C7 0x0000

Hex

16 Temperature Coefficient of Sensor Gain 2nd

order*)Addr. 0x88 - 0x89

C6 0x0000

Hex

17 Temperature Coefficient of Sensor Gain 1st order*)

Addr. 0x8A - 0x8B

C5 0x0000

Hex

18 Temperature Coefficient of Sensor Offset 3rd order*)

Addr. 0x8C - 0x8D

C4 0x0000

Hex

19 Temperature Coefficient of Sensor Offset 2nd order*)

Addr. 0x8E - 0x8F

C3 0x0000

Hex

20 Temperature Coefficient of Sensor Offset 1st order*)

Addr. 0x90 - 0x91

C2 0x0000

Hex

21 Sensor Gain Coefficient*) Addr. 0x92 - 0x93

C1 0x4000

Hex

22 Sensor Offset Coefficient*) Addr. 0x94 - 0x95

C0 0x2000

Hex

23 Sensor Path pre-Processing*) Addr. 0x96 SENSDIG 0x02 Hex





24 Temperature Path pre-Processing*) Addr. 0x97 TEMPDIG 0x00 Hex

25 Configuration Code*) Addr. 0x98 - 0x99

CCODE 0x0000

Hex

26 Manufacture Code*) Addr. 0x9A - 0x9B

MCODE 0x0000

Hex

27 High Nibble of Temperature Characteristic X1,Pressure Characteristic X1*)

Addr. 0x9C - 0x9D

TX1/PX1 0x0000

Hex

28 High Nibble of Temperature Characteristic X2, Pressure Characteristic X2*)

Addr. 0x9E - 0x9F

TX2/PX2 0x0000

Hex

29 High Nibble of Temperature Characteristic Y1,Pressure Characteristic Y1*)

Addr. 0xA0 - 0xA1

TY1/PY1 0x0000

Hex

30 High Nibble of Temperature Characteristic Y1,Pressure Characteristic Y1*)

Addr. 0xA2 - 0xA3

TY2/PY2 0x0000

Hex

31 Low Byte of Temperature Characteristic X1*)

Addr. 0xA4 TX1 0x0000

Hex

32 Low Byte of Temperature Characteristic X2*)

Addr. 0xA5 TX2 0x0000

Hex

33 Low Byte of Temperature Characteristic Y1*)

Addr. 0xA6 TY1 0x0000

Hex

34 Low Byte of Temperature Characteristic Y2*)

Addr. 0xA7 TY2 0x0000

Hex

35 Sensor ID#1*) Addr. 0xA8 - 0xA9

SID1 0x0000

Hex

36 Sensor ID#2*) Addr. 0xAA - 0xAB

SID2 0x0000

Hex

37 Sensor ID#3*) Addr. 0xAC - 0xAD

SID3 0x0000

Hex

38 Sensor ID#4*) Addr. 0xAE - 0xAF

SID4 0x0000

Hex

39 Checksum over a address range of Memory (0x72 - 0xAF)*)

Addr. 0xB0 - 0xB1

EECRC16 0x450C

Hex





5 Register Table

Register Name Address Description

BISTSTAT_H 0x6A High byte BIST Status Register

BISTSTAT_L 0x6B Low byte BIST Status Register

MASKERRC_H 0x6C High byte of Masked Error Code Register

MASKERRC_M 0x6D Middle byte of Masked Error Code Register

MASKERRC_L 0x6E Low byte of Masked Error Code Register

ERRC_H 0x6F High byte of Error Code Register

ERRC_M 0x70 Middle byte of Error Code Register

ERRC_L 0x71 Low byte of Error Code Register

ENERR_H 0x73 High byte Enable Error Register

ENERR_M 0x74 Middle byte Enable Error Register

ENERR_L 0x75 Low byte Enable Error Register

SENSOFF_H 0x76 High byte of sensor offset compensation

SENSOFF_L 0x77 Low byte of sensor offset compensation

SENSPGA 0x78 Sensor PGA configuration

SENSLP 0x7A Sensor low-pass digital filter coefficient

TEMPIF 0x7B Temperature Path configuration

LIMSENS_H 0x7C Setting of Sensors upper Clipping Value

LIMSENS_L 0x7D Setting of Sensors lower Clipping Value

MODECONF 0x7E Mode Configuration

SENTCONF 0x7F SENT configuration register

C10_H 0x80 High byte of temperature coefficient of 2nd order non-linearity

C10_L 0x81 Low byte of temperature coefficient of 2nd order non-linearity

C9_H 0x82 High byte of 3rd order non-linearity coefficient

C9_L 0x83 Low byte of 3rd order non-linearity coefficient

C8_H 0x84 High byte of 2nd order non-linearity coefficient

C8_L 0x85 Low byte of 2nd order non-linearity coefficient

C7_H 0x86 High byte of temperature coefficient of sensor gain (3rd order)

C7_L 0x87 Low byte of temperature coefficient of sensor gain (3rd order)

C6_H 0x88 High byte of temperature coefficient of sensor gain (2nd order)

C6_L 0x89 Low byte of temperature coefficient of sensor gain (2nd order)

C5_H 0x8A High byte of temperature coefficient of sensor gain (1st order)

C5_L 0x8B Low byte of temperature coefficient of sensor gain (1st order)

C4_H 0x8C High byte of temperature coefficient of sensor offset (3rd order)

C4_L 0x8D Low byte of temperature coefficient of sensor offset (3rd order)

C3_H 0x8E High byte of temperature coefficient of sensor offset (2nd order)

C3_L 0x8F Low byte of temperature coefficient of sensor offset (2nd order)

C2_H 0x90 High byte of temperature coefficient of sensor offset (1st order)

C2_L 0x91 Low byte of temperature coefficient of sensor offset (1st order)

C1_H 0x92 High byte of sensor gain coefficient

C1_L 0x93 Low byte of sensor gain coefficient

C0_H 0x94 High byte of sensor offset coefficient





C0_L 0x95 Low byte of sensor offset coefficient

SENSDIG 0x96 Sensor path pre-processing

TEMPDIG 0x97 Temperature path pre-processing

CCODE_H 0x98 High Nibble of Configuration Code 1)

CCODE_L 0x99 Low byte of Configuration Code 1)

MCODE_H 0x9A High Nibble of Manufacturer Code 1)

MCODE_L 0x9B Low Byte of Manufacturer Code 1)

TX1_H/PX1_H 0x9C High Nibble of Temperature Characteristic X1 / High Nibble of Pressure Charac-teristic X1 1)

PX1_L 0x9D Low Byte of Pressure characteristic X1 1)

TX2_H/PX2_H 0x9E High Nibble of Temperature Characteristic X2 / High Nibble of Pressure Charac-teristic X2 1)

PX2_L 0x9F Low Byte of Pressure characteristic X2 1)

TY1_H/PY1_H 0xA0 High Nibble of Temperature Characteristic Y1 / High Nibble of Pressure Charac-teristic Y1 1)

PY1_L 0xA1 Low Byte of Pressure characteristic Y1 1)

TY2_H/PY2_H 0xA2 High Nibble of Temperature Characteristic Y2 / High Nibble of Pressure Charac-teristic Y2 1)

PY2_L 0xA3 Low Byte of Pressure characteristic Y2 1)

TX1_L 0xA4 Low Byte of Temperature characteristic X1 1)

TX2_L 0xA5 Low Byte of Temperature characteristic X2 1)

TY1_L 0xA6 Low Byte of Temperature characteristic Y1 1)

TY2_L 0xA7 Low Byte of Temperature characteristic Y2 1)

SID1_H 0xA8 High Nibble of Sensor ID#1 1)

SID1_L 0xA9 Low Byte of Sensor ID#1 1)

SID2_H 0xAA High Nibble of Sensor ID#2 1)

SID2_L 0xAB Low Byte of Sensor ID#2 1)

SID3_H 0xAC High Nibble of Sensor ID#3 1)

SID3_L 0xAD Low Byte of Sensor ID#3 1)

SID4_H 0xAE High Nibble of Sensor ID#4 1)

SID4_L 0xAF Low Byte of Sensor ID#4 1)

1) Refers to Table 6.5.5.2.2-2, Enhanced Serial Message ID in slow Channel




6 Functional Description

6.1 OverviewThe data path architecture of the IC E520.44 includes a constant voltage excitation for the resistive sensor bridge and a programmable gain amplifier (PGA) with high common mode rejection with and wide full scale input range and coarse sensor offset compensation. The following 14-bit delta sigma ADC digitizes the amplified sensor signal and feeds it into a digital compensation calculator processor (CCP). The temperature for sensor compensation is measured either by an integrated temperature sensor diode or an external diode, which shall be connected to pin TSEN. Also this digital input is digitized and fed into the CCP.

The compensation of offset, sensitivity, non-linearity (up to 3rd order) of the sensor characteristic and temperature drifts of offset and gain is applied to the signal by a dedicated arithmetic unit of the CCP. The corresponding coeffi-cients required for the polynomial correction are calculated initially during the calibration process of each individual sensor. The CCP also includes programmable filtering and signal clipping functions which can be applied to the output.

The signal output OUT of the SSP E520.44 can be configured either as an analogue voltage output (ratiometric to supply VS) or as a digital SENT data interface (SENT = Single Edge Nibble Transfer).In analogue output mode, an 12-bit DAC converts raw or pre-processed (linearised) sensor data back to the ana-logue domain and feeds it to a rugged single-wire analogue output voltage buffer. For minimum wire count in the complete sensor module, the same analogue output pin can be configured as a serial input/output interface (SIO) which allows to read digital data from the device or to write configuration and calibration data into the embedded EEPROM of the E520.44.In SENT output mode, the output physical interface is configured as a digital push-pull driver. Data are transmitted from this following the SENT protocol specification according to SAE 2716 (Jan. 2010).

For enhanced analogue diagnostic the analogue output value is checked against the digital equivalent by means of a group of comparators. Additionally, self diagnostic routines include checks for sensor bridge or excitation faults. In case of failures (interface, output, or internal errors) detected by integrated self test routines these are indicated at the output OUT (see ch. 6.6). In analogue mode, this is a failure state where no regular output voltage signal canbe expected, while in digital SENT mode dedicated failure messages including detail information are transmitted (see ch. 6.5.5.2).

Automotive and industrial applications are supported by over-voltage protection (OVP) and reverse voltage polarity protection (RVP) at supply and output pins.

6.2 Power SupplyThe IC operates from a 5V-supply with internal over voltage and reverse voltage protection. The protection circuitry prevents damage to the device in case of over-voltage appearing at the supply input VS. Also a low-drop reverse protection circuit is integrated which blocks negative voltages from the internal circuitry.

Two independent linear regulators are integrated to generate a stabilized voltage of 3.3 V (typical) for internal ana-logue blocks (VDDA) including the sensor excitation unit and the digital circuitry (VDDD). Both regulator outputs arecurrent limited to maximum limitation current ILIM,A and ILIM,D at VDDA and VDDD, respectively.

VDDA and VDDD need external bypass capacitors to ground to ensure safe operation. An external capacitor at VS is mandatory to block fast transients from the IC and to meet automotive EMC requirements.




low drop reverse protection

VBGVBG

VDDA VDDD

VS

Figure 6.2-1: Supply Regulators

6.3 OscillatorAs the central clock reference the circuitry contains a master clock oscillator. All other frequencies are derived from this master clock fCLK .

6.4 Modes of OperationConcerning the output of data, the SSP is capable to operate in two different modes: in Analogue Output mode and in SENT mode:

• In Analogue Output mode (MODECONF.OUTMODE = 0b), the pressure information is transmitted to the output as an analogue voltage by using a 12-bit DAC. The pressure value is converted to a voltage level, which can be used directly, e.g. by an analogue control loop, or can be acquired by the ADC of an external MCU.

• In SENT mode (MODECONF.OUTMODE = 1b), data is transferred in a digital way via the single wire SENT interface.

Both modes are using the pin OUT for data transmission, therefore they cannot be active simultaneously. To definethe mode of operation of the SSP, a configuration bit OUTMODE in register MODECONF (see 6.4) has to be set to the desired value during the SSP configuration phase.

The SSP power-up sequence in both these configurations is the same:After the supply voltage has exceeded the power-on threshold VDDDTH,on (checked at the digital regulator VDDD), an internal initialisation is performed followed by the execution of different kinds of build-in self-tests (BISTs), which can be enabled or disabled on demand by configuration settings (see ch. 6.6.5). In parallel with the execution of theBISTs, a time window tWINDOW opens which allows to receive specific SIO commands at the output port OUT (see ch. 6.5.5.3 for details of the serial I/O). During this window, the pin OUT remains at high impedance (hi-Z) to allow reception of SIO messages. Depending on reception of valid SIO commands, this hi-Z time window is divided in two sections as explained below.




Example 1: Selectable Power-up BISTs; no SIO command received during tWINDOW

RAM PBIST EE PBIST SP BIST

tSPBIST

ROM PBIST AU PBIST

VDDD

VDDDTH,on

Internal State Operate

t

tPWRUP

tWIN,SIO-BYTE

Init

tINIT

VDDD

VDDDTH,on

Internal State Configuration or Diagnosis

t

tPWRUP

tWINDOW

TWIN,SIO-BYTE

CMDSIO

Init

tINIT

0xE5 0x5E CHK

Example 2: Selectable Power-up BISTs; valid SIO command received during tWINDOW

RAM PBIST EE PBIST ROM PBIST

SIO command byte: Only ENACONF or ENADIAG accepted, OUT = hi-Z

Figure 6.4-1: Power Up Sequence

If no SIO command was received within the time tWIN,SIO-BYTE, the SSP will enter the operational state (OPERATE) at the end of BIST execution (see Figure 6.4-1, example 1) after tPWRUP. Depending on the power-up BISTs enabled, this power-up delay will be very short tPWRUP,short (no BISTs active) or longer up to tPWRUP,long with all BISTs including signal path BIST active(SP-BIST, see ch. 6.6.5).

If a valid SIO command - ENACONF ("enable configuration") or ENADIAG ("enable diagnosis") - is received within the window time, the SSP will enter the state CONFIGURATION or DIAGNOSIS, respectively. The detection of SIOcommands is performed in two steps by the receiver (see Figure 6.4-1, example 2). In a first phase the command byte of the SIO command (byte 1) is interpreted. The byte 1 needs to be transferred to the SSP within tWIN,SIO-BYTE. Only if this command byte is either ENACONF or ENADIAG, the time window where OUT is hi-Z will be prolonged to tWINDOW to permit interpretation of further bytes including check sum and process the SIO answer indicating acknowledgement or not-acknowledge of the command. If the byte 1 is different, the hi-Z window time ends and thecircuit enters OPERATE state after all enabled BISTs are completed. This two-step interpretation allows for a very short power-up time tPWRUP,short (with no BISTs active).

In case a valid ENACONF or ENADIAG command was received in the time window, all running BISTs are interrup-ted and the output port OUT will remain at hi-Z ready to receive further SIO commands. In CONFIGURATION state, several SIO commands allow control of internal functions and read/write access to the SSPs internal memory(see Table 6.5.5.3-1).




If the EEPROM write protection bit EE_WP is set in register MODECONF, the configuration command ENACONF will be inhibited. Also any write access to the internal memory is blocked in this case. With EE_WP set, the dia-gnosis command ENADIAG remains valid, which allows circuit diagnostic functions such as control of internal func-tions and read access to the SSPs internal memory

The following table summarizes the conditions and features of the internal states of the SSP.

Table 6.4-1: Internal States

State Description

OPERATE(ANALOGUE output mode enabled)

• This state is entered after expiry of tPWRUP 1) with no SIO command received and the SSP con-figured to Analogue Output Mode (MODECONF.OUTMODE = 0b)

• The signal path is activated and pressure data are calculated• The output of analogue data (voltage) at pin OUT is enabled• Receiving of SIO commands is not feasible in this configuration

OPERATE(SENT mode enabled)

• This state is entered after expiry of tPWRUP 1) with no SIO command received and the SSP is con-figured to SENT Mode (MODECONF.OUTMODE = 1b)

• The signal path is activated and pressure data are calculated• The output of digital SENT data at pin OUT is enabled• Receiving of SIO commands is not feasible in this configuration

CONFIGURA-TION

• This state is entered if the SIO command ENACONF was received before tWINDOW is expired (Entry into CONFIGURATION is not possible if the EEPROM write-protection bit MODECON-F.EE_WP = 1b was set before)

• The pin OUT remains in hi-Z state and the device is ready to receive further SIO commands• Write access to EEPROM and configuration memory is permitted

DIAGNOSIS • This state is entered if the SIO command ENADIAG was received before tWINDOW is expired• The pin OUT remains in hi-Z state and the device is ready to receive further SIO commands• Write access to EEPROM and configuration memory is barred, independent of the state of the

EEPROM write-protection bit MODECONF.EE_WP1) See Figure 6.4-1

Table 6.4-2: Register MODECONF (0x7E) Mode Configuration

MSB LSB

Content EE_WP OUT-MODE

Reset value 0 0 0 0 0 0 0 0

Access R R R R R R/W R R/W

Bit Description EE_WP : EEPROM Write Protection• 0b: Write access permitted• 1b: Write access inhibitedOUTMODE : Mode Selection• 0b: Analogue Output Mode• 1b: SENT Mode




6.5 Signal PathIn Figure 6.5-1 a block diagram of the signal path is depicted. The different blocks are described in more detail in the following sections.

Signal Correction

Sraw

Traw

Limiter

Pcorr

Tnorm

OUTDAC Output Buffer

SIOT

P

SensorPath

TemperaturePath

INP

INN

TSEN

SensorExcitation

EXHI

Output Stage

SENT

Figure 6.5-1: Signal Path

6.5.1 Sensor Excitation EXHIA voltage closely related to the internal supply voltage VDDA is used for sensor excitation. The voltage at the bridge supply pin EXHI is provided through a low resistive analogue switch with current limitation. The voltage at pin EXHI is defined by its difference Δ VEXHI to VDDA and the maximum current available from EXHI to the sensor bridge is ILIM,EXHI.

6.5.2 Sensor PathIn Figure 6.5.2-1 the signal path from the bridge input to the uncorrected digital data output (Raw Sensor Data) is depicted. The input voltage is amplified by a programmable gain amplifier (PGA) with a coarse offset compensationadded at the input of the first amplifier stage. A chopping principle is applied in the signal front-end to suppress error caused by amplifier offset and 1/f-noise. Chopper modulation and demodulation at frequency fchop are executed at the bridge input and in the digital domain, respectively.

+

FM

MIXER

FM REJECT LOWPASS

SINC323rd ORDER

PHASECOMP

D=32

8 FM2nd ORDER

ΔΣ MODULATOR

256 FM

PGA

COARSE GAIN

BRIDGE OFFSETCOARSE COMP.FM

INPUTMIXER

BRIDGE

RAWSENSOR

DATA SIGNALCORRECTION

Figure 6.5.2-1: Sensor Path (bridge input to raw-data)

The temperature of the sensor bridge (off chip) or the chip temperature is measured by means of a junction diode and converted to digital using a Δ Σ A/D-converter.Both, temperature data and raw sensor data are processed by a digital correction algorithm in order to remove off-sets, non-linearities, and temperature effects from the bridge signal. In case of Analogue Output Mode the correc-ted digital data are converted to the analogue equivalent using a 12-bit DAC and fed to an output buffer (see Figure6.5-1). When using digital SENT data output, just a re-scaling of the corrected digital output to the SENT protocol using 12-bit digital (pressure) output data is done.




The total gain of the signal path (with analogue voltage output) is defined as the quotient of analogue output voltage to PGA input signal. This total gain is partitioned among the gain of the PGA (coarse gain setting) and the gain factor added in the digital correction. The PGA section includes the input stage of the Δ Σ modulator shown inFigure 6.5.2-1.The coarse gain setting has to be chosen as large as possible for an optimum signal-to-noise ratio (SNR). On the other hand, saturation of the analogue amplifiers or the Δ Σ ADC must be avoided imperatively, because signal clipping cannot be removed by the digital correction engine. Therefore, it is mandatory to use a PGA gain setting which ensures the sensor output voltage is not exceeding the maximum PGA input range. The specified input range and the corresponding gain setting ensures the delta-sigma converter operates within the allowed range achieving best linearity.Table 6.5.2-1 below lists the recommended gain settings which should be used to fit the input voltage span of the sensor (first column). The second and third column of this table give the digital gain setting and the corresponding gain of the sensor front-end (PGA + ADC), respectively. All gain values given are typical data. It should be noted, the total system gain (input to output of SSP) is fine-tuned during the digital correction, which includes also a digital multiplication which can be temperature and signal dependent to correct for non-linearity and thermal variation of the signal. The digital "fine trimming" of the gain is set by the calibration data stored in EEPROM as the analogue coarse gain and offset settings.For completeness Table 6.5.2-1 also gives typical data of total gain in Analogue Output Mode (for a specific setting of digital calibration parameters) in column 4 with typical supply VVS,typ = 5.0V (Note: Analogue output is ratiometric, thus gain changes linear with VS). In column 5 the input offset range which is ensured to be covered by the coarse offset calibration is given for the different gain settings. Especially at high gain (GPGA > 7) the coarse offset com-pensation range is more than ten times the input signal range.

Table 6.5.2-1: Gain Table

max. PGA inputrange 1)

Gain setting GPGA 2) Front-end gain 3) Total gain analogue(typical) 4)

max. bridge offset 5)

150 mV 0 7.9 14.7 380 mV

115 mV 1 10.2 18.9 380 mV

87 mV 2 13.2 24.4 320 mV

66 mV 3 17.1 31.5 320 mV

50 mV 4 22.1 40.9 260 mV

38 mV 5 28.7 53.0 260 mV

29 mV 6 38.2 70.5 200 mV

22 mV 7 50.0 92.1 200 mV

17 mV 8 63.2 117 200 mV

13 mV 9 85.3 156 200 mV

10 mV 10 106 196 200 mV

7 mV 11 142 263 200 mV

5 mV 12 183 340 200 mV

5 mV 13 223 413 200 mV

4 mV 14 300 555 200 mV

3 mV 15 386 715 200 mV1) The gain tolerances are +/- 8% for all gain data. The specification of the max. input range takes into account also the internal PGA-offset.2) Digital configuration setting in register SENSPGA (see 6.5.2.1.2)3) Front-end gain: PGA input to ADC output (typical, @ VDDA = 3.3V)4) Total gain, analogue output selected; exemplary typical data (@ VS = 5.0V, VDDA = 3.3V, digital settings C0 = 0x2000, C1=0x4000, SENSDIG = 0x020)5) Offset range ensured to be covered by coarse offset setting at input including tolerances (see ch. 6.5.2.1.1)




6.5.2.1 Sensor Amplifier Section

The amplifier section of the sensor path is optimized for sensors forming a resistive bridge. It covers a wide range of bridge resistor values and sensitivity values. Versatile configuration options of this amplifier, followed by an optimally adapted signal acquisition chain (ADC) allow perfect fitting to many types of sensors for pressure, strain, force, torque, acceleration etc. (e.g. piezo-resistive MEMS, thin/thick film on ceramic/steel, balance beam accelero-meters, strain gauges).

6.5.2.1.1 Sensor Offset Compensation

A coarse compensation of the sensor offset voltage at the amplifier input allows an efficient use of the sensor amp-lifier gain settings and the dynamic range of the following sensor ADC. This offset compensation is performed by a binary, weighed resistor 11-bit DAC (sign + 10 bit absolute, control register bits: SENSOFF.OSENS[10:0]), which feeds a compensation current into the first stage of the instrumentation amplifier (first stage of the PGA, see Figure 6.5.2.1.2-1). Bridge offset at the input in the range VOS,RANGE can be compensated by this. The residual offset after optimum calibration can be trimmed in the analogue domain to minimum VOS,RESI. The reference of the offset com-pensation DAC tracks the sensor bridge supply voltage VEXHI.(Note: Usually only a coarse input offset trimming is needed to optimize the input range of the PGA to the bridge characteristics. Fine trimming of offset is achieved during individual sensor calibration in the digital domain which also includes thermal offset variations.)

The following table describes the offset setting by the binary weighted steps of this DAC (typical values) as a func-tion of the selected gain. For the 10 upper gain settings (GPGA = 6 15) offset LSB and range are identical. Only at smaller gains the LSB increases. Actual offset values may derive by up to 20% from the data given in this table.The bit dOS[n] in the table equals SENSOFF.OSENS[n]. Bit dOS[10] gives the sign of the offset compensation as:

dOS[10]=0 positive offset,dOS[10]=1 negative offset

dOS[9:1]=3FF dOS[9] dOS[8] dOS[7] dOS[6] dOS[5] dOS[4] dOS[3] dOS[2] dOS[1] dOS[0]

GPGAfront-end

GAINoffset range,

unsigned [mV]step9 =

MSBstep8[mV]

step7[mV]

step6[mV]

step5[mV]

step4[mV]

step3[mV]

step2[mV]

step1[mV]

step0 = LSB

0 7.9 590.4 289.20 149.40 75.60 38.40 19.20 9.60 4.80 2.40 1.20 0.601 10.2 590.4 289.20 149.40 75.60 38.40 19.20 9.60 4.80 2.40 1.20 0.602 13.2 482.2 236.18 122.01 61.74 31.36 15.68 7.84 3.92 1.96 0.98 0.493 17.1 482.2 236.18 122.01 61.74 31.36 15.68 7.84 3.92 1.96 0.98 0.494 22.1 393.6 192.80 99.60 50.40 25.60 12.80 6.40 3.20 1.60 0.80 0.405 28.7 393.6 192.80 99.60 50.40 25.60 12.80 6.40 3.20 1.60 0.80 0.406 38.2 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.307 50.0 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.308 63.2 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.309 85.3 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.30

10 106 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.3011 142 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.3012 183 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.3013 223 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.3014 300 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.3015 386 295.2 144.60 74.70 37.80 19.20 9.60 4.80 2.40 1.20 0.60 0.30

Figure 6.5.2.1.1-1: Binary offset compensation steps (parameter GAIN), typical data

The 3rd column describes the typical offset range (absolute), which is the sum of the 10 bits (columns) the right. Thesign will be set by the MSB dOS[10]. For a complete overview also the typical gain values are given in the 2nd column.




It should be noted steps 0 through 6 are strictly binary weighted (factor 2) while steps 7, 8, and 9 are intentionally a bit smaller. By this, the occurrence of missing codes is avoided at the cost of a not perfectly linear characteristic (see Figure 6.5.2.1.1-2 for an exemplary DAC characteristic). This can be advantageous for sensors with small sig-nal (high gain required) and very large offset, where missing codes in the DAC characteristic might complicate to determine correct offset settings.

Note: Guaranteed offset compensation range VOS,RANGE as given in Table Table 6.5.2-1 (and chapter 4) is smaller than the typical data in the table above because of tolerances and additional margins to considered additionally.

0

100

200

300

400

500

0 128 256 384 512 640 768 896 1024

Offset setting (typical) [mV] , @ GPGA = 0x2

Figure 6.5.2.1.1-2: Offset compensation DAC characteristic (real and ideal)

Table 6.5.2.1.1-1: Sensor Offset Compensation Registers


SENSOFF_H 0x76 High byte of sensor offset compensation

SENSOFF_L 0x77 Low byte of sensor offset compensation

Table 6.5.2.1.1-2: Register SENSOFF_H (0x76) High byte of sensor offset compensation

MSB LSB

Content PDSENS OSENS[10:8]

Reset value 0 0 0 0 0 000

Access R/W R R R R R/W

Bit Description PDSENS : Sensor pull-down enable to detect open at sensor outputs (INN. INP) ERRC.SERR3 (chapter 6.6.6, Diagnosis Registers)OSENS[10:8] : high nibble of sensor offset setting




Table 6.5.2.1.1-3: Register SENSOFF_L (0x77) Low byte of sensor offset compensation

MSB LSB

Content OSENS[7:0]

Reset value 00000000

Access R/W

Bit Description OSENS[7:0] : Low byte of sensor offset setting

6.5.2.1.2 Programmable Gain Amplifier (PGA)

The low noise, low offset programmable gain amplifier (PGA) can cope with a wide range of full scale differential input voltages. Superior noise performance of this sensor front-end allows sensor signal conditioning for low sensit-ivity bridges with sensitivity smaller than 1 mV/V with excellent signal-to-noise ratio (SNR). The PGA provides a dif-ferential output for the following AD converter in the sensor signal path.

A configurable switch at the input allows for adaptation of the sensor signal polarity (register bit SENSPGA.POL)

The amplification can be programmed to 16 values arranged in a harmonic sequence in order to enable an optimum adaptation to the sensitivity of the particular sensor. The range of gain settings of the PGA (not to confusewith the total gain) spreads over the range given in Table 6.5.2-1. For the higher gain settings a certain factor of thegain is performed by digital multiplication. This gain range ensures that large sensor signals can be processed and also small input voltages are sufficiently amplified to make best use of the input range of the ADC.

EXHI

EXLO

Sensor bridge

INP

INN

fCHOP

Input mixer,polarity switch

resistive DAC forbridge offset compensation

PGA stage 1PGA stage 2 PGA stage 3

to DS ADC

resistive DAC forbridge offset compensation

Figure 6.5.2.1.2-1: Programmable Gain Amplifier




Table 6.5.2.1.2-1: Register SENSPGA (0x78) Sensor PGA configuration

MSB LSB

Content POL GPGA[3:0]

Reset value 0 0 0 0 00000

Access R R R R/W R/W

Bit Description POL : Sensor input polarity• 0b : normal• 1b : reverseGPGA[3:0] : Gain of PGA

6.5.2.2 ΔΣ-Modulator for Sensor Signal Chain

After the coarse sensor offset compensation and amplification the sensor signal is fed to a single bit, 2nd order Δ Σ ADC with fully differential input.

The reference voltage of the ΔΣ-modulator tracks the supply voltage of the sensor bridge VEXHI to ensure ratiometricoperation of the signal acquisition chain. The Δ Σ-ADC output provides 14 bit words including sign.

The ADC has a symmetric maximum input voltage range +/- VIN . The output voltage of the PGA must be smaller than the maximum input voltage in order to avoid clipping and other non-linear distortions.

Note: The PGA output voltage is the sum of the input voltage (including the bridge-offset) plus the PGA-offset (-VOS,PGA < offset < +VOS,PGA) multiplied by the PGA-gain. The specified maximum input signal (as given in Table 6.5.2-1) for the different gain settings also takes into account the PGA-offset.

Modulatorinput

Modulatoroutputbit stream

b1 z -1

1-z -1

ΔΣ-Modulator coefficients (t.b.d.):a

1 = 0.3, a

2 = 0.5, b

1 = 0.3, c

1 = 0.8

-a2

z -1

1-z -1

-a1

c1

Figure 6.5.2.2-1: 2nd order Delta Sigma Modulator Structure

6.5.2.3 Digital Low-pass Filter

After the mixer- and the decimation filter-stage (Figure 6.5.2-1, Ch. 6.5.2 Sensor Path), the sensor signal is low-pass filtered in a 2nd order digital filter. This filter can be configured by the data LPFC[2:0] of the register SENSLP.

The transfer function of the 2nd order low-pass is described as follows:

; where LPFC [2, 3, 4, 5, 6, 7]




The data in LPFC[2:0] herein defines the -3dB corner frequency fc . This corner frequency is calculated by the equation:

; where fchop is the chopper frequency of the PGA amplifier.

The output of the filter is the raw signal of the sensor path SRAW which is a signed value. The tolerance of the -3dB corner frequency equals the tolerance of the master clock frequency fCLK. With the register data set LPFC to 0 or 1 the corner frequency will be the same as for LPFC = 2.

Table 6.5.2.3-1: Digital Low-pass Filter: -3dB corner frequency

LPFC 3-dB frequency fc settling time: 10% to 90%

0b010 = 2 4.7 kHz 160 µs

0b011 = 3 2.2 kHz 160 µs

0b100 = 4 1.05 kHz 300 µs

0b101 = 5 0.52 kHz 650 µs

0b110 = 6 0.26 kHz 1.3 ms

0b111 = 7 0.13 kHz 2.5 msRemark: for LPF-settings 2, 3, 4 the settling time is dominated by the sampling rate (fchop / 3)

Table 6.5.2.3-2: Register SENSLP (0x7A) Sensor low-pass digital filter coefficient

MSB LSB

Content reserved reserved reserved reserved reserved LPFC[2:0]


Access R R R/W R/W R/W R/W

Bit Description LPFC[2:0] : 2nd order Low-pass filter coefficients

6.5.3 Sensor Signal CorrectionThe sensor and the temperature signal are first processed by digital filters as a part of the Δ Σ ADC to gain digitizedraw data with an accuracy up to 14 bit for sensor (SRAW) and 14 bit for temperature raw data (TRAW).

The raw data can be read via SIO by the command GETSIG (see ch. 6.5.5.3) as 16 bit unsigned values (SRAW [15:0] & TRAW [15:0]).

A dedicated arithmetic unit processes the incoming raw data of the sensor SRAW and the temperature TRAW to com-pensate for temperature dependence of the sensor offset, sensitivity and non-linearities up to 3 rd order.

Pre-processing Temperature Data

For a rough normalization of the temperature data the offset can be corrected with 6 Bit (TEMPDIG.TOFF) and the gain can be adjusted with a 2 Bit left shift parameter (TEMPDIG.TGAIN):

;

where TRAW [ -1 , +1 -2-13 ]; TGAIN {0,1,2,3} and TOFF [ -1 , + 1-2-5 ]




Pre-processing Sensor Data

To match sensor data a gain can be adjusted with a 3 Bit parameter (Table 6.5.3-27.SGAIN) in the two's comple-ment representation :

,where SGAIN [ -3 , +3 ].

The following table shows the programmable gain factors.

Table 6.5.3-1: Gain Factor of SGAIN[2:0]

SGAIN[2:0] 2-SGAINDEC GAIN FACTOR

011b 2-3 1/8

010b 2-2 1/4

001b 2-1 1/2

000b 20 1

111b 21 2

110b 22 4

101b 23 8

Sensor Model The sensor bridge output S is approximated by:

The correction function C(S,T) implemented in E520.44 is described by the following equation:

The definition of variables is given in the next table:

Table 6.5.3-2: Symbol Table

Symbol Description

P Main physical input parameter of sensor

S Sensor raw data

T Sensor temperature (sensor cross sensitivity), offset corrected

k0 Target function offset (user defined during calibration)

k1 Target function conversion factor (user defined during calibration)

Sensor Data Correction The correction is performed in two steps:

1. Compensate for offset and gain temperature dependence:

2. Remove 2nd and 3rd order non-linearities from the intermediate result X:




The coefficients c0 ... c10 , TOFF, TGAIN and SGAIN are computed externally during the calibration process (soft-ware with parameter optimization calculation algorithms). After the calibration procedure these coefficient have to be copied to the corresponding data registers and stored permanently in the embedded E²PROM data area.

Table 6.5.3-3: Coefficient Table

Symbol Description

c0 Sensor offset coefficient

c1 Sensor gain coefficient

c2 Temperature coefficient of sensor offset 1st order

c3 Temperature coefficient of sensor offset 2nd order

c4 Temperature coefficient of sensor offset 3rd order

c5 Temperature coefficient of sensor gain 1st order

c6 Temperature coefficient of sensor gain 2nd order

c7 Temperature coefficient of sensor gain 3rd order

c8 2nd order non-linearity coefficient

c9 3rd order non-linearity coefficient

c10 Temperature coefficient of 2nd order non-linearity

Table 6.5.3-4: Sensor Signal Correction Register


C10_H 0x80 High byte of temperature coefficient of 2nd order non-linearity

C10_L 0x81 Low byte of temperature coefficient of 2nd order non-linearity

C9_H 0x82 High byte of 3rd order non-linearity coefficient

C9_L 0x83 Low byte of 3rd order non-linearity coefficient

C8_H 0x84 High byte of 2nd order non-linearity coefficient

C8_L 0x85 Low byte of 2nd order non-linearity coefficient

C7_H 0x86 High byte of temperature coefficient of sensor gain (3rd order)

C7_L 0x87 Low byte of temperature coefficient of sensor gain (3rd order)

C6_H 0x88 High byte of temperature coefficient of sensor gain (2nd order)

C6_L 0x89 Low byte of temperature coefficient of sensor gain (2nd order)

C5_H 0x8A High byte of temperature coefficient of sensor gain (1st order)

C5_L 0x8B Low byte of temperature coefficient of sensor gain (1st order)

C4_H 0x8C High byte of temperature coefficient of sensor offset (3rd order)

C4_L 0x8D Low byte of temperature coefficient of sensor offset (3rd order)

C3_H 0x8E High byte of temperature coefficient of sensor offset (2nd order)

C3_L 0x8F Low byte of temperature coefficient of sensor offset (2nd order)

C2_H 0x90 High byte of temperature coefficient of sensor offset (1st order)

C2_L 0x91 Low byte of temperature coefficient of sensor offset (1st order)

C1_H 0x92 High byte of sensor gain coefficient

C1_L 0x93 Low byte of sensor gain coefficient

C0_H 0x94 High byte of sensor offset coefficient

C0_L 0x95 Low byte of sensor offset coefficient

SENSDIG 0x96 Sensor path pre-processing

TEMPDIG 0x97 Temperature path pre-processing




Table 6.5.3-5: Register C10_H (0x80) High byte of temperature coefficient of 2nd order non-linearity

MSB LSB

Content C10[15:8]


Access R/W

Bit Description C10[15:8] : High byte of temperature coefficient of 2nd order non-linearity

Table 6.5.3-6: Register C10_L (0x81) Low byte of temperature coefficient of 2nd order non-linearity

MSB LSB

Content C10[7:0]


Access R/W

Bit Description C10[7:0] : Low byte of temperature coefficient of 2nd order non-linearity

Table 6.5.3-7: Register C9_H (0x82) High byte of 3rd order non-linearity coefficient

MSB LSB

Content C9[15:8]


Access R/W

Bit Description C9[15:8] : High byte of 3rd order non-linearity

Table 6.5.3-8: Register C9_L (0x83) Low byte of 3rd order non-linearity coefficient

MSB LSB

Content C9[7:0]


Access R/W

Bit Description C9[7:0] : Low byte of 3rd order non-linearity

Table 6.5.3-9: Register C8_H (0x84) High byte of 2nd order non-linearity coefficient

MSB LSB

Content C8[15:8]


Access R/W

Bit Description C8[15:8] : High byte of 2nd order non-linearity

Table 6.5.3-10: Register C8_L (0x85) Low byte of 2nd order non-linearity coefficient

MSB LSB

Content C8[7:0]


Access R

Bit Description C8[7:0] : Low byte of 2nd order non-linearity




Table 6.5.3-11: Register C7_H (0x86) High byte of temperature coefficient of sensor gain (3rd order)

MSB LSB

Content C7[15:8]


Access R/W

Bit Description C7[15:8] : High byte of temperature coefficient of sensor gain (3rd order)

Table 6.5.3-12: Register C7_L (0x87) Low byte of temperature coefficient of sensor gain (3rd order)

MSB LSB

Content C7[7:0]


Access R/W

Bit Description C7[7:0] : Low byte of temperature coefficient of sensor gain (3rd order)

Table 6.5.3-13: Register C6_H (0x88) High byte of temperature coefficient of sensor gain (2nd order)

MSB LSB

Content C6[15:8]


Access R/W

Bit Description C6[15:8] : High byte of temperature coefficient of sensor gain (2nd order)

Table 6.5.3-14: Register C6_L (0x89) Low byte of temperature coefficient of sensor gain (2nd order)

MSB LSB

Content C6[7:0]


Access R/W

Bit Description C6[7:0] : Low byte of temperature coefficient of sensor gain (2nd order)

Table 6.5.3-15: Register C5_H (0x8A) High byte of temperature coefficient of sensor gain (1st order)

MSB LSB

Content C5[15:8]


Access R/W

Bit Description C5[15:8] : High byte of temperature coefficient of sensor gain (1st order)

Table 6.5.3-16: Register C5_L (0x8B) Low byte of temperature coefficient of sensor gain (1st order)

MSB LSB

Content C5[7:0]


Access R/W

Bit Description C5[7:0] : Low byte of temperature coefficient of sensor gain (1st order)




Table 6.5.3-17: Register C4_H (0x8C) High byte of temperature coefficient of sensor offset (3rd order)

MSB LSB

Content C4[15:8]


Access R/W

Bit Description C4[15:8] : High byte of temperature coefficient of sensor offset (3rd order)

Table 6.5.3-18: Register C4_L (0x8D) Low byte of temperature coefficient of sensor offset (3rd order)

MSB LSB

Content C4[7:0]


Access R/W

Bit Description C4[7:0] : Low byte of temperature coefficient of sensor offset (3rd order)

Table 6.5.3-19: Register C3_H (0x8E) High byte of temperature coefficient of sensor offset (2nd order)

MSB LSB

Content C3[15:8]


Access R/W

Bit Description C3[15:8] : High byte of temperature coefficient of sensor offset (2nd order)

Table 6.5.3-20: Register C3_L (0x8F) Low byte of temperature coefficient of sensor offset (2nd order)

MSB LSB

Content C3[7:0]


Access R/W

Bit Description C3[7:0] : Low byte of temperature coefficient of sensor offset (2nd order)

Table 6.5.3-21: Register C2_H (0x90) High byte of temperature coefficient of sensor offset (1st order)

MSB LSB

Content C2[15:8]


Access R/W

Bit Description C2[15:8] : High byte of temperature coefficient of sensor offset (1st order)

Table 6.5.3-22: Register C2_L (0x91) Low byte of temperature coefficient of sensor offset (1st order)

MSB LSB

Content C2[7:0]


Access R/W

Bit Description C2[7:0] : Low byte of temperature coefficient of sensor offset (1st order)




Table 6.5.3-23: Register C1_H (0x92) High byte of sensor gain coefficient

MSB LSB

Content C1[15:8]


Access R/W

Bit Description C1[15:8] : High byte of sensor gain coefficient

Table 6.5.3-24: Register C1_L (0x93) Low byte of sensor gain coefficient

MSB LSB

Content C1[7:0]


Access R/W

Bit Description C1[7:0] : Low byte of sensor gain coefficient

Table 6.5.3-25: Register C0_H (0x94) High byte of sensor offset coefficient

MSB LSB

Content C0[15:8]


Access R/W

Bit Description C0[15:8] : High byte of sensor offset coefficient

Table 6.5.3-26: Register C0_L (0x95) Low byte of sensor offset coefficient

MSB LSB

Content C0[7:0]


Access R/W

Bit Description C0[7:0] : Low byte of sensor offset coefficient

Table 6.5.3-27: Register SENSDIG (0x96) Sensor path pre-processing

MSB LSB

Content SGAIN[2:0]


Access R R R R R R/W

Bit Description SGAIN[2:0] : Sensor data gain with sign bit in two's complement representation

Table 6.5.3-28: Register TEMPDIG (0x97) Temperature path pre-processing

MSB LSB

Content TOFF[5:0] TGAIN[1:0]

Reset value 000000 00

Access R/W R/W

Bit Description TOFF[5:0] : Signed temperature offsetTGAIN[1:0] : Temperature data gain(multiply by left shift)




6.5.4 Temperature PathThe temperature acquisition runs independent of the sensor signal acquisition. Therefore, the sensor signal is sampled periodically without interruptions necessary for temperature measurement.Besides an internal temperature measurement the analogue input terminal TSEN provides a possibility to connect an external temperature sensor to the device.

A first order 14-bit delta-sigma ADC is used for AD-conversion of the temperature signal. The voltage VDDA is used as reference of this ADC.The allowed ADC range is limited in order to indicate a missing or defect temperature sensor. The voltage drop at asilicon diode will never exceed the range 0.2V to 0.9V. Thus, a drop of more than 1.65 V (= 0.5 * VDDA) or below about 0.1V will be indicated as an error.

On-chip Temperature MeasurementIn this mode the forward voltage of a diode connected to the bridge excitation voltage VEXHI is used to measure the temperature. The measurement method is similar to the temperature measurement with an external diode. This diode forward voltage biased at constant current ITSEN,PD exhibits a typical temperature drift of -2 mV/K.

Temperature Measurement by External DiodeIn this mode, the forward voltage drop VEXHI - VTSEN across an external diode connected between EXHI (anode) and TSEN (cathode) is used as input to the temperature ADC.

EXHI

EXLO

TSEN

VSSA

14 bitDS-ADC

VREFH

VINH

VINLVREFL

VDDA (3.3V)Bridge

Digital Temp-Out

Figure 6.5.4-1: Temperature Measurement Channel

Table 6.5.4-1: Register TEMPIF (0x7B) Temperature Path configuration

MSB LSB

Content TSEN

Reset value 0 0 0 0 0 0 0 0

Access R R R R R R R R/W

Bit Description TSEN : Temperature input control• 0b : internal Temperature Sensor• 1b : external Temperature Sensor




6.5.5 Output StageThe output stage is capable to work in three different operating modes:• Analogue voltage output mode,• SENT Mode (digital output data), and• as a bi-directional serial input output (SIO Mode).

See chapter 6.4 for details of the configuration.

6.5.5.1 Analogue Voltage Mode

In Analogue Mode the amplified, digitally corrected, and filtered sensor signal is fed into an output DAC to generatean analogue signal representation. A subsequent buffer amplifier with a gain of 2 provides a voltage at terminal OUT with a signal ratiometric to the supply voltage VVS. The output voltage range is determined by programming voltage minimum and maximum limits (e.g. 10% to 90% of VVS).

The output is protected against over-voltage and reverse polarity and it is current limited to avoid damage in case of short circuits to GND or supply VS.

VVS

Gain = 2

OUTPcorr

/ Sraw

Data 12-bit resistive string-DAC

VREF

VVS

/ 2

Limiter

Figure 6.5.5.1-1: Analogue Output Stage

6.5.5.1.1 Limiter

The E520.44 provides a digital limiter defining upper and lower clipping limit at the output of the sensor signal cor-rection. Figure 6.5.5.1.1-1 illustrates the output of the corrected pressure value PCORR sent to the output DAC. The corrected pressure value PCORR will be checked in this stage to be inside the valid working range.In case the corrected DAC input exceeds the upper or the lower clipping limit, the output value will be tied to the value which is pre-set in the clipping registers LIMSENS_H or LIMSENS_L, respectively.




0% / 0x000

Pcorr

%VVS

/ DAC [11:0]

100% / 0xFFF

CLHI,MIN

87.5% / 0xE01

CLLO,MAX

12.5% / 0x1FE

2 x SENSUL[7:0]

2 x SENSLL[7:0]

CLLO

CLHI

Figure 6.5.5.1.1-1: Output limitation characteristic (analogue output)

The upper clipping limit can be configured with the register LIMSENS.SENSUL and lower clipping limit with LIM-SENS.SENSLL respectively. The decimal values of upper-/lower limit can be calculated by:

• Upper clipping limit CLHI = 3585dec + (2 * LIMSENS.SENSUL[7:0]dec)• Lower clipping limit CLLO = 2 * LIMSENS.SENSLL[7:0]dec

Note: Digital sensor output data read via the serial I/O interface will not be subject to clipping (no limitation)

Table 6.5.5.1.1-1: Sensor Limiter Register


LIMSENS_H 0x7C Setting of Sensors upper Clipping Value

LIMSENS_L 0x7D Setting of Sensors lower Clipping Value

Table 6.5.5.1.1-2: Register LIMSENS_H (0x7C) Setting of Sensors upper Clipping Value

MSB LSB

Content SENSUL[7:0]


Access R/W

Bit Description SENSUL[7:0] : unsigned upper clipping limit of sensor signal

Table 6.5.5.1.1-3: Register LIMSENS_L (0x7D) Setting of Sensors lower Clipping Value

MSB LSB

Content SENSLL[7:0]


Access R/W

Bit Description SENSLL[7:0] : unsigned lower clipping limit of sensor signal




6.5.5.1.2 12-bit Output DAC

The output 12-bit DAC converts the digital output to an analogue voltage. It uses a reference voltage VVS/2 generat-ing a ratiometric behaviour of the analogue output. The DAC output is amplified by a factor 2 in the output buffer stage (Figure 6.5.5.1-1) which also provide over-voltage protection and reverse-voltage protection at OUT.

The update rate of the corrected data received by the DAC is one third of the chopper frequency:fDAC = fchop/3 ( 6.7kHz).




6.5.5.2 SENT Mode

The device can be operated alternatively with a digital SENT data output (SENT: Single Edge Nibble Transmission). In SENT-Mode (MODECONF.OUTMODE = 1b) the pin OUT operates as a push-pull stage to gener-ate the digital output data. The output is protected against over-voltage and reverse polarity.

6.5.5.2.1 SENT Physical Interface

The SENT physical interface provides a push-pull output driver, which complies to the requirements of the standardSAE J2716, JAN2010.The required external circuitry is depicted in Figure 8.2-1 with corresponding component parameters in ch. 8.2. TheSENT output driver with this external circuitry creates a typical data pulse shape on the SENT interconnection wire as shown in the next figure.

V(SENT) [V]

0.5

3.8

4.5

1.39

tSTABLE,LOW

tSTABLE,HIGH

t

1.1

tFALL

tRISE

Figure 6.5.5.2.1-1: SENT Signal at Interconnection Wire

6.5.5.2.2 SENT Protocol

The SSP provides a SENT signal output. This protocol is specified by the SAE J2716-Standard and described below.

SENT (Single Edge Nibble Transmission) is a one wire protocol that encodes data nibbles (four bits) by one pulse per nibble. The pulse length is measured between two falling edges and reflects the nibble value. The minimum nibble pulse length, NLENGTH is NLENGTH,MIN clock ticks (representing the nibble value 0x0) and the maximum nibble pulse length is NLENGTH,MAX clock ticks (NLENGTH,MIN + 15 ticks, representing 0xF).

The communication is unidirectional: the SSP slave sends pressure signal values autonomously whereas the mas-ter acts as a receiver only.

SENT Message Format

Each SENT message consists of nine (SENTCONF.NPP = 1b) or ten (SENTCONF.NPP = 0b) negative pulses on the transmission line depending on configuration without or with a pause pulse added to the message. The follow-ing picture illustrates one sent message without the optional pause pulse:




DataNibble 1

DataNibble 2

DataNibble 3

DataNibble 4

DataNibble 5

DataNibble 6

CRCNibbleSync frame

StatusNibble

CRCNibble Sync frame

Message frame, 24 bit dataPrevious message Subsequent message

Figure 6.5.5.2.2-1: SENT Message without Pause Pulse (SENTCONF.NPP = 1b)

The elementary unit of time measurement in the context of the SENT protocol is called a clock tick (tTICK). By defaultthis time is tTICK,TYP (12µs) long, but other values can be configured with SENTCONF.TICKSEL[3:0].

The message starts with the sync frame with a fixed duration of SFRAME clock ticks. This pulse is used by the receiver to detect the start of a message and to measure the transmitters clock tick time. Next is the status nibble, followed by six data nibbles and a checksum nibble (CRC). Since the pulse times depend on the transmitted values(except for the sync frame) the length of such a SENT message is not fixed.With the SENT configuration bit cleared (SENTCONF.NPP = 0b) , a pause pulse will be added after the CRC nibble. The length of that pulse is always adapted to the previously sent data to ensure a constant message length of MLENGTH clock ticks, as shown in the following diagram.

DataNibble 1

DataNibble 2

DataNibble 3

DataNibble 4

DataNibble 5

DataNibble 6

CRCNibbleSync frame

StatusNibble

CRCNibble Sync frame

Message frame, 24 bit dataPrevious message Subsequent message

Pausepulse

Figure 6.5.5.2.2-2: SENT Message with Pause Pulse (SENTCONF.NPP = 0b)

Status Nibble DefinitionThe status nibble bits contain the following data:• Bit 0 is set if and only if an error is present. In this case the transmitted pressure value is either 0 (initialization

error, during device initialization) or 4090 (diagnostic error, otherwise).• Bit 1 is 0.• Bit 2 and 3 contain information for serial data transmission (see below: Serial Data).

Data NibblePressure values are always transmitted within 3 nibbles, resulting in 12 bits.

SENT standardizes several application specific protocols of which the SSP provides the protocol called P/S (securepressure sensor) or P/S/t (secure pressure sensor with temperature in supplementary channel). The protocol con-figuration is defined by a bit in the configuration register: SENTCONF.ENTSENT

The 6 data nibbles contain the following information:• Data nibbles 1 to 3 contain pressure information. The pressure value is sent as a 12-bit unsigned integer num-

ber, the most significant nibble first.• Data nibble 4 and 5 contain an 8-bit rolling counter, most significant nibble first. This modulo-256 counter is

incremented with every message.• Data nibble 6 is the inverted data nibble 1.

Supplementary data and status information are transmitted as Enhanced Serial Messages in the so called "slow channel", see Table 6.5.5.2.2-2.Some values of data nibbles 1 to 3 (pressure data) are reserved for special purposes, see the following table.




Table 6.5.5.2.2-1: Error Codes in Data Nibbles

Signal Interpretation Signal Value

unused error codes 4091..4095

diagnostic error 4090

unused error code 4089

high clamp 4088

pressure data 2..4087

low clamp 1

initialization 1) 01) The initialisation time of SENT (MODECONF.OUTMODE = 1b) depends on internal configuration time, tINIT and the duration of the different power-up BISTs activated such as RAM-, EEPROM-, ROM- and AU-BIST (s. ch. 6.4, Modes of Operation)

Details about the diagnostic error (data = 4090dec) are provided within the enhanced serial message with message ID 0x01, see Table 6.5.5.2.2-3. The initialization code is sent during device initialization.

CRC NibbleThe CRC nibble contains checksum data. It's generation is defined in the SAE J2716 standard.

Serial Data

The status nibble embeds two bits for so called serial data transmission. 18 of these bit pairs that are transmitted in18 consecutive messages result in one enhanced serial message. This is called the slow channel whereas data that is transmitted within the data nibbles belongs to the fast channels.The format of enhanced serial messages (with 8-bit ID) is shown in the following picture:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Status nibble bit 3

SENT messagenumber

1 1 1 1 1 1 0 0 ID[7:4] 0 ID[3:0] 0

CRC6[5:0] DATA[11:0]Status nibble bit 2

Figure 6.5.5.2.2-3: Enhanced serial Message Format

An enhanced serial message carries 8-bit ID information and 12-bit data information (the E520.44 does not support4-bit ID messages). Additionally a 6-bit CRC checksum allows for integrity checking (see SAE J2716). A subset of all possible IDs is sent in a repetitive manner (see Figure 6.5.5.2.2-4, Figure 6.5.5.2.2-5).The available enhanced serial message IDs are defined in the following table.

Table 6.5.5.2.2-2: Enhanced serial Message IDs

ID[7:0] DATA[11:0] description accordingto SENT standard

DATA[11:0] origin

0x01 Diagnostic Error Code see Table 6.5.5.2.2-3

0x03 Sensor Type • SENTCONF.ENTSENT = 0b : DATA[11:0] = 0x003 (P/S)• SENTCONF.ENTSENT = 1b : DATA[11:0] = 0x005 (P/S/t)

0x04 Configuration Code DATA[11:0] = CCODE

0x05 Manufacturer Code DATA[11:0] = MCODE

0x06 SENT standard revision DATA[11:0] = 0x003(SAE J2716, JAN2010)

0x07 Pressure characteristic X1 DATA[11:0] = PX1[11:0]

0x08 Pressure characteristic X2 DATA[11:0] = PX2[11:0]




ID[7:0] DATA[11:0] description accordingto SENT standard

DATA[11:0] origin

0x09 Pressure characteristic Y1 DATA[11:0] = PY1[11:0]

0x0A Pressure characteristic Y2 DATA[11:0] = PY2[11:0]

0x10 Temperature data (unsigned) DATA[11:0] = T[11:0] 1)

0x12 Temperature characteristic X1 DATA[11:0] = TX1[11:0] 1)

0x13 Temperature characteristic X2 DATA[11:0] = TX2[11:0] 1)

0x14 Temperature characteristic Y1 DATA[11:0] = TY1[11:0] 1)

0x15 Temperature characteristic Y2 DATA[11:0] = TY2[11:0] 1)

0x29 Sensor ID #1 DATA[11:0] = SID1[11:0]

0x2A Sensor ID #2 DATA[11:0] = SID2[11:0]

0x2B Sensor ID #3 DATA[11:0] = SID3[11:0]

0x2C Sensor ID #4 DATA[11:0] = SID4[11:0]1) Only for sensor type selection P/S/t (SENTCONF.ENTSENT = 1b)

The next table describes the diagnostic error codes (DECs) transferred at message ID 0x01 in descending order of priority (which is relevant if two different error codes would occur at the same time).The error code is generated from the content of diagnosis registers ERRC (error code) and ENERR (enable error, see ch. 6.6.6, Diagnostic registers). The relations of error enabling and error code are described briefly in column Details.

Table 6.5.5.2.2-3: Diagnostic Error Codes (DEC)

Value Definition Details

0x000 no error

0x003 Initialization error 1. Power on EEPROM self-test failed : this code is sent, then reset and retest are performed2. Any enabled error occurs during initialization, after initializa-tion next DEC identifies error

0xA00 Bridge excitation short check failed

SERR1 and ENSERR1

0xA01 Sensor connections check failed

• SENSOFF.PDSENS = 0b (SERR0 and ENSERR0) or (SERR2 and ENSERR2)

• SENSOFF.PDSENS = 1b (SERR0 and ENSERR0) or (SERR3 and ENSERR3) or (SERR2 and ENSERR2)

0xA02 EEPROM shadow signa-ture error

EECBERR and ENEECBERR

0xA03 Arithmetic unit error AUBERR and ENAUBERR

0xF00 Sensor connection checkfailed 1)

• SERR4 and ENSERR4 ( = short sensor INP to INN )

0xFyy Other error 1) • bit 0 : V3ERR and EN3ERR• bit 1 : SAMPSAT and ENSAMPSAT• bit 2 : SADCSDAT and ENSADCSAT• bit 3 : TADCSAT and ENTADCSAT• bit 4 : TNORMSAT and ENTNORMSAT• bit 5 : CORRSAT and ENCORRSAT 2)

• bit 6 : n/a• bit 7 : V5ERR and EN5ERR

1) All errors with DEC 0xFyy are transmitted parallel, there is no priority2) The pressure data output on SENT is saturated according to SENT standard. This error bit should be disabled (ENERR.ENCORRSAT = 0b) to prevent fast channel error code 4090.




The E520.44 supports enhanced serial messages, only in the slow channel, but not the "short serial messages" of the SENT standard.

The transmission of enhanced serial data is looped according to the following two schemes depending on the set-ting of bit ENTSENT in the SENT configuration register SENTCONF (see Table 6.5.5.2.2-5), i.e. if it is configured as sensor type P/S or P/S/t.

PressureCharacterisic Sensor ID

1ID01

2ID03

3ID01

4ID04

5ID01

6ID05

7ID01

8ID06

9ID01

10ID07

11ID01

12ID08

13ID01

14ID09

15ID01

16ID0A

17ID01

18ID29

19ID01

20ID2A

21ID01

22ID2B

23ID01

24ID2C

Diagnostic Error Code

...

Figure 6.5.5.2.2-4: Slow Channel Message Cycle for SENTCONF.ENTSENT = 0b (P/S)

PressureCharacterisic

1ID01

2ID03

3ID01

4ID04

5ID01

6ID05

7ID01

8ID06

9ID01

10ID07

11ID01

12ID08

13ID01

14ID09

15ID01

16ID0A

17ID01

18ID12

19ID01

20ID13

25ID01

26ID14

27ID01

28ID15

Diagnostic Error Code

...

21ID01

22 23ID01

24ID10

ID10

Temperature DataSensor ID

ID29

ID2A

33ID01

34ID2B

35ID01

36ID2C

29ID01

30 31ID01

32

TemperatureCharacterisic

Figure 6.5.5.2.2-5: Slow Channel Message Cycle for SENTCONF.ENTSENT = 1b (P/S/t)

Temperature Data on Slow Channel

If the SSP E520.44 is configured as sensor type P/S/t with SENTCONF.ENTSENT = 1b the normalized temperatureT is transmitted via SENT slow channel. This temperature has a specific characteristic which is also transmitted via SENT slow channel with the characteristic values TX1, TX2, TY1 and TY2. With this characteristic values the trans-mitted temperature T (12-bit data in message ID 0x10) is be mapped to the SENT standard temperature character-istic (SAE J2716).The following equation describes the transformation of T to an absolute temperature TABS (in K), where TABS is an 12-bit unsigned fixed-point number with binary point between bit2 and bit3 (data range 0.125 ... 511 corresponds to200.125 K ... 711.0 K):

Error Handling

Depending on the configuration, the SSP will perform several power-on self tests after power-up. While these tests are running no SENT messages will be transmitted.

If the tests are passed successfully, the SSP will still be within its initialization phase until valid pressure values are available. During this phase the E520.44 will transmit the fast channel initialization signal with value 0 (seeTable 6.5.5.2.2-1). If an enabled diagnostic error (selected by register ENERR) occurred during the power-up sequence a fast channel error value 4090dec would be transmitted and the SENT error flag is set. Also, as a enhanced serial message the diagnostic error code 0x003 would be transmitted (see Table 6.5.5.2.2-3).

If an enabled diagnosis occurs while the SSP E520.44 is in full operation and transmits pressure values, also the fast channel error value 4090dec is transmitted with set error flag (status bit 0) until the error disappears. The dia-gnostic error code in the enhanced serial message transmits information about the error source and all error flags in the error code register ERRC are reset subsequently. If no error is present any more the next diagnostic error code will be 0x000.




For short temporary errors, the error flag and the fast channel error value 4090dec is sent for at least 3 subsequent fast frames. In this case, it may happen the slow channel DEC to identify the intermediate error will be transmitted only when the fast channel already sends valid pressure values again.

Register Description

Table 6.5.5.2.2-4: SENT Registers


SENTCONF 0x7F SENT configuration register

CCODE_H 0x98 High Nibble of Configuration Code1)

CCODE_L 0x99 Low byte of Configuration Code1)

MCODE_H 0x9A High Nibble of Manufacturer Code1)

MCODE_L 0x9B Low Byte of Manufacturer Code1)

TX1_H/PX1_H 0x9C High Nibble of Temperature Characteristic X1, High Nibble of Pressure Charac-teristic X1,1)

PX1_L 0x9D Low Byte of Pressure characteristic X11)

TX2_H/PX2_H 0x9E High Nibble of Temperature Characteristic X2, High Nibble of Pressure Charac-teristic X21)

PX2_L 0x9F Low Byte of Pressure characteristic X21)

TY1_H/PY1_H 0xA0 High Nibble of Temperature Characteristic Y1, High Nibble of Pressure Charac-teristic Y11)

PY1_L 0xA1 Low Byte of Pressure characteristic Y11)

TY2_H/PY2_H 0xA2 High Nibble of Temperature Characteristic Y2, High Nibble of Pressure Charac-teristic Y21)

PY2_L 0xA3 Low Byte of Pressure characteristic Y21)

TX1_L 0xA4 Low Byte of Temperature characteristic X11)

TX2_L 0xA5 Low Byte of Temperature characteristic X21)

TY1_L 0xA6 Low Byte of Temperature characteristic Y11)

TY2_L 0xA7 Low Byte of Temperature characteristic Y21)

SID1_H 0xA8 High Nibble of Sensor ID#11)

SID1_L 0xA9 Low Byte of Sensor ID#11)

SID2_H 0xAA High Nibble of Sensor ID#21)

SID2_L 0xAB Low Byte of Sensor ID#21)

SID3_H 0xAC High Nibble of Sensor ID#31)

SID3_L 0xAD Low Byte of Sensor ID#31)

SID4_H 0xAE High Nibble of Sensor ID#41)

SID4_L 0xAF Low Byte of Sensor ID#41)

1) Refers to Table 6.5.5.2.2-2, Enhanced Serial Message ID in slow Channel




Table 6.5.5.2.2-5: Register SENTCONF (0x7F) SENT configuration register

MSB LSB

Content ENTSENT NPP TICKSEL[3:0]


Access R R R/W R/W R/W

Bit Description ENTSENT : Enable temperature data on SENT output, changes sensor type according SENT Standard :0b : sensor type 0x003 (P/S)1b : sensor type 0x005 (P/S/t)

NPP : No SENT Pause Pulse0b : pause pulse1b : no pause pulse

TICKSEL[3:0] : SENT clock tick selection0000b = 12 us0001b = 3 us0010b = 4 us0011b = 5 us0100b = 6 us0101b = 8 us0110b = 10 us0111b = 12 us1000b = 16 us1001b = 24 us1010b = 32 us1011b = 40 us1100b = 48 us1101b = 64 us1110b = 80 us1111b = 90 us

Table 6.5.5.2.2-6: Register CCODE_H (0x98) High Nibble of Configuration Code

MSB LSB

Content CCODE[11:8]


Access R R R R R/W

Bit Description CCODE[11:8] : High Nibble of Configuration Code data field

Table 6.5.5.2.2-7: Register CCODE_L (0x99) Low byte of Configuration Code

MSB LSB

Content CCODE[7:0]


Access R/W

Bit Description CCODE[7:0] : Low byte of Configuration Code data field




Table 6.5.5.2.2-8: Register MCODE_H (0x9A) High Nibble of Manufacturer Code

MSB LSB

Content MCODE[11:8]


Access R R R R R/W

Bit Description MCODE[11:8] : High Nibble of Manufacturer Code data field

Table 6.5.5.2.2-9: Register MCODE_L (0x9B) Low Byte of Manufacturer Code

MSB LSB

Content MCODE[7:0]


Access R/W

Bit Description MCODE[7:0] : Low byte of Manufacturer Code data field

Table 6.5.5.2.2-10: Register TX1_H/PX1_H (0x9C) High Nibble of Temperature Characteristic X1, High Nibble of Pressure Characteristic X1,

MSB LSB

Content TX1[11:8] PX1[11:8]


Access R/W R/W

Bit Description TX1[11:8] : High Nibble of Temperature characteristic X1 data fieldPX1[11:8] : High Nibble of Pressure characteristic X1 data field

Table 6.5.5.2.2-11: Register PX1_L (0x9D) Low Byte of Pressure characteristic X1

MSB LSB

Content PX1[7:0]


Access R/W

Bit Description PX1[7:0] : Low byte of Pressure characteristic X1 data field

Table 6.5.5.2.2-12: Register TX2_H/PX2_H (0x9E) High Nibble of Temperature Characteristic X2, High Nibble of Pressure Characteristic X2

MSB LSB

Content TX2[11:8] PX2[11:8]


Access R/W R/W

Bit Description TX2[11:8] : High Nibble of Temperature characteristic X2 data fieldPX2[11:8] : High Nibble of Pressure characteristic X2 data field




Table 6.5.5.2.2-13: Register PX2_L (0x9F) Low Byte of Pressure characteristic X2

MSB LSB

Content PX2[7:0]


Access R/W

Bit Description PX2[7:0] : Low byte of Pressure characteristic X2 data field

Table 6.5.5.2.2-14: Register TY1_H/PY1_H (0xA0) High Nibble of Temperature Characteristic Y1, High Nibble of Pressure Characteristic Y1

MSB LSB

Content TY1[11:8] PY1[11:8]


Access R/W R/W

Bit Description TY1[11:8] : High Nibble of Temperature characteristic Y1 data fieldPY1[11:8] : High Nibble of Pressure characteristic Y1 data field

Table 6.5.5.2.2-15: Register PY1_L (0xA1) Low Byte of Pressure characteristic Y1

MSB LSB

Content PY1[7:0]


Access R/W

Bit Description PY1[7:0] : Low byte of Pressure characteristic Y1 data field

Table 6.5.5.2.2-16: Register TY2_H/PY2_H (0xA2) High Nibble of Temperature Characteristic Y2, High Nibble of Pressure Characteristic Y2

MSB LSB

Content TY2[11:8] PY2[11:8]


Access R/W R/W

Bit Description TY2[11:8] : High Nibble of Temperature characteristic Y2 data fieldPY2[11:8] : High Nibble of Pressure characteristic Y2 data field

Table 6.5.5.2.2-17: Register PY2_L (0xA3) Low Byte of Pressure characteristic Y2

MSB LSB

Content PY2[7:0]


Access R/W

Bit Description PY2[7:0] : Low byte of Pressure characteristic Y2 data field




Table 6.5.5.2.2-18: Register TX1_L (0xA4) Low Byte of Temperature characteristic X1

MSB LSB

Content TX1[7:0]


Access R/W

Bit Description TX1[7:0] : Low byte of Temperature characteristic X1 data field

Table 6.5.5.2.2-19: Register TX2_L (0xA5) Low Byte of Temperature characteristic X2

MSB LSB

Content TX2[7:0]


Access R/W

Bit Description TX2[7:0] : Low byte byte of Temperature characteristic X2 data field

Table 6.5.5.2.2-20: Register TY1_L (0xA6) Low Byte of Temperature characteristic Y1

MSB LSB

Content TY1[7:0]


Access R/W

Bit Description TY1[7:0] : Low byte of Temperature characteristic Y1 data field

Table 6.5.5.2.2-21: Register TY2_L (0xA7) Low Byte of Temperature characteristic Y2

MSB LSB

Content TY2[7:0]


Access R/W

Bit Description TY2[7:0] : Low byte of Temperature characteristic Y2 data field

Table 6.5.5.2.2-22: Register SID1_H (0xA8) High Nibble of Sensor ID#1

MSB LSB

Content SID1[11:8]


Access R R R R R

Bit Description SID1[11:8] : High Nibble of Sensor ID#1 data field

Table 6.5.5.2.2-23: Register SID1_L (0xA9) Low Byte of Sensor ID#1

MSB LSB

Content SID[7:0]


Access R/W

Bit Description SID[7:0] : Low byte of Sensor ID#1 data field




Table 6.5.5.2.2-24: Register SID2_H (0xAA) High Nibble of Sensor ID#2

MSB LSB

Content SID2[11:8]


Access R R R R R/W


Table 6.5.5.2.2-25: Register SID2_L (0xAB) Low Byte of Sensor ID#2

MSB LSB

Content SID2[7:0]


Access R/W

Bit Description SID2[7:0] : Low byte of Sensor ID#2 data field

Table 6.5.5.2.2-26: Register SID3_H (0xAC) High Nibble of Sensor ID#3

MSB LSB

Content SID3[11:8]


Access R R R R R/W


Table 6.5.5.2.2-27: Register SID3_L (0xAD) Low Byte of Sensor ID#3

MSB LSB

Content SID3[7:0]


Access R/W


Table 6.5.5.2.2-28: Register SID4_H (0xAE) High Nibble of Sensor ID#4

MSB LSB

Content SID4[11:8]


Access R R R R R/W


Table 6.5.5.2.2-29: Register SID4_L (0xAF) Low Byte of Sensor ID#4

MSB LSB

Content SID4[7:0]


Access R/W





6.5.5.3 SIO Mode (Serial Input Output)

A serial input / output mode (SIO) allows bidirectional serial communication via the OUT pin to simplify calibration and configuration. To achieve true single-wire operation the SIO shares the OUT pin with the analogue output buf-fer (and the SENT output driver). When the IC is receiving data in SIO-Mode, the buffer amplifier is switched to highimpedance (High Z) state.

SIO Interface

The SIO interface provides access to the internal command processor for configuration and calibration purposes. Measurement data (raw data or corrected data) can be acquired through the SIO interface as well as writing data toconfiguration registers.The SIO data transmission uses the Manchester Code (Biphase-L, falling edge is a logical 1) with a baud rate of DATABAUDRATE. The SIO interface works as a slave only. This means, the E520.44 can never initiate a communica-tion in SIO mode.

00

TC,TX/RX(SIO)

tW(SIO)

1

TW,TX/RX(SIOL)

VIL(SIO)

VIH(SIO)

VOL(SIO)

VOH(SIO)

Figure 6.5.5.3-1: SIO Bit Timing Diagram

SIO Byte Format

Data is transferred byte wise. Each byte is preceded by a start bit which is always '1'. Each Manchester coded bit includes either a falling edge (1) or a rising edge (0) in the middle of a bit cycle time interval tC(SIO).

0 1

TC,TX/RX(SIO) TC,TX/RX(SIO)

Figure 6.5.5.3-2: Manchester Coded Bits

To ensure proper decoding of the received data the bus level should be driven low after the last bit of a byte for at least one bit time tC(SIO) . After the start bit the MSB is transferred first (see Figure 6.5.5.3-3). The first rising edge indicates the start of the byte transmission.

Note: If the LSB is a 0, the SIO line must be driven to 0V actively!




S 1 0 0 0 0 1 0 0

STARTBIT

MSB LSB LOWPHASE

L

10 x tC(SIO)_TX/RX

Figure 6.5.5.3-3: Manchester Coded Byte (Example: command ENACONF 0x84)

The following Figure 6.5.5.3-4 shows a SIO protocol example during configuration mode . Two commands are transmitted by the bus master. The first command is a WRITE command that writes a 16 bit value into the user RAM. The second command GETSIG is used to retrieve pressure measurement data.

WRITE

commandcode 0x9D

from master to slave from slave to master

OUTHV ADDR DATA1 DATA2 CHK ACK GETSIG 0x00 CHK ACK SDATA1 SDATA2 CHK

address datahigh byte

datalow byte

checksum SSP confirmsreceptionwith 0x06

commandcode 0xC3

checksum SSP'sacknowledge

correctedpressurehigh byte

correctedpressurelow byte

checksum

Figure 6.5.5.3-4: SIO communication protocol example

SIO commands

Below the different commands available in SIO mode are described.

Table 6.5.5.3-1: Command Table

CommandName

CommandCode

Validity 1) Description

ENACONF 0x84 W Go to configuration state. Activate full access to the SSP (read, write, BIST start and EEPROM update)

ENADIAG 0x8C W Go to diagnosis state. Activate restricted access to the SSP (read and BIST start)

READ 0x93 C, D Read 16 bit value from configuration memory

WRITE 0x9D C Write 16 bit value to configuration memory

EEUPD 0xA3 C Update EEPROM, all changes on RAM are stored on EEPROM

READEE 0xD3 C, D Read EEPROM and store on RAM

OPERATE 0xAA C, D Restart device with current EEPROM configuration data

BIST 0xB3 C, D Execute built-in self-tests

ANAOUT 0xBC C, D Activate analogue output

GETSIG 0xC3 C, D Read pressure / temperature value

RESET 0xE2 C, D Resets the device1) W - during Startup-Window, C - Configuration State, D - Diagnosis State




Table 6.5.5.3-2: Command ENACONF

Command Name ENACONF - enable full access

Function Go to configuration state. Activates full access to the SSP (read, write, BIST start and EEP-ROM update)

Validity • Only during SIO command window tWINDOW

• If EEPROM write protection bit EE_WP in register MODECONF is set to 0b (See chapter6.4 for modes of operation details)

Command Code Byte 1 : 0x84

Following Bytes Byte 2 : 0xE5 (constant)Byte 3 : 0x5E (constant)Byte 4 : 0xC8 (checksum)

Answer Byte 1 :• 0x06 (ACK). if configuration state is entered• 0x15 (NACK), if command, any parameter or checksum is invalid

Table 6.5.5.3-3: Command ENADIAG

Command Name ENADIAG - enable restricted access

Function Go to diagnosis state. Activate restricted access to the SSP (read and BIST start)

Validity Only during SIO command window tWINDOW (See chapter 6.4 for modes of operation details)

Command Code Byte 1 : 0x8C

Following Bytes Byte 2 : 0xE5 (constant)Byte 3 : 0x5E (constant)Byte 4 : 0xD0 (checksum)

Answer Byte 1 :• 0x06 (ACK), if diagnostic state is entered• 0x15 (NACK), if command, any parameter or checksum is invalid

Table 6.5.5.3-4: Command READ

Command Name READ - read 16 bit value

Function Read a 16 bit value from given address

Validity After activation of configuration or diagnosis state

Command Code Byte 1 : 0x93

Following Bytes Byte 2 : Configuration memory addressByte 3 : Checksum

Answer Byte 1 :• 0x06 (ACK)• Byte 2 - Byte 4 will be sent

• 0x15 (NACK), if address or checksum is invalid• no further Byte will be sent

Byte 2 : High byte of configuration memoryByte 3 : Low byte of configuration memoryByte 4 : Checksum




Table 6.5.5.3-5: Command WRITE

Command Name WRITE - write a 16 bit value

Function Write a 16 bit value to given address

Validity After activation of configuration state

Command Code Byte 1 : 0x9D

Following Bytes Byte 2 : Configuration memory addressByte 3 : High Byte to writeByte 4 : Low Byte to writeByte 5 : Checksum

Answer Byte 1 :• 0x06 (ACK), if value was written• 0x15 (NACK), if command, address or checksum is invalid

Table 6.5.5.3-6: Command EEUPD

Command Name EEUPD- EEPROM update

Function Changes on the RAM data are stored to the EEPROM

Validity After activation of configuration state

Command Code Byte 1 : 0xA3

Following Bytes Byte 2 : 0x01 (constant)Byte 3 : 0xA5 (checksum)

Answer Byte 1 :• 0x06 (ACK), if update successful• 0x15 (NACK), if command or checksum is invalid

Table 6.5.5.3-7: Command READEE

Command Name READEE - read EEPROM content

Function Read EEPROM and store to RAM and registers


Command Code Byte 1 : 0xD3

Following Bytes Byte 2 : 0x00Byte 3 : 0xD4 (checksum)

Answer Byte 1 :• 0x06 (ACK), if reading has finished• 0x15 (NACK), if command, parameter or checksum invalid

Table 6.5.5.3-8: Command OPERATE

Command Name OPERATE - restart device

Function Restart device with current EEPROM configuration data


Command Code Byte 1 : 0xAA

Following Bytes Byte 2 : 0xAB (checksum)

Answer Byte 1 :• 0x06 (ACK), after having sent this byte the SSP enters operation state • 0x15 (NACK), if command or checksum invalid




Table 6.5.5.3-9: Command BIST

Command Name BIST- execute BIST

Function Execute the built-in self-tests


Command Code Byte 1 : 0xB3

Following Bytes Byte 2 : Select a test step:• 0x01 : ROM BIST• 0x02 : RAM BIST• 0x03 : EEPROM BIST• 0x04 : Arithmetic Unit BIST• 0x05 : n/aByte 3 : Checksum

Answer Byte 1 :• 0x06 (ACK), if selected test starts• 0x15 (NACK), if command, parameter or checksum invalidAfter the selected test is done, the corresponding DONE flag in BISTSTAT register and - in case of an error - the corresponding error flag in BISTSTAT register is set. Use the READ command on BISTSTAT to check the flags and determine the result:• DONE flag :• 0b : test not done• 1b : test has finished

• ERR flag :• 0b : no error detected• 1b : test failed

Table 6.5.5.3-10: Command ANAOUT

Command ANAOUT - activate analogue output

Function Activate analogue output1) 2)


Command Code Byte 1 : 0xBC

Following Bytes Byte 2 : high nibble (Bit[7:4]) selects analogue output:• 0000b : write directly to DAC register, then Byte2[3:0] = DACREG[11:8]• 0001b - 0111b : switch OUT to high ohmic• 1XXXb : route internal signals to DAC register :• Bit[6] :• 0b : Raw pressure data SRAW

• 1b : Corrected pressure data PCORR

• Bit[5] :• 0b : reserved• 1b : reserved

• Bit[4] :• 0b : select single signal correction• 1b : select continuous signal correction

Byte 3 :• if Byte2[7:4] = 0000b then low byte for DAC (DACREG[7:0] = Byte3),• else unused (don't care)Byte 4 : Checksum

Answer Byte 1 :• 0x06 (ACK), after having sent this byte the SSP activates the analogue output• 0x15 (NACK), if command, parameter or checksum invalid

1) In order to communicate via SIO after activation of this command, simply force the pin OUT to GND and VVS for each at least tRX,Hi-Z(SIO) and the pin OUT will return to hi-Z state.2) DAC Value depends on Limiter setting(LIMSENS.SENSUL and LIMSENS.SENSLL)




Table 6.5.5.3-11: Command GETSIG

Command Name GETSIG- read pressure or temperature value

Function Read pressure or temperature value according to selection, returned values are not limited by the internal limiter


Command Code Byte 1 : 0xC3

Following Bytes Byte 2,• Bit[0]• 0b : select corrected pressure1)

• 1b : select uncorrected pressure• Bit[1]• 0b : don't select temperature• 1b : select temperature (normalized if bit[0] = 0b or raw if bit[0] = 1b)

• Bit[7:2] : unused (don't care)Byte 3 : Checksum

Answer Byte 1 :• 0x06 (ACK), if answer is ready• 0x07 (BEL), if answer is ready and an enabled error is present• if received Byte2[1] = 0b: (without temperature) Byte 2 - 3 and checksum will be send• else received Byte2[1] = 1b: (with temperature) Byte 2 - 5 and checksum will be send

• 0x15 (NACK), if checksum is invalidByte 2 : High byte of pressureByte 3 : Low byte of pressureByte 4 : High byte of temperatureByte 5 : Low byte of temperatureFinal Byte : Checksum

1)Note: If a corrected pressure value is requested, the correction of the recent uncorrected pressure is performed first before it is sent out

Table 6.5.5.3-12: Command RESET

Command Name Reset

Function Reset the device without leaving recent operation mode


Command Code Byte 1 : 0xE2

Following Bytes Byte 2 : 0xE3 (checksum)

Answer A reset will be performed. No answer is sent.




6.6 DiagnosticsThis chapter summarizes the diagnostic functions of the SSP. If any diagnosis detects an error in Analogue Mode,the analogue output OUT changes into the pre-defined failure-band (Hi- or Lo-level). The diagnostic level of the fail-ure-band can be set by ENERR.ERRLEVEL.A detailed description of the diagnostic functions, their execution process and activation is found in the next sec-tions.

6.6.1 Supply DiagnosisThe E520.44 provides a supply diagnosis system in order to detect an under-/over voltage of main supply voltage VVS.If the supply voltage VVS is below VStooLO or larger than VStooHI the supply diagnosis error bit (ERRC.V5ERR) is set. In case this error bit is enabled the output is driven to the programmed failure band.Remark: below a supply-voltage of 3.8V a power-on-reset can be triggered at the output will become high ohmic.

The internal voltage monitor observes the internally regulated 3.3V supplies VDDA and VDDD, respectively. If the digital supply voltage is below VDDDTH,on a power-on-reset is generated. The logic is reset and the analogue output changes to high impedance (Hi-Z). If the analogue supply voltage is below the range of VDDA, the error flag ERRC.V3ERR is set to 1b .

The voltage monitoring function can be enabled by bits EN5ERR for VVS monitoring and EN3ERR for VDDA monit-oring in the ENERR registers, respectively.

6.6.2 Sensor DiagnosisThe chip provides surveillance monitoring for the sensor and its connections to the device. The following events can be detected:

• SERR0: open at bridge excitation EXHI, EXLO ;• SERR1: short of bridge excitation (between EXHI and EXLO) ;• SERR2: short of sensor outputs (INP, INN) to bridge excitation (EXHI,EXLO) ;• SERR3: open at sensor outputs INP, INN (with sensor pull-down enabled SENSOFF.PDSENS);• SERR4: short circuit between INP and INN (during Power-up only)

The check whether all bridge voltages are inside the specified range is done by use of voltage comparators as depicted in Figure 6.6.2-1.To detect an open circuit at positive or negative sensor inputs INP or INN (SERR3), the internal pull-down resistors need to be enabled (by setting bit .PDSENS in register SENSOFF_H).

To allow for short circuit detection between inputs INP and INN, an additional self test is implemented, which can operate during power-up phase only. During this test, current sources are activated to check for short circuit between INP and INN. The result of this self test will be shown in bit SERR4 of the ERRC registers.




EXHI

EXLO

Sensor Bridge

Enable Pull-downs

Internal (high-ohmic) pull-up resistors,to detect open at INN, INP

VIN,DIAG,LO

VIN,DIAG,HI

INP

INN

INP too high, short to EXHI,

INP too low, short to EXLOwith pull-down enabled: open INP detectable

INN too high, short to EXHI,

INN too low, short to EXLOwith pull-down enabled: open INN detectable

Bridge-EXLO missing

Bridge-EXHI missing

VEX,DIAG,short

Bridge short to EXLO

test current source to detect shorts INN, INP

Figure 6.6.2-1: Sensor Diagnosis

6.6.3 Output DiagnosisThe device E520.44 provides an over current diagnosis for the analog output:

• ENERR.ENCURRLIM =1b enables an overcurrent detection for the analogue output by setting the flag ERRC.-CURRLIM, whenever the current limit is exceeded at the output (IOUTsink,LIM,ana or IOUTsource,LIM,ana ).

When enabled, shorts to supply VS or ground at the analogue output can be detected by a comparator circuit.

In case the short circuit error flag is set(ERRC.CURRLIM=1b) the output will be driven to the failure band. The fail-ure band level of the analogue output can be selected by setting the register contents ENERR.ERRLEVEL appro-priately (see Figure 6.6.7.1-1). When the output was driven to the failure band, there would be no further way to detect if the error has disappeared. Therefore, the output will periodically change to normal operation (tOUTERR,PWD), to verify if an output short or overload error is persisting. A duty cycle is given by the drive time to failure band (tOU-

TERR,ON) vs. time in normal operation tOUTERR,OFF).

This analogue output diagnosis function is only available if the analogue output mode is selected (MODECON-F.OUTMODE = 0b). When the output is configured as SENT (MODECONF.OUTMODE = 1b) this diagnostic func-tion is disabled.

The device E520.44 provides an Analogue Output Diagnosis :• ENERR.ENOUTERR = 1b enables an check of the analog output stage and indicates errors by setting the flag

ERRC.OUTERR.

The block diagram is shown below (Figure 6.6.3-1). The analogue output voltage is compared to four different threshold levels. The outputs of these comparators are compared to the digital input of the output DAC. In this way,deviations between the analogue output voltage and the DAC-input data are detectable.




The analog output diagnosis is implemented to check for internal errors of the DAC, the DAC-reference circuit, and the output buffer stage. It can be used further to detect shorts of the output to VS or GND but those errors are bet-ter to be detected by the current limitation error.

In case an error (ERRC.OUTERR=1b ) occurs the output will be driven to the failure band. The failure band level of the analogue output can be selected by setting the register contents ENERR.ERRLEVEL appropriately (see Figure 6.6.7.1-1). When the output was driven to the failure band, there would be no further way to detect if the error has disappeared. Therefore, the output will periodically change to normal operation (tOUTERR,PWD), to verify if the error is persisting. A duty cycle is given by the drive time to failure band (tOUTERR,ON) vs. time in normal operation tOUTERR,OFF).This analogue output diagnosis function is only available if the analogue output mode is selected (MODECONF.OUTMODE = 0b). When the output is configured as SENT (MODECONF.OUTMODE = 1b) this dia-gnostic function is disabled.

BufferOUTOutput

DACDAC

output register

1/0

VS

Control logic

OutputCompareregister

CompareOutput VALID / INVALID

VOUT,REF4

VOUT,REF3

VOUT,REF2

VOUT,REF11/0

1/0

1/0

Figure 6.6.3-1: Analogue Output Diagnostic

6.6.4 Watchdog Monitor DiagnosisTo avoid accidental failures, e.g. provoked by transient disturbances, a watchdog monitor is implemented which observes:

• the correct logic control flow of the EEPROM write access,• the copy process from EEPROM to RAM,• the signal correction,• the execution of SIO commands and• all self tests, which are running continuously.

If the Watchdog monitor detects any inconsistency in the logic control flow the flag WDERR is set in the register ERRC and a system reset is generated. After reset the initialization is performed without the enabled built-in self-tests.




6.6.5 BIST (Built In Self Test)The device E520.44 is capable of performing various tests concerning memories (ROM, RAM, EEPROM), signal path (SP) and arithmetic unit (AU). These features can be selected with register ENERR (see Chapter 6.6.6, Dia-gnosis registers). The build-in self-tests (BISTs) are available for :

1. EEPROM BIST (see chapter 6.6.5.1)1.1 EEPROM data check1.2 EEPROM shadow data check

2. Signal path BIST (see ch. 6.6.5.2)3. ROM +RAM BIST (see ch. 6.6.5.3)4. Arithmetic Logical unit BIST (see ch. 6.6.5.4)

When enabled in ENERR register, the BISTs 1.1, 2, 3, 4 are available during power-up. Additionally, all BISTS can be triggered by command BIST and performed state independently. The results can be read from BISTSTAT register. These BISTs will take a certain amount of time (from tPWRUP,short to tPWRUP,long) which will lead to a longer power-up time. A detailed description of the different BIST functions is found in the next sections.

6.6.5.1 EEPROM BIST

This build-in-self-test provides integrity checks of the EEPROM content. To detect multi bit errors a 16 bit standard CRC over the EEPROM configuration data is performed. It can be enabled with bits ENERR.ENEEPBERR and/or ENERR.ENEECBERR (see below).

The result can be read from registers BISTSTAT or ERRC register. If a fault is detected by the diagnostic, it is indicated at the output.

• EEPROM data check (power-up only) In this mode, programmed data stored in EEPROM are checked during the power-up time. It checks data consistency through a 16 bit CRC-algorithm. This feature can be enabled or disabled with ENERR.ENEEPBERR. The result could be read from ERRC/BISTSTAT.EEPBERR and BIST-STAT.EEPBIST_DONE.

• EEPROM shadow data check (continuously) It checks data consistency of working registers, which are copied from EEPROM during power-up time also using a 16 bit CRC-algorithm. The feature can be selected with ENERR.ENEECBERR. The result could be read from ERRC/BISTSTAT.EECBERR and BISTSTAT.EECBIST_DONE.

6.6.5.2 Signal Path BIST

This built-in self test allows a holistic check of the complete signal processing chain.An appropriate voltage for a typical gain and offset setting is applied as a test stimulus at the PGA input. This input signal is amplified, digitally corrected and passed through the DAC to the analogue output.The resulting output voltage is fed back to the input of the 2nd ADC, which is the temperature ADC in normal opera-tion. The corresponding output of this temperature ADC, which are a digital equivalent of the test input voltage, are checked for correctness against an expected (digital) result.

This BIST covers the full signal path from input to the output and the correct operation of the temperature ADC. Thesignal path BIST will take a time tSPBIST. The completion of this BIST will be signalized by BCS (BIST Completion Sequence) at the output in analogue mode (see Figure 6.6.7.1-2).This feature can be selected with ENERR.ENSPBERR. The result could be read from ERRC/BISTSTAT.SPBERR and BISTSTAT.SPBIST_DONE.

The SP-BIST is available only if the analogue output mode is selected (MODECONF.OUTMODE = 0b). With SENT output mode selected (MODECONF.OUTMODE = 1b) this diagnosis is disabled.




6.6.5.3 ROM+RAM BIST

This BIST provides an integrity check of the ROM- and RAM content, respectively.A ROM build-in-self-test can be configured by ENERR.ENROPBERR to run only in power-up tpwrup sequence. The result can be read from ERRC/BISTSTAT.ROPBERR and BISTSTAT.ROPBIST_DONE.A RAM build-in-self-test can be configured by ENERR.ENRAPBERR to run only in power-up tpwrup sequence. The result can be read from ERRC/BISTSTAT.RAPBERR and BISTSTAT.RAPBIST_DONE.

6.6.5.4 Arithmetic Logical unit BIST

The SSP 520.44 also provides a built-in-self-test for the arithmetic unit. The test can be enabled to run continuouslyalso during operation performing a functional test of the arithmetic unit with ENERR.AUBERR. The result can be read from ERRC/BISTSTAT.AUBERR and BISTSTAT.AUBIST_DONE.An arithmetic unit BIST running after power-up only, can be enabled with ENERR.AUPBERR and the result is avail-able from ERRC/BISTSTAT.AUPBERR and BISTSTAT.AUPBIST_DONE respectively.

6.6.6 Diagnosis RegisterFor fault diagnosis purposes the following registers are available:

Table 6.6.6-1: Diagnosis Register Description

Register Address Description

BISTSTAT 0x6A - 0x6B BIST Status Register (READ / WRITE)

MASKERRC 0x6C - 0x6E Masked Error Code (READ only)

ERRC 0x6F - 0x71 Error Code Register (READ / WRITE)

ENERR 0x73 - 0x75 Enable Error Register (READ / WRITE)

The Enable Error Register (ENERR) is used to enable or disable error checks:Results of diagnostic functions are results are indicated at OUT (in analogue mode) with diagnostic level or Hi-Z or with a specific command answer when using the digital SIO. An enabled error can be read from registers Masked Error Code (MASKERRC) or Error Code (ERRC). The relation between register contents ENERR, ERRC, and MASKERRC is shown in Figure 6.6.6-1:

AND MASKERRC [23:0]ENERR [23:0]

ERRC [23:0]

Figure 6.6.6-1: Diagnosis Logic (simplified)

The following Table 6.6.6-2 summarizes information about error of various diagnosis options as coded in the ERRCregister, when enabled by setting of ENERR. It also describes the execution depending on operational state of the E520.44 and the output behaviour resulting from error conditions.

Furthermore, refer to chapter 6.6.7 for a description of error occurrence handling and their classification into 3 type classes used (see Table 6.6.7.1-1).




Table 6.6.6-2: Overview of diagnosis functions and registers

Bit 8) ERRC ENERR EXEC 1) STATE 2) Description Conditions OUT 3)

0 V5ERR EN5ERR C CS,DS VVS out of range error VVS < VVS,min, orVVS > VVS,max

--- 4)

0 V5ERR EN5ERR E, C OS VVS out of range error VVS < VVS,min, orVVS > VVS,max

Drive to failure band 5)

1 SAMPSAT

ENSAMPSAT

C CS, DS Sensor amplifier satura-tion

Input signal or common modevoltage too large, Repeat 3x in case of error occur-rence

--- 4)

1 SAMPSAT

ENSAMPSAT

E, C OS Sensor amplifier satura-tion

Input signal or common modevoltage too large, Repeat 3x in case of error occ

Drive to failure band

2 SADC-SAT

ENSADC-SAT

C CS, DS Sensor ADC out of range

Input signal Voltage too large

--- 4)

2 SADC-SAT

ENSADC-SAT

E, C OS Sensor ADC out of range

Input signal Voltage too large


3 TADC-SAT

ENTADC-SAT

C CS, DS Temperature ADC out of range

Input signal too large

--- 4)

3 TADC-SAT

ENTADC-SAT

E, C OS Temperature ADC out of range

Input signal too large


4 TNORMSAT

ENT-NORMSAT

C CS, DS Saturation after temper-ature normalization

Wrong coeffi-cients for tem-perature

--- 4)

4 TNORMSAT

ENT-NORMSAT

E, C OS Saturation after temper-ature normalization

Wrong coeffi-cients for tem-perature


5 CORRSAT

ENCORRSAT

E, C CS, DS Signal correction satur-ation

Wrong coeffi-cients for pres-sure

--- 4)

5 CORRSAT

ENCORRSAT

E, C OS Signal correction satur-ation

Wrong coeffi-cients for pres-sure


6 SERR4 ENSERR4 E, P --- Sensor error 4:Short between INN and INP

Repeat 3x in case of error occurrence

Drive persist-ently to failure band

7 SERR3 ENSERR3 C CS, DS Sensor error 3:Open at sensor outputs INP, INN

--- --- 4)

7 SERR3 ENSERR3 E, C OS Sensor error 3:Open at sensor outputs INP, INN







8 SERR2 ENSERR2 C CS, DS Sensor error 2:Short (INP, INN) to bridge excitation (EXHI,EXLO)


--- 4)

8 SERR2 ENSERR2 E, C OS Sensor error 2:Short (INP, INN) to bridge excitation (EXHI,EXLO)



9 SERR1 ENSERR1 C CS, DS sensor error 1:Short of bridge excita-tion between EXHI and EXLO


--- 4)

9 SERR1 ENSERR1 E, C OS sensor error 1:Short of bridge excita-tion between EXHI and EXLO



10 SERR0 ENSERR0 C CS, DS sensor error 0 :Open at bridge excita-tion EXHI, EXLO


--- 4)

10 SERR0 ENSERR0 E, C CS, OS, DS sensor error 0 :Open at bridge excita-tion EXHI, EXLO



11 OUT-ERR

ENOU-TERR

C CS, DS Error in DAC or output stage


--- 4)

11 OUT-ERR

ENOU-TERR

E, C OS Error in DAC or output stage


Drive periodic-ally pulse to failure band

12 CUR-RLIM

ENCUR-RLIM

C CS, DS Current limitation on OUT

Short at outputto VDDD or Vvs,repeat 3xin case of error occurrence

--- 4)

12 CUR-RLIM

ENCUR-RLIM

E, C OS Current limitation on OUT


Drive periodic-ally pulse to failure band

13 n/a n/a --- --- --- --- ---

14 WDERR n/a C, AE CS, OS, DS Watchdog monitor error --- Hi-Z, reset, restart without BIST

15 V3ERR EN3ERR C CS,DS VDDA out of range VDDA < VDDAmin, orVDDA > VDDAmax

--- 4)

15 V3ERR EN3ERR E, C OS VDDA out of range VDDA < VDDAmin, orVDDA > VDDAmax

Drive to failure band 5)





16 RAP-BERR

ENRAP-BERR

E, P --- Power-up RAM BIST error

Repeat BIST 3x in case of error occurr.


16 RAP-BERR

n/a T CS, DS Power-up RAM BIST error

--- --- 4)

17 EEP-BERR

ENEEP-BERR

E, P --- Power-up EEPROM BIST error



17 EEP-BERR

n/a T CS, DS Power-up EEPROM BIST error

--- --- 4)

18 ROP-BERR

ENROP-BERR

E, P --- Power-up ROM BIST error

Repeat BIST 3x


18 ROP-BERR

n/a T CS, DS Power-up ROM BIST error

--- --- 4)

19 AUP-BERR

ENAUP-BERR

E, P --- Power-up Arithmetic unit BIST error



19 AUP-BERR

n/a T CS, DS Power-up Arithmetic unit BIST error

--- --- 4)

20 SPBERR 7)

ENSP-BERR

E, P --- Power-up Signal path BIST error

Repeat BIST 3x in case of error occur-rence

BIST comple-tion sequence6)

, drive persist-ently to failure band

21 AUBERR

n/a T CS, DS Arithmetic unit BIST error

--- --- 4)

21 AUBERR

ENAU-BERR

E, C OS Arithmetic unit BIST error

--- Drive to failure band

22 EEC-BERR

n/a T CS, DS Continuous EEPROM shadow data BIST error

--- --- 4)

22 EEC-BERR

ENEEC-BERR

E, C OS Continuous EEPROM shadow data BIST error

--- Drive to failure band

23 n/a n/a --- --- - --- ---NOTES : 1) Execution:

• E : enabled by EEPROM bit• P : executable after Power-up (enabled by EEPROM bit)• T : triggered execution by SIO-commands (after entering in CS, DS within twindow)• C : execution continuously (enabled by EEPROM bit)• AE: always enabled2) Internal State (see Table 6.4-1)

• CS : configuration state (R/W)• OS : operation state• DS : diagnosis state (Read only)3) Error indicator on OUT-pin with analogue output mode selected (MODECONF.OUTMODE=0b), see Chapter 6.6.74) No error indication; only by read out of EERC/MASKERRC using the SIO interface5) Recommended to select Diagnostic Low Level (ENERR.ERRLEVEL=0b) with low Supply6) BIST completion sequence (BCS): Low-, High-level at OUT (see Chapter 6.6.7)7) Available only with analogue output mode selected (MODECONF.OUTMODE=0b)8) Bit position in error code registers ERRC_ or MASKERRC_(H/M/L)




Table 6.6.6-3: BIST Status Description (0x6A and 0x6B)

Bit BISTSTAT Register Description

0 RAPBIST_DONE Power-up RAM BIST done by setting to 1b

1 EEPBIST_DONE Power-up EEPROM BIST done by setting to 1b

2 ROPBIST_DONE Power-up ROM BIST done by setting to 1b

3 AUPBIST_DONE Power-up Arithmetic Unit BIST done by setting to 1b

4 SPBIST_DONE Power-up Signal Path BIST done by setting to 1b

5 AUBIST_DONE Continuous Arithmetic unit BIST done by setting to 1b

6 EECBIST_DONE Continuous EEPROM shadow data BIST done by setting to 1b

7 SERR4_DONE Power-up SERR4 done by setting to 1b

8 1) RAPBERR Power-up RAM BIST failed by setting to 1b

9 1) EEPBERR Power-up EEPROM BIST failed by setting to 1b

10 1) ROPBERR Power-up ROM BIST failed by setting to 1b

11 1) AUPBERR Power-up Arithmetic Unit BIST failed by setting to 1b

12 1) SPBERR Power-up Signal path BIST failed by setting to 1b

13 1) AUBERR Continuous Arithmetic unit BIST failed by setting to 1b

14 1) EECBERR Continuous EEPROM shadow data BIST failed by setting to 1b

15 1) SERR4 Power-up SERR4 failed by setting to 1b

1) see Table 6.6.6-2, only a share address of Table 6.6.6-10.

Table 6.6.6-4: Diagnosis Register


BISTSTAT_H 0x6A High byte BIST Status Register

BISTSTAT_L 0x6B Low byte BIST Status Register

MASKERRC_H 0x6C High byte of Masked Error Code Register

MASKERRC_M 0x6D Middle byte of Masked Error Code Register

MASKERRC_L 0x6E Low byte of Masked Error Code Register

ERRC_H 0x6F High byte of Error Code Register

ERRC_M 0x70 Middle byte of Error Code Register

ERRC_L 0x71 Low byte of Error Code Register

ENERR_H 0x73 High byte Enable Error Register

ENERR_M 0x74 Middle byte Enable Error Register

ENERR_L 0x75 Low byte Enable Error Register




Table 6.6.6-5: Register BISTSTAT_H (0x6A) High byte BIST Status Register

MSB LSB

Content SERR4 EECBERR AUBERR SPBERR AUPBERR ROPBERR EEPBERR RAPBERR

Reset value 0 0 0 0 0 0 0 0

Access R/W R/W R/W R/W R/W R/W R/W R/W

Bit Description SERR4 : Error in power-up SERR4 checkEECBERR : Error in continuous EEPROM shadow data BISTAUBERR : Error in continuous arithmetic unit BISTSPBERR : Error in power-up Signal path BISTAUPBERR : Error in power-up arithmetic unit BISTROPBERR : Error in power-up ROM BISTEEPBERR : Error in power-up EE BISTRAPBERR : Error in power-up RAM BIST

Table 6.6.6-6: Register BISTSTAT_L (0x6B) Low byte BIST Status Register

MSB LSB

Content SERR4_DONE

EECBIST_DONE

AUBIST_DONE

SPBIST_DONE

AUPBIST_DONE

ROPBIST_DONE

EEPBIST_DONE

RAPBIST_DONE

Reset value 0 0 0 0 0 0 0 0


Bit Description SERR4_DONE : Power-up SERR4 Check Status• 0b : in process• 1b : doneEECBIST_DONE : Continuous EEPROM shadow data BIST Check Status• 0b : in process• 1b : doneAUBIST_DONE : Continuous Arithmetic Unit BIST Check Status• 0b : in process• 1b : doneSPBIST_DONE : Power-up Signal path BIST Check Status• 0b : in process• 1b : doneAUPBIST_DONE : Power-up Arithmetic Unit BIST Check Status• 0b : in process• 1b : doneROPBIST_DONE : Power-up ROM BIST Check Status• 0b : in process• 1b : doneEEPBIST_DONE : Power-up EE BIST Check Status• 0b : in process• 1b : doneRAPBIST_DONE : Power-up RAM BIST Check Status• 0b : in process• 1b : done




Table 6.6.6-7: Register MASKERRC_H (0x6C) High byte of Masked Error Code Register

MSB LSB

Content MEEC-BERR

MAUBERR MSPBERR MAUP-BERR

MROP-BERR

MEEP-BERR

MRAP-BERR

Reset value 0 0 0 0 0 0 0 0

Access R R R R R R R R

Bit Description MEECBERR : EECBERR & ENEECBERRMAUBERR : AUBERR & ENAUBERRMSPBERR : SPBERR & ENSPBERRMAUPBERR : AUPBERR & ENAUPBERRMROPBERR : ROPBERR & ENROPBERRMEEPBERR : EEPBERR & ENEEPBERRMRAPBERR : RAPBERR & ENRAPBERR

Table 6.6.6-8: Register MASKERRC_M (0x6D) Middle byte of Masked Error Code Register

MSB LSB

Content MV3ERR MCUR-RLIM

MOUTERR MSERR0 MSERR1 MSERR2

Reset value 0 0 0 0 0 0 0 0


Bit Description MV3ERR : V3ERR & EN3ERRMCURRLIM : CURRLIM & ENCURRLIMMOUTERR : OUTERR & ENOUTERRMSERR0 : SERR0 & ENSERR0MSERR1 : SERR1 & ENSERR1MSERR2 : SERR2 & ENSERR2

Table 6.6.6-9: Register MASKERRC_L (0x6E) Low byte of Masked Error Code Register

MSB LSB

Content MSERR3 MSERR4 MCORRSAT

MTNORM-SAT

MTADC-SAT

MSADC-SAT

MSAMPSAT

MV5ERR

Reset value 0 0 0 0 0 0 0 0


Bit Description MSERR3 : SERR3 & ENSERR3MSERR4 : SERR4 & ENSERR4MCORRSAT : CORRSAT & ENCORRSATMTNORMSAT : TNORMSAT & ENTNORMSATMTADCSAT : TADCSAT & ENTADCSATMSADCSAT : SADCSAT & ENSADCSATMSAMPSAT : SAMPSAT & ENSAMPATMV5ERR : V5ERR & EN5ERR




Table 6.6.6-10: Register ERRC_H (0x6F) High byte of Error Code Register

MSB LSB

Content EECBERR AUBERR SPBERR AUPBERR ROPBERR EEPBERR RAPBERR

Reset value 0 0 0 0 0 0 0 0

Access R R/W R/W R/W R/W R/W R/W R/W

Bit Description EECBERR : Continuous EEPROM shadow data BIST errorAUBERR : Continuous Arithmetic unit BIST errorSPBERR : Power-up Signal Path BIST errorAUPBERR : Power-up Arithmetic unit errorROPBERR : Power-up ROM BIST errorEEPBERR : Power-up EEPROM BIST errorRAPBERR : Power-up RAM BIST error

Table 6.6.6-11: Register ERRC_M (0x70) Middle byte of Error Code Register

MSB LSB

Content V3ERR WDERR CURRLIM OUTERR SERR0 SERR1 SERR2

Reset value 0 0 0 0 0 0 0 0

Access R/W R R/W R/W R/W R/W R/W R/W

Bit Description V3ERR : VDDA out of rangeWDERR : Watchdog monitor errorCURRLIM : Current limitation on OUTOUTERR : analog output errorSERR0 : Open at bridge excitation between EXHI and EXLOSERR1 : Short between EXHI and EXLOSERR2 : Short between (INN, INP) and (EXHI, EXLO)

Table 6.6.6-12: Register ERRC_L (0x71) Low byte of Error Code Register

MSB LSB

Content SERR3 SERR4 CORRSAT TNORM-SAT

TADCSAT SADCSAT SAMPSAT V5ERR

Reset value 0 0 0 0 0 0 0 0


Bit Description SERR3 : Open sensor at INN, INPSERR4 : Short sensor between INN and INPCORRSAT : Saturation in signal correctionTNORMSAT : Saturation after temperature normalizationTADCSAT : Temperature ADC saturationSADCSAT : Sensor ADC saturationSAMPSAT : Sensor amplifier saturationV5ERR : VVS out of range error




Table 6.6.6-13: Register ENERR_H (0x73) High byte Enable Error Register

MSB LSB

Content ERR-LEVEL

ENEEC-BERR

ENAU-BERR

ENSP-BERR

ENAUP-BERR

ENROP-BERR

ENEEP-BERR

ENRAP-BERR

Reset value 0 0 0 0 0 0 0 0


Bit Description ERRLEVEL : Diagnostic Level selection of failure-band• 0b : 0 V• 1b : Vvs

ENEECBERR : Enable continuous EEPROM shadow data BISTENAUBERR : Enable Arithmetic Unit BISTENSPBERR : Enable power-up Signal path BISTENAUPBERR : Enable power-up Arithmetic Unit BISTENROPBERR : Enable power-up ROM BISTENEEPBERR : Enable power-up EEPROM BISTENRAPBERR : Enable power-up RAM BIST

Table 6.6.6-14: Register ENERR_M (0x74) Middle byte Enable Error Register

MSB LSB

Content EN3ERR ENCUR-RLIM

ENOU-TERR

ENSERR0 ENSERR1 ENSERR2

Reset value 0 0 0 0 0 0 0 0


Bit Description EN3ERR : Enable internal VDDA monitoringENCURRLIM : Enable current limitation detectionENOUTERR : Enable analog output error detectionENSERR0 : Enable open detection at bridge excitation between EXHI and EXLOENSERR1 : Enable short detection between EXHI and EXLOENSERR2 : Enable short detection ((INN, INP) to bridge excitation (EXHI,EXLO))

Table 6.6.6-15: Register ENERR_L (0x75) Low byte Enable Error Register

MSB LSB

Content ENSERR3 ENSERR4 ENCORRSAT

ENT-NORMSAT

ENTADC-SAT

ENSADC-SAT

ENSAMPSAT

EN5ERR

Reset value 0 0 0 0 0 0 0 0


Bit Description ENSERR3 : Enable open sensor output detection (EXHI, EXLO)NOTE: This diagnosis requires SENSOFF.PDSENS = 1b

ENSERR4 : Enable short sensor detection between INN and INPENCORRSAT : Enable CORRSAT (saturation in signal correction)ENTNORMSAT : Enable TNORMSAT (saturation in temperature normalization)ENTADCSAT : Enable TADCSAT (saturation in temperature ADC )ENSADCSAT : Enable SADCSAT (saturation in sensor ADC)ENSAMPSAT : Enable SAMPSAT (saturation in PGA)EN5ERR : Enable V5ERR (VVS out of range detection)




6.6.7 Error Indication6.6.7.1 Diagnostic Levels on OUT

Three different error indications are triggered through terminal OUT in analogue mode (MODECONF.OUTMODE=0b):

1. Continuously forcing the analogue output to a defined voltage level, a failure band (defined by the configura-tion bit ENERR.ERRLEVEL), i.e. close to the upper or lower supply rail, respectively. Driving to failure band is continued as long as the error persists. This error indication is mainly generated in diagnosis functions.

2. Periodically repeating signal with a fixed duty-cycle. This error indication is related to output over current dia-gnosis and output error diagnosis (ENERR.CURRLIM=1b, see ch. 6.6.3, ENERR.OUTERR=1b, see ch. 6.6.3). A duty cycle will be generated at OUT switching between failure band level (for tOUTERR,ON) and normal operation as shown in Figure 6.6.7.1-1 (with failure band level depending on bit ENERR.ERRLEVEL).

3. Persistently setting the analogue output to a defined voltage level, a failure band (defined by the configuration bit ENERR.ERRLEVEL). This error indication is used for the following error events:• Short circuit between INP and INN (enabled by bit ENERR.SERR4, see ch. 6.6.2 Sensor Diagnosis) during

power up BIST, only.• Signal Path BIST (enabled by bit ENERR.SPBERR, see ch. 6.6.5.2).

After the error flag is set, and also after leaving the tWINDOW time, OUT is driven to failure band persistently. Only after a new power-up sequence this state can be cleared (in case the error disappeared).

See Table 6.6.6-2 for a detailed description of diagnosis errors and their corresponding error level.

OUT

Low

High

tOUTERR,ON

tOUTERR,PWD

tOUTERR,OFF

ENERR.ERRLEVEL=0b

VOUTERR,VAL(n)

VOUTERR,VAL(n+1)

1 / fDAC

1 2 3 4 16 3331

Figure 6.6.7.1-1: Periodically repeating signal (ERRC.OUTERR=1b or ENERR.CURRLIM=1b, ERRLEVEL = 0b)

In analogue output mode, the device 520.44 has general 3 types of diagnosis handling (see Table 6.6.7.1-1) for error indication at pin OUT. After power-up, the completion of enabled Signal-path BIST, ENERR.ENSPBERR will be indicated at pin OUT as a BIST completion sequence (BCS) - a sequence of low and high level generated at theend of the BISTs.Figure 6.6.7.1-2 shows a typical BIST completion sequence generation after all enabled BIST are processed sequentially and without errors.




Error- Counter

high ohmic

tWINDOW

INIT

0

PBIST

OUT

BIST

A-Power-up-Start PBIST

BPBIST finish

Handling

0

SPBIST

Diagnosis

0 0

CSPBIST

DBCS

BIST Completion Sequence

Low

High

Others

0

E- Correction- other Tasks

No BIST error

tSPBIST

tBCS,LOW

tBCS,HIGH

Output valid

Figure 6.6.7.1-2: BIST completion sequence, BCS (all BIST are error-free)

Notes:• PBIST: All power-up BIST (ROMBIST, EEPROMBIST, ROMBIST, AUPBIST) enabled• Power-up Signal path BIST (SPBIST) is also enabled

Table 6.6.7.1-1: Error Signalizations on pin OUT (analogue output mode)

No Type Handling Level Error Indica-tion

1 Immediate • Diagnosis Flag : ERRC[0], ERRC[2:5], ERRC[15]• Drives immediately to failure band

Failure band continuously

2 Single repeat

• Diagnosis Flag : ERRC[14] = WDERR• OUT is driven to Hi-Z• Restarts through reset activation with new window-time twindow

• Restarts diagnostic without BIST

Hi-Z Hi-Z

3 Triple repeat

• Diagnosis Flag : ERRC[1], ERRC[6:10], ERRC[16:19], ERRC[21:22]

• Increments internal error counter• Restarts the latest diagnostic• Repeat the diagnostic and increment error counter if dia-

gnostic is still failed• If error counter reaches the limit of 3 :• if it occurs within twindow, the error counter and subsequent

power-up BIST are hold, and wait until twindow expired.• Set OUT to failure band.

• If the flag is not set or diagnostic is passed (error counter below the limit), set pin OUT to normal operation.

Failure band continuously




No Type Handling Level Error Indica-tion

Triple repeat

• Diagnosis Flag : ERRC[6](SERR4), ERRC[20](SPBERR)• Increments internal error counter• Restarts the latest diagnostic• Repeat the diagnostic and increment error counter if dia-


power-up BIST are hold, and wait until twindow expired.• In case of Error is encountered during Signal-path BIST

(ENERR.ENSPBERR):• Low level generation of BIST Completion Sequence

(BCS) for tBCS,LOW

• High level generation of BIST Completion Sequence (BCS) for tBCS,HIGH

• Set OUT to failure band.• If the flag is not set or diagnostic is passed (error counter

below the limit), set pin OUT to normal operation. To indicate the end of the signal-path BIST the BIST completion sequence (BCS) shall be generated.

Failure band persistently

Triple repeat

• Diagnosis Flag : ERRC[11](OUTERR), ERRC[12](CURRLIM)• Increments internal error counter• Restarts the latest diagnostic• Repeat the diagnostic and increment error counter if dia-


power-up BIST are hold, and wait until twindow expired• Set OUT to failure band.

• If the flag is not set or diagnostic is passed (error counter below the limit), set pin OUT to normal operation.

Failure band periodically

In the following diagrams (Figure 6.6.7.1-3 and Figure 6.6.7.1-4) two exemplary cases of error handling (error-type No. 3: triple repeat) are depicted during:1. Power-up BIST: Started during twindow (see Figure 6.6.7.1-3), and2. Continuous BIST: Enabled during normal operation (see Figure 6.6.7.1-4).




Error- Counter

high ohmic

tWINDOW

RAMBISTINIT

RAPBERR

RAMBISTINIT

1 20

OUT

BIST

A-Power-up-Start RAMBIST

B - Err detected- Incr. Counter- Restart

B B - Err detected- Counter = 3- Hold

- Wait till twindow

Handling

3

Diagnosis

Error

Low

High

Failure band

C - SPBIST hold- No BIST Completion Sequence(BCS)- drives to failure band

SPBIST

Figure 6.6.7.1-3: Error handling during power-up BIST (ex. power-up RAM BIST Error)

Notes:• PBIST: All power-up BISTs (ROMBIST, EEPROMBIST, ROMBIST, AUPBIST) enabled• Power-up Signal Path BIST (SPBIST) also enabled• Failure band level selected as Lo (ENERR.ERRLEVEL = 0b)

Error- Counter

high ohmic

tWINDOW

INIT

0

PBIST

OUT

BIST

A-Power-up-Start PBIST

G - Err detected- Counter = 3- drives to Failure band

BPBISTfinishHandling

0

SPBIST

Diagnosis

0 0

EECBIST

0

EECBERR

1

F - Err detected- Incr. Counter- Restart

CSPBIST

D BCS

EECBIST

3

F

2

Error

FEECBIST

Low

High

CORR

0

1 / fDAC

E- Correction- other Tasks

Failure band

BCS = BIST Completion Sequence

Figure 6.6.7.1-4: Error handling during continuous BIST (ex. Continuous EEPROM shadow data BIST Error)

Notes:• PBIST: All power-up BIST (ROMBIST, EEPROMBIST, ROMBIST, AUPBIST) enabled• Power-up Signal path BIST (SPBIST) also enabled• Failure band level selected as Lo (ENERR.ERRLEVEL = 0b)




7 Package Information

7.1 Package QFN20L5The E520.44 is available in a Pb free, RoHs compliant, QFN20L5 plastic package according to JEDEC MO-220K, variant VHHC-2. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak temperature of 260°C.Note: Thermal resistance junction to ambient Rth,ja is 35 °C/W (typ), based on JEDEC standards JESD 51-5, -7.

Figure 7.1-1: Package Outline

Table 7.1-1: Package Characteristics

Description Symbol mm inch

min typ max min typ max

Package height A 0.80 0.90 1.00 0.031 0.035 0.039

Stand off A1 0.00 0.02 0.05 0.000 0.00079 0.002

Thickness of terminal leads, including leadfinish

A3 -- 0.20REF

-- -- 0.0079REF

--

Width of terminal leads b 0.25 0.30 0.35 0.010 0.012 0.014

Package length / width D / E -- 5.00BSC

-- -- 0.197BSC

--

Length /width of exposed pad D2 / E2 3.50 3.65 3.80 0.138 0.144 0.150

Lead pitch e -- 0.65BSC

-- -- 0.026BSC

--

Length of terminal for soldering to sub-strate

L 0.35 0.40 0.45 0.014 0.016 0.018

Number of terminal positions N 20 20Note: Dimensions in mm are true. Dimensions in inch are just for information; these may contain rounding errors.




7.2 Package QFN20L4The E520.44 is available in a Pb free, RoHs compliant, QFN20L4 plastic package according to JEDEC MO-220K, variant VGGD-5. The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020 with a soldering peak temperature of 260°C.Note: Thermal resistance junction to ambient Rth,ja is 45 °C/W (typ), based on JEDEC standards JESD 51-5, -7.

Figure 7.2-1: Package Outline

Table 7.2-1: Package Characteristics

Description Symbol mm inch

min typ max min typ max

Package height A 0.80 0.90 1.00 0.031 0.035 0.039

Stand off A1 0.00 0.02 0.05 0.000 0.00079 0.002

Thickness of terminal leads, including leadfinish

A3 -- 0.20REF

-- -- 0.0079REF

--

Width of terminal leads b 0.18 0.25 0.30 0.0071 0.0098 0.012

Package length / width D / E -- 4.00BSC

-- -- 0.157BSC

--

Length /width of exposed pad D2 / E2 2.50 2.65 2.80 0.098 0.104 0.110

Lead pitch e -- 0.50BSC

-- -- 0.020BSC

--

Length of terminal for soldering to sub-strate

L 0.35 0.40 0.45 0.013 0.016 0.018

Number of terminal positions N 20 20Note: Dimensions in mm are true. Dimensions in inch are just for information; these may contain rounding errors.




7.3 Bare diceDice are delivered as wafers on foil. Sample volumes may be packed in waffle packs.

Wafer thickness after grinding: 400 μm ± 30 μm

Note: Contact factory for detail information on pad-layout E520.44.




8 Typical ApplicationsThe E520.44 can be used either with an analogue voltage output or a digital SENT data interface:• A global circuit diagram of the SSP used with analogue output is depicted in 8.1 and the recommended compon-

ent parameters are given in the table below. Please note, the analogue voltage output is ratiometric to the supplyVS of the E520.44. Therefore the implementation of serial resistance in the supply (or ground) line needs to be considered carefully to avoid unwanted voltage drop and related scaling deviations.

• A recommended circuit diagram of the SENT data output is shown in .

8.1 Typical Application Circuit E520.44 - Analogue Output

E52

0.44

.

VS

.

.

VSSA

VSSD

VDDA

VDDD

EXHI

TSEN

INP

INN

EXLO

OUTSensorBridge

Input Channel

Analog In

VSS

VS5 regulated

Sensor module Control Unit

*) for improved EMC

.

..

.

.

CVDDA

CVS

CINP*)Cout1

CINN*)

CVDDD

RoutCout2*)

Rof1*)

Figure 8.1-1: Application Circuit E520.44 - Analogue Output Configuration

Table 8.1-1: Recommended passive components values

Description Condition Symbol Min Typ Max Unit

Blocking capacitor for supplyline

10%, 50V, ESR < 0.2Ω @ 1MHz

CVS 47 100 nF

Blocking capacitor for ana-logue supply (regulator out)

10%, 50V, ESR < 0.2Ω @ 1MHz

CVDDA 47 100 470 nF

Blocking capacitor for digital supply (regulator out)

10%, 50V, ESR < 0.2Ω @ 1MHz

CVDDD 47 100 470 nF

Filter capacitor for EMC improvement

10%, 50V, ESR < 0.2Ω @ 1MHz

COUT1 10 22 47 nF

PI-filter for improved EMC performance 1)

depending on PCB layout

COUT2 1 10 22 nF

PI-filter for improved EMC performance 1)

depending on PCB layout

ROF1 1 - 10 Ω

Input impedance at ana-logue signal line

ROUT 2.2 kΩ





Filter capacitor for EMC improvement 2)

depending on rout-ing length of bridge to inputs

CINP 10 - 1000 pF

Filter capacitor for EMC improvement 2)

depending on rout-ing length of bridge to inputs

CINN 10 - 1000 pF

1) To further improve the EMC suceptibility at the analogue output a PI-filter (COUT1, COUT2, ROF1) at OUT can be advantageous over a single capacitor at OUT. The total capacitance should not exceed COUT1,max.

2) Wiring of the resistive sensor bridge should be as short as possible and symmetrical to avoid coupling of disturb-ance at the low level input. Depending on board layout, these unwanted coupling can be suppressed by adding small capacitors to INN and INP, respectively.

8.2 Application Circuit of SENT interface

E52

0.44

VS

OUT

VSSA

VSSD

CPU

Supply

Control unit

TimerInput

RF

*)

CIN

RPULLUP

C01

R01

C02

RTAU1

CTAU1

V(SENT)

CVS

CF

*) RV

*)

Sensor module

*) Optional: 2nd stage filter + divider

Figure 8.2-1: Typical Application Circuit SENT transmitter & receiver

Table 8.2-1: Recommended passive components values


Pull up resistor on SENT receiver

RPULLUP 9.5 55 kΩ

SENT receiver input filter resistor (1st stage) 1)

RTAU1 448 560 672 Ω

SENT receiver input filter capacitor (1st stage) 1)

CTAU1 1.54 2.2 2.86 nF

Time constant of SENT receiver input lowpass filter (1st stage)

TAU1 0.74 1.73 µs

Time constant of SENT receiver filter resistor (2nd stage, determined by RF, RV,CF) 2)

TAU2 0.6 1.4 µs

SENT receiver filter resistor (2nd stage)

RF 4 kΩ





Parasitic input capacitor of receiver 3)

CIN 100 pF

EMC filter resistor at SENT transmitter 4)

R01 198 220 242 Ω

EMC filter capacitor at SENT transmitter 4)

C01 1.54 2.2 2.86 nF

EMC filter capacitor at SENT transmitter 4)

C02 1.54 2.2 2.86 nF

1) The device tolerance shall meet the overall tolerance of the time constant TAU12) RF, RV creating an (optional) level converter from 5V output to 3.3V input, e.g. RF = 6.8 kΩ, RV = 12 kΩ (CF = 220 pF for low pass filter)3) A maximum parasitic wiring capacitance of 500 pF may be added.4) Values apply for a clock tick tTICK = 3 µs. For larger tTICK the resulting time constant may be scaled proportionally




9 General

9.1 WARNING - Life Support Applications PolicyELMOS Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless,semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing ELMOS Semiconductor AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of an ELMOS Semiconductor AG Product could cause loss of human life, body injury or damage to property. In development your designs, please ensure that ELMOS Semiconductor AG products are used within specified operating ranges as set forth in the most recent product specifications.

9.2 General DisclaimerInformation furnished by ELMOS Semiconductor AG is believed to be accurate and reliable. However, no respons-ibility is assumed by ELMOS Semiconductor AG for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of ELMOS Semiconductor AG. ELMOS Semiconductor AG reserves the right to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufactur-ability .

9.3 Application DisclaimerCircuit diagrams may contain components not manufactured by ELMOS Semiconductor AG, which are included as means of illustrating typical applications. Consequently, complete information sufficient for construction purposes isnot necessarily given. The information in the application examples has been carefully checked and is believed to beentirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of ELMOS Semiconductor AG or others.




10 Contact Info

Table 10-1: Contact Information

HeadquartersELMOS Semiconductor AGHeinrich-Hertz-Str. 1,D-44227 Dortmund (Germany)

+49 231 7549100 [email protected]

www.elmos.com

Sales and Application Support Office North AmericaELMOS NA. Inc.32255 Northwestern Highway, Suite 220,Farmington Hills, MI 48334 (USA)

+1 2488653200 [email protected]

Sales and Application Support Office Korea and JapanELMOS Korea LtdB-1007, U-Space 2, #670 Daewangpangyo-ro,Sampyoung-dong, Bundang-gu, Seongnam-si,Gyeonggi-do, 463-400 Seoul (Korea)


Sales and Application Support Office ChinaElmos Semiconductor Technology (Shanghai) Co., Ltd.Unit 16B, 16F Zhao Feng World Trade Building,No. 369 Jiang Su Road, Chang Ning District,Shanghai, PR China, 200050

+86 216 2100908 [email protected]

Sales and Application Support Office SingaporeElmos Singapore Pte. Ltd.3A International Business Park, #09-13 ICON@IBP,Singapore 609935





11 Contents

Table of ContentFeatures...................................................................................................................................................................... 1Applications................................................................................................................................................................. 1General Description.................................................................................................................................................... 1Ordering Information................................................................................................................................................... 1Typical Operating Circuit - Analogue Output Mode.....................................................................................................1Functional Diagram..................................................................................................................................................... 2Pin Configuration........................................................................................................................................................ 2Pin Description............................................................................................................................................................ 31 Absolute Maximum Ratings..................................................................................................................................... 42 ESD......................................................................................................................................................................... 43 Recommended Operating Conditions...................................................................................................................... 54 Electrical Characteristics.......................................................................................................................................... 6

4.1 Power Supply................................................................................................................................................... 64.2 Oscillator.......................................................................................................................................................... 64.3 Modes of Operation......................................................................................................................................... 64.4 Signal Path....................................................................................................................................................... 6

4.4.1 Sensor Excitation EXHI............................................................................................................................ 64.4.2 Sensor Path............................................................................................................................................. 7

4.4.2.1 Sensor Amplifier Section.................................................................................................................. 74.4.2.1.1 Sensor Offset Compensation...................................................................................................74.4.2.1.2 Programmable Gain Amplifier (PGA).......................................................................................7

4.4.2.2 ΔΣ-Modulator for Sensor Signal Chain............................................................................................74.4.3 Temperature Path.................................................................................................................................... 74.4.4 Output Stage............................................................................................................................................ 8

4.4.4.1 Analogue Voltage Mode................................................................................................................... 84.4.4.1.1 12-bit Output DAC................................................................................................................... 8

4.4.4.2 SENT Mode..................................................................................................................................... 94.4.4.2.1 SENT Physical Interface..........................................................................................................94.4.4.2.2 SENT Protocol......................................................................................................................... 9

4.4.4.3 SIO Mode (Serial Input Output) .....................................................................................................104.5 Diagnostics.................................................................................................................................................... 10

4.5.1 Supply Diagnosis................................................................................................................................... 104.5.2 Sensor Diagnosis................................................................................................................................... 104.5.3 Output Diagnosis................................................................................................................................... 104.5.4 BIST (Built In Self Test)......................................................................................................................... 11

4.6 EEPROM Delivery State................................................................................................................................ 115 Register Table........................................................................................................................................................ 136 Functional Description .......................................................................................................................................... 15

6.1 Overview........................................................................................................................................................ 156.2 Power Supply................................................................................................................................................. 156.3 Oscillator........................................................................................................................................................ 166.4 Modes of Operation....................................................................................................................................... 166.5 Signal Path..................................................................................................................................................... 19

6.5.1 Sensor Excitation EXHI..........................................................................................................................196.5.2 Sensor Path........................................................................................................................................... 19

6.5.2.1 Sensor Amplifier Section................................................................................................................216.5.2.1.1 Sensor Offset Compensation.................................................................................................216.5.2.1.2 Programmable Gain Amplifier (PGA).....................................................................................23

6.5.2.2 ΔΣ-Modulator for Sensor Signal Chain..........................................................................................246.5.2.3 Digital Low-pass Filter.................................................................................................................... 24

6.5.3 Sensor Signal Correction....................................................................................................................... 256.5.4 Temperature Path.................................................................................................................................. 32




6.5.5 Output Stage.......................................................................................................................................... 336.5.5.1 Analogue Voltage Mode.................................................................................................................33

6.5.5.1.1 Limiter.................................................................................................................................... 336.5.5.1.2 12-bit Output DAC.................................................................................................................35

6.5.5.2 SENT Mode................................................................................................................................... 366.5.5.2.1 SENT Physical Interface........................................................................................................366.5.5.2.2 SENT Protocol....................................................................................................................... 36

6.5.5.3 SIO Mode (Serial Input Output) .....................................................................................................476.6 Diagnostics.................................................................................................................................................... 53

6.6.1 Supply Diagnosis................................................................................................................................... 536.6.2 Sensor Diagnosis................................................................................................................................... 536.6.3 Output Diagnosis................................................................................................................................... 546.6.4 Watchdog Monitor Diagnosis.................................................................................................................556.6.5 BIST (Built In Self Test)......................................................................................................................... 56

6.6.5.1 EEPROM BIST.............................................................................................................................. 566.6.5.2 Signal Path BIST............................................................................................................................ 566.6.5.3 ROM+RAM BIST........................................................................................................................... 576.6.5.4 Arithmetic Logical unit BIST...........................................................................................................57

6.6.6 Diagnosis Register................................................................................................................................. 576.6.7 Error Indication....................................................................................................................................... 66

6.6.7.1 Diagnostic Levels on OUT.............................................................................................................667 Package Information.............................................................................................................................................. 70

7.1 Package QFN20L5........................................................................................................................................ 707.2 Package QFN20L4........................................................................................................................................ 717.3 Bare dice........................................................................................................................................................ 72

8 Typical Applications............................................................................................................................................... 738.1 Typical Application Circuit E520.44 - Analogue Output..................................................................................738.2 Application Circuit of SENT interface.............................................................................................................74

9 General.................................................................................................................................................................. 769.1 WARNING - Life Support Applications Policy................................................................................................769.2 General Disclaimer........................................................................................................................................ 769.3 Application Disclaimer.................................................................................................................................... 76

10 Contact Info.......................................................................................................................................................... 7711 Contents............................................................................................................................................................... 78



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