real world analog solutions for your processor applications · real world analog solutions for your...

Real World Analog Solutions for Your Processor Applications

Bonnie BakerSenior Applications Engineer, [email protected]

ADC: Delta-Sigma, SAR vs. Pipeline ADCs –When and Where to Use Them

Agenda • What Are the Signal Frequencies

– Analog classes of applications– Frequency ranges of ADCs

• Nuts and Bolts of Delta-Sigma Converters– ΔΣ converter core and auxiliary ΔΣ functions– Applications for the ΔΣ converter

• The SAR ADC– Input stage dynamics – Applications for the SAR converter

• The High-speed Pipeline Topology– Driving the capacitive input stage– Applications for the pipeline converter

• Conclusion

Real World vs. Bandwidth

Bandwidth (Hz)

Noi

se-F

ree

Res

olut

ion

(bits

)

1 10 100 1k

0

5

10

15

20

25

10k 100k 1M

Temperature

Pressure

FlowLevel

Displacement/Proximity

Photo Sensing

10M 100M

Imaging/Test & Measurement

1G

ADC Architectures• There are many different ADC architectures

– Successive approximation (SAR)– Sigma delta (ΣΔ)– Slope or dual slope– Pipeline– Flash ... as in quick, not memory

• Delta-sigma converters determine the digital world by:– Oversampling– Applying digital filtering

• SARs determine the digital world by:– Sampling the input signal – Using an iterative process

• Pipeline converters determine the digital world by:– Undersampling– With sample/gain algorithm topology– Multiple stages/larger cycle-latency

ΔΣ − Delta SigmaOr Sigma Delta(Oversampling)

SAR Successive Approximation(Nyquist)

Conversion Rate 1K10010 10K 100K 1M 10M 100M

24

20

16

12

8

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er R

esol

utio

n (b

its)

TI ADC TechnologiesAdvantagesAdvantages

• High resolution• High stability

(averages and filters out noise)• Low power• Low cost

DisadvantagesDisadvantages• Cycle-latency• Low speed

Leadership

Leadership!

Leadership

Leadership

Pipeline(Undersampling)

SPS




24

20

16

12

8

Con

vert

er R

esol

utio

n (b

its)


• Zero-cycle latency • Low latency-time• High accuracy• Typically low power• Easy to use

DisadvantagesDisadvantages• Max sample rates 2-5 MHzLeadership

Leadership!

Leadership

Leadership


SPS




24

20

16

12

8

Con

vert

er R

esol

utio

n (b

its)


• Higher speeds• Higher bandwidth

DisadvantagesDisadvantages• Lower resolution• Pipeline delay/data

latency• More powerLeadership

Leadership!

Leadership

Leadership


SPS

OPAMPOP

AMPMUXMUX FILTERFILTER A/DA/D

μC orμP

μC orμP

D/AD/APOWERAMP

POWERAMP

REFREF

Where to Find Low Freq ADCs

Anti-alias FilterBand-pass FilterProgrammable Gain AmpInstrumentation AmpA/D Converter Driver

Sensor InterfaceVoltage Reference SourceBufferGainDifference AmplifierInstrumentation AmplifierFilterLevel Shift

Voltage Reference Source

Actuator DriverLine Driver4-20mA Driver

Voltage Reference SourceDDS Synthesis

Valve

OPAMPOP

AMP FILTERFILTER A/DA/D

μ Cor μ P

μ Cor μ P

REFREF

Where to Find High Freq ADCs

Anti-alias FilterBand-pass FilterProgrammable Gain AmpA/D Converter Driver

BufferVGALNADifference AmplifierLevel Shift







• Conclusion

Nuts and Bolts of ΔΣ ADCs

• The system versus ΔΣ (delta-sigma)• ΔΣ analog-to-digital converter core

– Programmable gain amplifier (PGA)– Analog modulator– Digital filter– Decimation filter

• Other features and options• Typical applications

ΔΣAnalog to Digital Converter

Applications for ΔΣ Converters• Signal Level: System Clock Range ~ 0.5 to 40 MHz

– Has an internal digital low-pass filter• Uses an integrator

– Accurate near DC– High resolution: Up to 24 bits

• Audio: System Clock Range ~ 20 to 40 MHz– Has an internal digital low-pass filter– Optimized noise performance– Optimized filter in audio frequency for flatness

• High Speed– Has an internal digital band-pass filter

• Uses a band-pass topology instead of integrator

OPAMPOP


μ Cor

μ P

μ Cor

μ P

D/AD/APOWERAMP

POWERAMP

REFREF

The ΔΣ ADC System






Valve

Decimation Filter

Delta-Sigma ADC Core

Input

Output

FIR Filter(Finite Impulse Response)

1-bit DataStream

OutputData

Digital Low-passFilter

AnalogInputs

Delta-SigmaModulatorPGA

Digital Output

Digital Out+-Analog Input

+-

1ST Order Modulator

Decimation Filter

Programmable Gain Amp

Input

Output


1-bit DataStream

OutputData


AnalogInputs


Digital Output


+-

1ST Order Modulator

Chopper-Stabilized

Programmable Gain Amplifier (PGA)

Decimation Filter

Outputdata

Digital Low-pass

Filter

AnalogInputs


+

−

RG

+

−

+

−

R2

R1

R2

R1RF

RF

VIN+

VIN−

VOUT

VREF

OR

Decimation Filter

Input

Output


1-bit DataStream

OutputData


AnalogInputs


Digital Output


+-

1ST Order Modulator


Signal input, X1 X2 X3 X4

X5

DifferenceAmp

IntegratorComparator(1-bit ADC)

1-bit DAC

To DigitalFilter

+- +

-

VMax

X1

X2

X3

X5

Vmax

0V+Vmax

-Vmax

Latc

h

X4

+Vmax

-Vmax

1

0Vmax

0V

ΔΣ ModulatorTime Domain

ΔΣ ModulatorFrequency Domain

Input Signal

Frequencyk FS / 2 k FS

Pow

er

• The integrator serves as a high-pass filter to the noise.

• The result is noise shaping.

X(s)QuantizationNoise, N(s)

Integrator ,H(s)= 1/s Y(s)

Decimation Filter


Input

Output


1-bit DataStream

OutputData


AnalogInputs


Digital Output


+-

1ST Order Modulator

ΔΣ ModulatorFrequency Domain

Input Signal

Digital filter removes HF noise.

Digital filter response

Frequencyk FS / 2 k FS

Pow

er

• The integrator serves as a high-pass filter to the noise.

• The result is noise shaping.

VIN

QuantizationNoise, Q(n)

Integrator ,H(f)

Digital Filter

Digital Filter Options• FIR• Sinc• IIR• Averaging

Input

Output

Sinc4

Digital Filter Response(ADS1232)

Decimation Filter

OutputData

Digital Low-pass

Filter

AnalogInputs


Decimation Filter

Decimation Filter

Digital OutputOutput

Data

Digital Low-pass

Filter

AnalogInputs


Other Analog Features and OptionsAnalog

• Features– Internal voltage or current reference(s) – AC excitation capable– DAC for TARE offset adjust– Transducer burn-out sensor

• Input Interface– Differential and/or multichannel Inputs– Buffer input– Negative input

Other Digital Features and OptionsDigital

• Features– Single-cycle conversion (zero-cycle latency)– Programmable digital filter– Calibration: Offset, gain, self, system– Sleep mode, BOR, memory, digital latches

• Interface– Slave/master– Clock polarity– Daisy chain

Zero-Latency in MUX ApplicationsADS1258

16-ChannelDelta-SigmaConverter

Load Cell

Pressure Sensor

10mΩ

Thermistor

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN15

AIN14

GPIO(7:0)

24-bitADC

DigitalFilter

Oscillator

SPIInterface

Control

CS

DRDY

SCLK

DIN

DOUTSTART

RESET

PWDN

Zero Cycle Latency: ADS1258

Zero cycle latency =• Zero latency• Single cycle conversion• Single cycle settling• No latency

Analog IN

Data OUT

Single CycleConversion

0-cycle latency

DataInvalid

N+0 N+1 N+2 N+3N-1

N+1 N+2N+3

N+00-cycle latency

0-cycle latency

“Hidden Conversions”

MSC12xxADS1216/7/8

ADS1224ADS1226

ADS1232ADS1234

ADS1240ADS1241

ADS1242ADS1243

ADS1256ADS1258

XX

XX

XX

XX

XX

XX

0-CYCLE LATENCY

(1st digital output)

1-CYCLE LATENCY

(2nd digital output)

2-CYCLE LATENCY

(3rd digital output)

3-CYCLE LATENCY

(4th digital output)

MULTIPLEXED24-bit DELTA-SIGMA ADCS

fully settled after MUX switching(optional mode

of operation)

4-CYCLE LATENCY

(5th digital output)

(X)(X)

(X)(X)

(X)(X)

(X)(X)

TI Del-sig Cycle latency






• Conclusion

• Most serial ADCs are SARs or Del-Sigs.• SARs are best for general-purpose apps.

– Data loggers – Temp sensors – Bridge sensors – General purpose

• In the market SARs:– Can be 8 to 18 bits of resolution– Speed range: >10 ksps to < 5 Msps

• SARs found as – Standalone– Peripheral in microcontrollers, processors

The SAR ADC

SARAnalog-to-Digital Converter

OPAMPOP


μ Cμ C

D/AD/APOWERAMP

POWERAMP

REFREF

The SAR ADC System






Valve

VS

16C 2C C C

VREF

1/2 VREF

SC+

_

SAR

Control Logic

RIN(50 Ω)

Shift Register

VSS

Cap array is both the sample cap and a DAC.

S1

SAR Converter: Block Diagram

SAR Conversion Concept

Analog InputVIN

FS

0

1/4FS

1/2FS

3/4FS

TEST MSB

TEST MSB -1

TEST LSB

TEST MSB -2

Bit = 1

Bit = 0Bit = 1 Bit = 0

Digital Output Code = 1010ADC OutputTime

ADC Input Impedance

• Input internal impedance is relatively low.• A high-impedance source increases sample cap

charging time.• Rise time of voltage on

CSW ~ (RS + RSAMP) * CSW

RSW = 50Ω

CSAMP = 40pF

Analog Input

Sample Cap

MUX Resistance

Leakage Current

VCC

VSS

RS DESD

DESD

Sample Cap Charging Time

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CS

CLK

DOUT

VCAP

SamplePeriod

910 8 7 6 5 4 3 2 1 011DD D D D D D D D D DD

Final Voltage on CSAMPLE

Desired Voltage on CSAMPLE

+

-

+5V

RFRG

RFRG

SAR ADC

+5V

RIN

CIN

C2

IN+

IN-

R3

R2

REFIN

REFOUT

+2.5V

U1

U2VINVOP

Driving SAR Converters

OPA350

ADS8361

Load Cell Application2nd Order, 10Hz,

Butterworth,Low-Pass Filter

LCL-816G

+

-

RL1 RL2

RL1RL2

VREF1

INA326

+

-

OPA333

VDD = 5V

ADS7841

CS

SHDN

DINDOUTMODEBUSY

CH0CH1

CH2

CH3DCLK

VREF1 = 4.096V

VREF2= 2.048V

Touch-screen Controller






• Conclusion

High Speed: Pipeline Topology• Pipeline converters fit high-speed applications

(5 MHz to 100+MHz). • Applications where you typically find pipeline

converters are:– Test and measurement instrumentation– Medical imaging– Radar systems– Data acquisition

System

ADCDigital

Processing,DDC

DSPAnalogFront-endDiff/SE

Signal ConditioningBand-pass FilteringGain to Match FSR of A/DSE to Diff ConversionDC-level Shifting

Conversion DigitizationMixing (alias)

Digital ProcessingFrequency TranslationDecimationProcessing Gain (SNR)

DSP

Analog Digital

What’s the Application/EE ?Time Domain• Imaging (CCD)

– Camcorders– Digital cameras– Scanners– RGB/comp. video– Test instrumentation– Medical

• Important Specs– SNR– Slew-rate/ tset– DNL– DC-accuracy/drift

Frequency Domain• Communications

– Set-top boxes– Cable modems– Base stations– IF digitizers– GPS– Frequency synthesizers

• Important Specs– SFDR– ENOB– Analog input bandwith– Jitter

ADC Interface SolutionsPrinciple Configuration Choices

Single-Ended Input (SE) Differential Input (DE)

ADCADC

Input+ fs

Vcm

- fs

Vcm

IN

IN

IN

IN

+ fs/2Vcm-fs/2

+ fs/2Vcm-fs/2

Requires full input swing from +fs to –fs.2x the swing compared to differential.Input signal at IN typically requires a

common-mode voltage for bias.Input IN\ also requires a Vcm for correct

DC-bias.

Combined differential inputs result in full-scale input of +fs to –fs.

Each input only requires 0.5x the swing compared to single-ended.

Both inputs require a Vcm for correct DC-bias.

SE vs. DE Issues• Single-ended Inputs (SEs)

– Degraded dynamic performance (larger FSR).– Common-mode voltage and op amp headroom may

limit use for DC-coupling.– Best suited for time-domain applications.

• Differential (DE)– Optimized performance due to lower FSR, reduction

of even-order and common-mode components.– Best for higher input frequencies (IFs).– More complex driver circuitry (consider diff-amps).– Best suited for frequency-domain applications.

HS-ADC Simplified Input Circuit

ø1 ø1ø2

Input Clock

Internal Clock, non-overlapping

tCONV

ø2

ø1 ø1

ø1

ø1

ø1

ø1 ø1

ø1ø2

ø2

Out

OutIn

In

CS

CH

VB

VB

VCM

VCM

CS

CH

+

-

• Requires minimumclock frequency

Driving Capacitive Input ADCs

• Due to Op amp’s finite (RO) output impedance, VOUT will drop momentarily when cap load is switched.

• As the output recovers, ringing may occur, which results in increased settling time.

• Use external R: Isolates op amp output from capacitive load and improves settling.

Cs S/H

R

RC

C

IN

IN

LO RO

VOUT

SE: Interface

RF

IN

IN

ADS82610-bit, 60Msps

VIN Rs

0.1uF

-

+

OPA691

RIN

REFT REFB

0.1uF

+2.5 VCM

(+2.5V)

+Vs

+5V

CM

(+3.5V) (+1.5V)

43Ω

499Ω

226Ω

1.5kΩ

43Ω

+5V

0.1uF

FSR = 2Vp-p

Single-ended, AC-coupled driver for single supply operation

22pF

1.5kΩ22pF

Matched, symmetric source impedances

Differential ADC Driver

Ideal Baseband Driver Solution• No transformer• VCM matched to ADC• Good even-order harmonic rejection• Easily configured for gain and low-pass filter

100Ω 600Ω

100Ω

600Ω

43.2Ω

43.2Ω

22pF

22pFVcm

VOCM ADS807THS41xxTHS45xx

Ultra-Sound Receive Chain

T/RSwitches

Transducer

LNA VGA

CWBeamformer

(Analog)

n-polefilter

*Optional*

Beamformer(FPGA,

ASIC, DSP)ADC

T/RSwitches

LNA VGA

n-polefilter

*Optional*

ADC FIFO

FIFO

ConclusionDelta-sigma, SAR, Pipeline ADCs

• Commonalities– Input stage– Input driving amplifier

• Differences– Sampling frequencies

• Appropriate Applications– Delta-Sigma: DC up to 30 ksps– SAR: 10 ksps up to 5 Msps– Pipeline: 1 Msps up to 500 Msps

Real World Analog Solutions for Your Processor Applications

Bonnie BakerSenior Applications Engineer, [email protected]

ADC: Delta-Sigma, SAR vs. Pipeline ADCs –When and Where to Use Them

real world analog solutions for your processor applications · real world analog solutions for your...

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