Section IIBasic PLD Architecture

Section II Agenda

Basic PLD Architecture—XC9500 and XC4000 Hardware

Architectures—Foundation and Alliance Series

Software

Section IIBasic PLD Architecture

XC9500 and XC4000 Hardware Architectures

XC9500 CPLDs

5 volt in-system programmable (ISP) CPLDs

5 ns pin-to-pin

36 to 288 macrocells (6400 gates)

Industry’s best pin-locking architecture

10,000 program/erase cycles

Complete IEEE 1149.1 JTAG capability

FunctionBlock 1

JTAGController

FunctionBlock 2

I/O

FunctionBlock 4

3

Global Tri-

States 2 or 4

FunctionBlock 3

I/O

In-SystemProgramming Controller

FastCONNECTSwitch Matrix

JTAG Port

3

I/O

I/O

Global Set/Reset

Global Clocks

I/OBlocks

1

XC9500 - Architectural Features Uniform, all pins fast, PAL-like architecture FastCONNECT switch matrix provides 100% routing

with 100% utilization Flexible function block

— 36 inputs with 18 outputs— Expandable to 90 product terms per macrocell— Product term and global three-state enables— Product term and global clocks— Product term and global set/reset signals

3.3V/5V I/O operation Complete IEEE 1149.1 JTAG interface

XC9500 Function Block

ToFastCONNECT

FromFastCONNECT

2 or 43 GlobalTri-State

GlobalClocks

I/O

I/O

36

Product-Term

Allocator

Macrocell 1

ANDArray

Macrocell 18

Each function block is like a 36V18 !

XC9500 Product Family9536

Macrocells

Usable Gates

tPD (ns)

Registers

Max I/O

36 72 108 144 216

800 1600 2400 3200 4800

5 7.5 7.5 7.5 10

36 72 108 144 216

34 72 108 133 166

Packages VQ44PC44 PC44

PC84TQ100PQ100

PC84TQ100PQ100PQ160

PQ100PQ160

288

6400

10

288

192

HQ208BG352

PQ160HQ208BG352

9572 95108 95144 95216 95288

XC9500XL 3.3V Key Features

High performance—tPD = 4ns, fSYS = 200MHz

36 to 288 macrocell densities

Lowest price, best value CPLD

Highest programming reliability—10,000 program/erase cycles

Most complete IEEE 1149.1 JTAG support

Space-efficient packaging, including chip scale pkg

Industry’s first 0.35um Flash CPLD

XC9500 XC9500XL

125MHz

200MHz

XC9500XL Embraces In-System Changes

Identical FBs, macrocells and I/Os

Maximum Flexibility— 54-input function block

fan-in— 90 p-terms per output— 3 global, locally invertible

clocks— global set/reset pin— p-term OE per macrocell— clock enable

Advanced, 2nd Generation Pin-Locking

New XC9500XL 3.3V Family

XC9536XL

Macrocells

Usable Gates

tPD (ns)

fSYSTEM

36 72

800 1600

4 5

200 178

Packages(Max. UserI/Os)

44PC (34)64VQ (36)

48CS (36)

44PC (34)64VQ(52)

100TQ (72)

48CS (38)

XC9572XL

144

3200

5

178

100TQ (81)144TQ (117)

144CS (117)

XC95144XL

288

6400

6

151

144TQ (117)208PQ (168)

352BG (192)

XC95288XL

CSP

BGA

XC4000 Architecture

CLB

CLB

CLB

CLB

SwitchMatrix

ProgrammableInterconnect I/O Blocks (IOBs)

ConfigurableLogic Blocks (CLBs)

D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

OutputBuffer

InputBuffer

Q D

Pad

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC

XC4000E/X Configurable Logic Blocks

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'

G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

YQ

Y

XQ

X

H1 DIN S/R EC

2 Four-input function generators (Look Up Tables)- 16x1 RAM or Logic function

2 Registers- Each can be configured as Flip Flop or Latch- Independent clock polarity- Synchronous and asynchronous Set/Reset

Look Up Tables

Capacity is limited by number of inputs, not complexity

Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM

Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB

Example:

A B C D Z

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1 . . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Look Up Table

Combinatorial Logic

AB

CD

Z

4-bit address

GFunc.Gen.

G4G3G2G1

WE

2(2 )4

= 64K !

XC4000X I/O Block Diagram

Shaded areas are not included in XC4000E family.

Xilinx FPGA Routing 1) Fast Direct Interconnect - CLB to CLB

2) General Purpose Interconnect - Uses switch matrix

CLBCLB

CLBCLB

CLBCLB

CLBCLB

SwitchMatrix

SwitchMatrix

3) Long Lines— Segmented

across chip— Global clocks,

lowest skew— 2 Tri-states per

CLB for busses

Other routing types in CPLDs

Other FPGA Resources

Tri-state buffers for busses (BUFT’s)

Global clock & high speed buffers (BUFG’s)

Wide Decoders (DECODEx)

Internal Oscillator (OSC4)

Global Reset to all Flip-Flops, Latches (STARTUP)

CLB special resources— Fast Carry logic built into CLBs— Synchronous Dual Port RAM— Boundary Scan

What’s Really In that Chip?

CLB(Red)

Switch Matrix

Long Lines(Purple)

Direct Interconnect (Green)

Routed Wires (Blue)

Programmable Interconnect Points, PIPs (White)

XC4000XL Family

* 25-30% of CLBs as RAM

* 20-25% of CLBs as RAM

4005XL 4010XL 4013XL 4020XL 4028XL

Logic Cells 466 950 1,368 1,862 2,432

Typ Gate Range* 3 - 9K 7-20K 10-30K 13-40K 18-50K(Logic + Select-RAM) Max. RAM bits 6K 13K 18K 25K 33K(no Logic)

I/O 112 160 192 224 256Initial Packages PC84 PC84

PQ100 PQ100PQ160 PQ160 PQ160 PQ160PQ208 PQ208 PQ208 PQ208 HQ208

PQ240 PQ240 HQ240BG256 BG256 BG256

BG352 BG352

4036XL 4044XL 4052XL 4062XL 4085XL 40125XV

Logic Cells 3,078 3,800 4,598 5,472 7,448 10,982

Typ Gate Range* 22-65K 27-80K 33-100K 40-130K 55-180K 78-250K(Logic + Select-RAM)

Max. RAM bits 42K 51K 62K 74K 100K 158K(no Logic)

I/O 288 320 352 384 448 544Initial packages HQ208

HQ240 HQ240 HQ240 HQ240BG352BG432 BG432 BG432 BG432PG411 PG411 PG411 PG475 PG559 PG559

BG560 BG560 BG560 BG560

CPLD or FPGA?

CPLD

Non-volatile

JTAG Testing

Wide fan-in

Fast counters, state machines

Combinational Logic

Small student projects, lower level courses

Control Logic

FPGA

SRAM reconfiguration

Excellent for computer architecture, DSP, registered designs

ASIC like design flow

Great for first year to graduate work

More common in schools

PROM required for non-volatile operation