s dc-dc onverter · 2013-08-09 · system level energy optimization techniques for a digital load...
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SYSTEM LEVEL ENERGY OPTIMIZATION TECHNIQUES FOR A DIGITAL LOAD
SUPPLIED WITH A DC-DC CONVERTER
by
Amir Parayandeh
A thesis submitted in conformity with the requirements
for the degree of Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
© Copyright by Amir Parayandeh 2013
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System Level Energy Optimization Techniques for a Digital Load Supplied with a
Dc-Dc Converter
Amir Parayandeh
Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
2013
Abstract
The demand to integrate more features has significantly increased the complexity and power
consumption of smart portable devices. Therefore extending the battery life-time has become a
major challenge and new approaches are required to decrease the power consumed from the
source. Traditionally the focus has been on reducing the dynamic power consumption of the
digital circuits used in these devices. However as process technologies scale, reducing the
dynamic power has become less effective due to the increased impact of the leakage power.
Alternatively, a more effective approach to minimize the power consumption is to continuously
optimize the ratio of the dynamic and leakage power while delivering the required performance.
This works presents a novel power-aware system for dynamic minimum power point tracking of
digital loads in portable applications. The system integrates a dc-dc converter power-stage and
the supplied digital circuit. The integrated dc-dc converter IC utilizes a mixed-signal current
program mode (CPM) controller to regulate the supply voltage of the digital load IC. This
embedded converter inherently measures the power consumption of the load in real-time,
eliminating the need for additional power sensing circuitry. Based on the information available in
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the CPM controller, a minimum power point tracking (MiPPT) controller sets the supply and
threshold voltages for the digital load to minimize its power consumption while maintaining a
target frequency. The 10MHz mixed-signal CPM controlled dc-dc converter and the digital load
are fabricated in 0.13µm IBM technology. Experimental results verify that the introduced system
results in up to 30% lower power consumption from the battery source.
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Acknowledgements
My years in graduate studies in University of Toronto have been an incredible journey primarily
because I have had the opportunity to interact with many amazing individuals. I would like to
first thank my advisor Prof. Aleksandar Prodic for his unswerving and consequential support,
patience and trust throughout these years. I owe a great deal of this work to his wisdom,
intellectual guidance and technical contributions. He is an exceptional teacher and his modesty
and integrity have always been inspiring. I will cherish many dear memories of working with
him during all these years.
I would also like to thank Prof. Olivier Trescases for his essential feedback, countless
discussions and numerous opportunities to collaborate on various projects from which I have
learned a great deal.
I am grateful to the members of my dissertation committee: Prof. Glen Gulak, Prof. Reza Iravani
and Prof. Zeb Tate for their valuable comments and suggestions.
I must also express special thanks to Dr. Brett Miwa for carefully reading the thesis and
providing extensive comments.
I would also like to thank Justin Philpott for reading parts of this thesis and providing insightful
comments and feedback.
I thank my current and former colleagues in the laboratory for power-management and integrated
SMPS: Seyed Behzad Mahdavi, Sm Ahsanuzzaman, Aleksandar Radic, Massimo Tarulli,
Zdravko Lukic, Andrija Stupar, Nabeel Rahman, Frank Zhenyu, Conny Huerta Oliviares and
Mahmoud Shousha. I thank them for their friendship, enjoyable discussions and collaborations
on numerous projects and publications. I have very fond memories of working closely with
Behzad and Ahsan.
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I would also like to thank Jaro Pristuna for CAD support during hectic IC tape-outs. Special
thanks to Prof. Glen Gulak and Jeetendar Narsinghani for their help and support in using the
high- speed tester and also to Mariusz Jarosz for tester board design.
I would also like to gratefully acknowledge the financial support of the Department of Electrical
and Computer Engineering at the University of Toronto and Natural Sciences and Engineering
Research Council of Canada (NSERC) in completing this dissertation.
I would also like thank my many friends in UofT who truly enriched my experience in these
years.
My deepest gratitude to my parents and my sisters who have been there for me in many
significant ways. I am forever grateful for their support.
Finally, I would like to thank my wife, Najmeh, for standing by my side, sustaining me through
all the hard times and most importantly, for filling my life with love and happiness. This
dissertation is dedicated to her.
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Contents
Chapter 1 Introduction ...............................................................................................1
1.1 Motivation ..................................................................................................................1
1.2 Previous Work and Thesis Objectives .......................................................................5
1.3 Brief System Description ...........................................................................................6
1.4 Thesis Overview ........................................................................................................7
Chapter 2 Low-Power CMOS Circuit Design ...........................................................9
2.1 Power and Performance in CMOS Circuits .............................................................10
2.2 Supply Voltage Scaling with Fixed Threshold Voltage ..........................................13
2.3 Supply Voltage Scaling and Threshold Voltage Scaling .........................................15
2.4 Variable Vth - Adaptive Body Biasing .....................................................................16
2.5 49-Stage Ring Oscillator Simulation Results ..........................................................18
2.6 Conclusion ...............................................................................................................21
Chapter 3 10 MHz Mixed-Signal Current Mode DC-DC Converter IC .................22
3.1 DC-DC Converter Design for Portable Applications ..............................................23
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3.2 Efficiency Optimization ...........................................................................................26
3.3 Mixed-Signal CPM DC-DC Converter IC ...............................................................31
3.3.1 Charge-Pump DAC ...................................................................................32
3.3.1.1 Effect of CP-DAC non-idealities .................................................35
3.3.2 Current Sensing Circuit Design ................................................................36
3.3.3 Windowed Analog-to-Digital Converter (ADC) ......................................43
3.3.4 Analog Comparator and Controller Timing ..............................................46
3.3.5 Gate Swing Scaling ...................................................................................48
3.3.5.1 Dual output switch-capacitor (SC) circuit ....................................48
3.3.5.2 Pulse-Controlled Variable Gate-Swing ........................................51
3.3.5.3 Gate Swing Scaling Circuit (GSSC) ............................................52
3.4 Mixed-Signal CPM IC Experimental Results ..........................................................55
3.4.1 Power-Stage Implementation ....................................................................56
3.4.2 ADC Measurements ..................................................................................58
3.4.3 Closed-Loop Transient Response .............................................................59
3.4.4 PFM Operation .........................................................................................61
3.4.5 GSSC Operation .......................................................................................62
3.4.6 Efficiency Optimization ............................................................................63
3.5 Conclusions ..............................................................................................................67
Chapter 4 Digital Test Load Design ........................................................................68
4.1 The MAC Circuit .....................................................................................................69
4.1.1 8-Bit Multiplier-Accumulator Design ......................................................71
4.2 Digital Load IC Implementation ..............................................................................71
4.3 Digital Load IC Experimental Results .....................................................................75
4.4 Conclusion ...............................................................................................................82
Chapter 5 Minimum Power Point Tracking System ................................................83
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5.1 Approaches to Minimum Power Point Tracking .....................................................84
5.2 Minimum Power Point Tracking System Architecture ............................................86
5.2.1 ABB_DAC block ......................................................................................87
5.2.2 The MAC Controller .................................................................................87
5.2.3 Dual MAC Digital Load ...........................................................................89
5.3 MiPPT controller .....................................................................................................91
5.3.1 ABB loop ..................................................................................................91
5.3.2 MiPPT Algorithm .....................................................................................93
5.4 Experimental Results ...............................................................................................96
5.4.1 ABB Loop Operation ................................................................................99
5.4.2 MiPPT Controller ...................................................................................101
5.4.3 Comparison with DVS ............................................................................105
5.5 Conclusions ............................................................................................................107
Chapter 6 Conclusions ...........................................................................................108
6.1 Suggestions for Future Work .................................................................................111
Appendix A Peak Current Mode DC-DC Converter IC with Current Observer ......113
A.1. Introduction ..........................................................................................................113
A.2. Mixed Signal Current Observer Module ..............................................................115
A.2.1. Hybrid Bi-Directional Delay-Line-Counter Architecture .....................115
A.2.2. Delay Bias Control Block .....................................................................118
A.2.3. Current Observer Simulation ................................................................119
A.3. Calibrating The Observer Slopes .........................................................................121
A.4. Experimental Results ...........................................................................................124
References .......................................................................................................................129
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List of Figures
Figure 1.1: World portable electronics market: retail sale value( US$bn) ..................................... 2
Figure 1.2: Simplified architecture of the system ........................................................................... 7
Figure 2.1: Normalized dynamic power with variable and fixed supply voltage ......................... 14
Figure 2.2: Normalized energy/operation with variable and fixed supply voltage ....................... 14
Figure 2.3: Schematic and cross-section of a CMOS inverter with adaptive body biasing .......... 17
Figure 2.4: Vth versus body-bias for NMOS and PMOS in 0.13µm ............................................ 17
Figure 2.5:FrequencyofringoscillatorsimulatedinCMOS0.13μmprocessasbody
potentials and supply voltage change......................................................................... 19
Figure 2.6: Frequency curves in VDD plane ................................................................................... 19
Figure 2.7: Constant frequency curves in VDD-Vth space .............................................................. 20
Figure 2.8: Power in VDD-Vth space .............................................................................................. 21
Figure 3.1: Modeled efficiency of the converter ,Vin = 2.5,Vout =1, fs =10MHz ........................... 27
Figure 3.2: Each loss component as a percentage of total loss ..................................................... 27
Figure 3.3: Efficiency curves as the gate-voltage swing increases ............................................... 29
Figure 3.4: Efficiency curves as the number of segments increase .............................................. 29
Figure 3.5: Efficiency optimization achieved by the combination of the two methods .............. 30
Figure 3.6: Simplified architecture of the integrated dc-dc converter with mixed-signal CPM
controller .................................................................................................................... 31
Figure 3.7: CP-DAC block diagram ............................................................................................. 33
Figure 3.8: Calibration circuit for digital current command ic[n] ................................................. 36
Figure 3.9: Current-sensing circuit block diagram ....................................................................... 37
Figure 3.10: Simulated loop gain of the current sensing circuit vs. load ...................................... 40
Figure 3.11: Inaccuracy of the current sensor versus the load ...................................................... 40
Figure 3.12: Current sensing error versus load for power-transistors with segmentation and
without segmentation ................................................................................................. 41
Figure 3.13: ADC characteristics for mixed-signal controller of the dc-dc converter ................. 43
Figure 3.14: Differential delay-line ADC architecture ................................................................. 45
Figure 3.15: ADC input bias stage ................................................................................................ 45
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Figure 3.16: Asynchronous CMOS analog comparator ................................................................ 47
Figure 3.17: Mixed-mode control loop timing ............................................................................. 47
Figure 3.18: Gate-Swing controller architecture, switch-capacitor circuit diagram and switch-
configurations for generating different gate-drive voltages ....................................... 49
Figure 3.19: Circuit modifications and waveforms for simultaneous gate-voltage swing
scaling on both power MOSFETS ............................................................................. 49
Figure 3.20: Pulse-controlled variable gate-voltage swing circuit and associated waveforms .... 51
Figure 3.21: GSSC circuit architecture ......................................................................................... 53
Figure 3.22: Block diagram of swing-controller block ................................................................. 53
Figure 3.23: Waveforms describing the operation of GSSC circuit ............................................. 53
Figure 3.24: Charge controller logic block and waveforms showing its operation ...................... 54
Figure 3.25: Die photo of the CPM dc-dc converter IC ............................................................... 55
Figure 3.26: Basic layout design for hybrid waffle structure ....................................................... 57
Figure 3.27: Die photo of power-stage with waffle structure ....................................................... 57
Figure 3.28: The transfer characteristic of ADC. Vref = 1V, e[n] is in gray encoding format ...... 58
Figure 3.29: ADC transfer characteristics for high and low resolution setting ............................ 59
Figure 3.30: Light to heavy transient response with time-optimal controller ............................... 60
Figure 3.31: Heavy to light transient response with time-optimal controller ............................... 60
Figure 3.32: Operation of the system in PFM mode ..................................................................... 61
Figure 3.33: The operation GSSC block with converter in closed loop ....................................... 62
Figure 3.34: Efficiency measurements of the mixed-signal CPM IC .......................................... 63
Figure 3.35: Optimization controller during light to heavy transient with PI controller .............. 64
Figure 3.36: Operation of the optimization controller during heavy to light transient ................. 64
Figure 3.37: Operation of the efficiency optimization controller in PFM mode. ......................... 65
Figure 3.38: Energy savings with instantaneous efficiency optimization versus estimation-
based optimization ..................................................................................................... 66
Figure 4.1 : Block diagram of the MAC unit. ............................................................................... 70
Figure 4.2:8 x 8 multiplier array ................................................................................................... 72
Figure 4.3:CSA block diagram ..................................................................................................... 72
Figure 4.4: Block diagram of 8-Bit MAC. .................................................................................... 73
Figure 4.5: Layout of the 3×4 MAC array .................................................................................... 73
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Figure 4.6: Top level layout of Digital Load IC ........................................................................... 74
Figure 4.7: Die photo of the MAC load IC ................................................................................... 75
Figure 4.8: Selected MAC outputs (PMAC), for VDD=1.3V ........................................................... 76
Figure 4.9: Selected MAC outputs (PMAC), for VDD=0.45V ......................................................... 76
Figure 4.10: Shmoo plot of MAC IC versus VDD and VBB ........................................................... 77
Figure 4.11: Power consumption of MAC IC at different operating points ................................. 79
Figure 4.12: Fixed frequency curve with variable supply and threshold voltage ......................... 80
Figure 4.13: Power consumption of the MAC IC with variable supply and threshold voltage .... 80
Figure 4.14: Power consumption of MAC IC at different target frequencies .............................. 81
Figure 5.1: Block diagram of the system implemented in this work ............................................ 86
Figure 5.2: Dual MAC IC digital load architecture ...................................................................... 90
Figure 5.3: Flowchart showing the operation of the ABB loop .................................................... 92
Figure 5.4: Operation of the ABB loop on shmoo plot................................................................. 92
Figure 5.5: Flowchart showing the operation of the MiPPT loop ................................................ 94
Figure 5.6: Operation of the MiPPT algorithm on shmoo plot ..................................................... 95
Figure 5.7: Operation of digital load IC supplied with dc-dc converter IC .................................. 98
Figure 5.8: Operation of the MAC controller implemented on FPGA ......................................... 98
Figure 5.9: Operation of the system with voltage scaling ............................................................ 99
Figure 5.10: Operation of the ABB loop .................................................................................... 100
Figure 5.11: Operation of the ABB loop: Ch-1 .......................................................................... 100
Figure 5.12: Closed-loop operation of the energy minimization controller and dc-dc
converter................................................................................................................... 102
Figure 5.13: The dc-dc converter waveforms during minimum energy tracking operation. ...... 102
Figure 5.14: Operation of the energy minimization controller with MAC IC running at
50MHz ..................................................................................................................... 104
Figure 5.15: Operation of the energy minimization controller when VDD is below the
optimum value.......................................................................................................... 104
Figure 5.16: Comparison of DVS with MiPPT controller presented in this work ..................... 106
Figure 5.17: Additional energy savings achieved compared with DVS ..................................... 106
Figure A.1: Architecture of mixed-signal ECM controller ......................................................... 114
Figure A.2: Simplified operation of current observer module .................................................... 117
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Figure A.3: Architecture of the mixed-signal current observer .................................................. 117
Figure A.4: Delay bias control block .......................................................................................... 118
Figure A.5: Open loop simulation of current observer with integrated power stage. When the
load transient occurs ic[n] also changes ................................................................... 120
Figure A.6: Closed loop Simulation of the current observer where the actual slope ratio is
different from the ideal slope ratio. .......................................................................... 121
Figure A.7: Schematic of calibration circuit ............................................................................... 122
Figure A.8: Simulation waveforms of calibration circuit for a step in ic[n] (Converter is
running in open loop with fixed duty) ..................................................................... 122
Figure A.9: Die photo of ECM IC, 1 x 2 mm2 ........................................................................... 125
Figure A.10: Propagation delays of hybrid delay-line-counter observer .................................... 127
Figure A.11: Ideal steady state slope ratio of inductor current and observed current ................ 127
Figure A.12: Light to heavy load step response of ECM IC with time-optimal controller ........ 128
Figure A.13: The efficiency of the converter running 10MHz, Vg = 2.5 .................................... 128
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List of Acronyms
MiPP Minimum Power Point
MiPPT Minimum Power Point Tracking
ADC Analog-to-Digital Converter
CPM Current Program Mode
ABB Adaptive Body Biasing
DVS Dynamic Voltage Scaling
DVFS Dynamic Voltage and Frequency Scaling
FBB Forward Body Biasing
RBB Reverse Body Biasing
ZBB Zero Body Biasing
PFM Pulse Frequency Modulation
SMPS Switch-Mode Power Supply
E-CPM Emulated Current Program Mode
SiP System in Package
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GSSC Gate Swing Scaling Circuit
CCM Continuous Conduction Mode
DCM Discontinuous Conduction Mode
DAC Digital-to-Analog Converter
LUT Look-up Table
PI Proportional Integrator
CP-DAC Charge Pump DAC
GBW Gain Bandwidth
SC Switch Capacitor
FSM Finite State Machine
MAC Multiplier Accumulator
DSP Digital Signal Processing
CSA Carry Save Adder
ESD Electrostatic Discharge
PRBS Pseudo Random Bit Sequence
ECM Emulated Current Mode
SCM Sensorless Current Mode
DPWM Digital Pulse Width Modulator
1
Chapter 1 Introduction
Introduction
1.1 Motivation
Portable electronic devices have increasingly become an indispensable part of every-day life.
The portable consumer electronics market, shown in Figure 1.1, has grown at a staggering rate
during the past decade [1]. In this market, sub-sectors such as mobile phones and portable
2
computers have particularly seen high growth rates in recent years. The key factor behind this
expansion is the increasing demand for portable devices that offer convergence of different
technologies in a single product. For example, mobile phones now integrate technologies such as
streaming video, camera, MP3, global positioning system (GPS) navigation, and different
software applications in a single device.
This growing complexity, while increasing the power consumption of the smart devices, has not
been matched by improvements in the capacity of the energy sources. Despite significant efforts
invested in development of new sources, lithium-ion batteries that have limited capacity, remain
the primary supplier of energy in portable applications [2]. As a consequence, sustaining long
Figure 1.1: World portable electronics market: retail sale value( US$bn) [1]
0
50
100
150
200
250
300
350
400
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010
Portable media players
Camcorders
Cameras
Portable computers
Mobile phones
3
battery-powered operation has become a major challenge in these applications. For this reason,
reducing the power consumption of portable devices has become a compelling design constraint.
A large portion of the power consumption in portable devices is attributed to various digital
processors that are commonly implemented in a standard CMOS process. Similar to other digital
CMOS logic circuits, the power consumption is dominated by two components: dynamic power
and leakage power [3].The dynamic component is dissipated through charging and discharging
the gate capacitances of logic circuits [4]. The leakage power, a consequence of non-ideal
transistor characteristics, is caused by the current flowing through transistors of the logic circuit
during its off state [5]. To extend the battery operation, various technology based, architecture
based and circuit based solutions that reduce the sum of the two power components without
sacrificing the processing speed have been developed. At the technology level, feature size
scaling has continuously brought lower power circuits by reducing the supply voltages [3]. To
retain performance, the threshold voltages of these circuits have also been reduced with
technology scaling. However in recent technologies, the benefits of constant-field scaling have
been compromised by an exponential increase in the leakage current [5]. On the architectural
level, pipelining and parallelism have helped in lowering power consumption of digital circuits
[6, 7]. At the circuit level, various low-power techniques have been discussed in the literature in
recent years [5-9]. Two most commonly used techniques are clock and power gating [3]. Clock
gating consists of disabling the clocks to the sections of the digital circuit that are not needed.
Disabling the clocks eliminates the switching activity and therefore the dynamic power. On the
other hand, to eliminate leakage power, power gating is widely used. This is achieved by
inserting high threshold transistors between the supply rails and the digital logic. When these
transistors are turned off, they significantly decrease the leakage current.
4
Another subsection of the low-power circuit techniques is changing the supply and/or threshold
voltage of the transistors in the digital circuit. Particularly, it has been shown that combining the
use of supply voltage and threshold voltage scaling is a tractable approach in minimizing power
dissipation while meeting the performance requirement [10-13].
The dynamic power consumption of a digital circuit can be reduced quadratically ( ) by
scaling down the supply voltage [7]. The supply voltage reduction also slows down the logic
gate. Under this condition, the speed requirement of the digital circuit can only be met if the
threshold voltage is also scaled down. However, this increases the leakage current [5].
Optimizing the trade-off between the dynamic and leakage power results in the minimum power
point (MiPP) for a given circuit. Since the target speed is maintained during the optimization
process, MiPP also corresponds to the minimum energy point of the circuit. Consequently, the
minimum power point is defined as an optimal combination of supply and threshold voltage,
where the total energy usage per desired operation of the digital circuit is minimized [10-27]. As
a result, operating at MiPP has become an important objective in energy constraint applications.
In real circuits, the MiPP is not a fixed point and changes with the workload and the operating
condition (e.g. temperature). For this reason a dynamic run-time optimization algorithm is
required to track the MiPP and effectively minimize the energy usage.
In portable applications, a dc-dc converter is used to deliver power from the battery to the digital
processor load [28-30]. The dc-dc converter provides a well regulated supply voltage for the
digital load where the current drawn from the converter is a function of the workload. For
portable applications, the design of the dc-dc converter faces two opposing constraints: To
maximize battery life, the converter needs to deliver power with high power processing
efficiency over a wide load range. On the other side, to reduce the volume and cost, it needs to
5
operate at high (multi-MHz) switching frequencies where the losses are also higher. This thesis
discusses the design of a dc-dc converter that meets these criteria. But more importantly, the
focus of the thesis is on developing a system level solution that uses the dc-dc converter to
implement minimum power point tracking for a digital circuit.
1.2 Previous Work and Thesis Objectives
An important challenge in implementing the minimum power point tracking (MiPPT) algorithm
is measuring/estimating the power consumption of a digital circuit in real-time. To do this,
various techniques have been proposed in the literature. A common estimation technique is to
use replica circuits that mimic the leakage and dynamic power consumption of the actual circuit
[10, 11, 13, 18, 19, 24]. The major drawback of the replica technique is that it cannot accurately
track the behaviour of the actual circuit as process and operating conditions change. For this
reason, it is desirable to measure the total power consumption directly. This can be achieved by
using sense resistors [31] and fairly demanding measurement circuits. However, this approach
significantly increases the circuit complexity and leads to additional losses, reducing energy-
saving gains. More importantly an analog-to-digital (ADC) converter is required to quantize the
measured current. As a result, the area and power overhead of the minimum power point tracking
algorithm increases, making direct measurement impractical in numerous applications. A direct
energy sensing technique that does not use a sense resistor or any high-bandwidth analog
circuitry was presented in [17]. However, the proposed circuit requires two relatively large on-
chip capacitors and has a fairly limited bandwidth preventing its use with highly dynamic loads,
which are very common in the low power applications. During periodic measurements, the
6
proposed circuit also disables the controller of the dc-dc converter supplying the load. This
presents a serious reliability issue since the supply voltage is not regulated during measurement
the phase.
Another drawback of all previous implementations of the minimum power or energy tracking
systems is that they assume the efficiency of the dc-dc converter is constant over the entire
range of operation [17]. However, in reality the dc-dc converter is designed with optimum
efficiency over a limited range. If, due to the operation of the MiPPT controller, the converter
operates outside this range where the efficiency is sub-optimal, the losses of the converter reduce
the energy-savings.
The main objective of this thesis is to present a run-time minimum power point tracking system
that considers both the dc-dc converter and the digital load circuit, and for any given operating
condition results in minimum energy utilization from the source.
As part of the MiPPT system, this thesis also presents a 10 MHz integrated dc-dc converter that
dynamically changes its own mode of operation to optimize the previously mentioned tradeoff
between the size and efficiency of the converter.
1.3 Brief System Description
A simplified block diagram of the minimum power point tracking system presented in this thesis
is shown in Figure 1.2. The system consists of a dc-dc converter, MiPPT controller, and a
custom-made digital circuit acting as a test load. The digital load is designed to allow
implementation of various power optimization techniques. The integrated dc-dc converter
incorporates a mixed-signal current-program mode (CPM) controller to regulate the supply
7
voltage of the digital load. The controller retains the information about the instantaneous load
current as well as the supply voltage, therefore eliminating the need for a dedicated measurement
circuitry attached to the load. This information is used to calculate the power consumption of the
digital load in real-time which is passed to the minimum power point (MiPPT) tracking
controller. Based on this information, the controller algorithm varies the supply voltage and the
threshold voltage of the digital load such that it consumes the minimum amount of energy while
operating at the desired speed. Additionally, a reconfigurable dc-dc converter architecture is
designed that dynamically adjusts its efficiency as the load current changes. The dc-dc converter
also needs to operate at the highest possible switching frequency that allows smaller physical
size and lower cost.
1.4 Thesis Overview
The thesis is organized as follows: In Chapter 2, after a brief overview of power and
performance in CMOS circuits, various low-power techniques are reviewed. Special attention is
C
VDD
L Vin
+_
Digital Load
MiPPT Controller
Vth
Mixed-Signal CPM
Controlled DC-DC Converter
Figure 1.2: Simplified architecture of the system
8
given to combined supply and threshold voltage scaling technique. The focus of Chapter 3 is the
design and implementation of the on-chip integrated 10 MHz multi-mode dc-dc converter. The
main design challenges in obtaining a highly-efficient high-frequency dc-dc converter with
instantaneous efficiency optimization are described and a complete integrated solution is
presented. Details of the implementation of the multi-mode dc-dc converter with mixed-signal
CPM controller are presented as well as experimental results of a fabricated IC. In Chapter 4,
design and implementation of the digital load IC is discussed. The MiPPT control algorithm and
its implementation are shown in Chapter 5. Finally, a summary of this work, its key
contributions, and possible future research direction are given in Chapter 6.
9
Chapter 2 Low-Power CMOS Circuit
Design
Low-Power CMOS Circuit Design
In the previous chapter it was briefly mentioned that scaling the supply and threshold voltage,
can reduce the power consumption of a logic circuit without increasing its delay. This chapter
discusses this technique in more detail. In Section 2.1, an overview of power and performance in
CMOS logic is presented. Different components of the power consumption are discussed and
their dependence on the supply and threshold voltage quantified through simple equations. It is
10
shown that, power and performance are closely related and in different cases designers can trade
power for performance or vice versa. This section also discusses power consumption metrics, i.e.
relation between instantaneous power consumption and total energy used by a circuit, and
discusses the metric selected in this work. The most basic technique to reduce the power
consumption of a digital circuit is to scale down the supply voltage. The advantages of this
technique over fixed-supply voltage, as well as its limitations are discussed in Section 2.2.
Section 2.3 continues the review of low-power methods by discussing the combined supply and
threshold voltage scaling technique. Applying this technique requires a mechanism for changing
the threshold voltage. Section 2.4 shows how this can be achieved using adaptive-body-biasing
(ABB). To better demonstrate the effectiveness of supply and threshold voltage scaling in
reducing the power consumption, Section 2.5 discusses the simulation results of a ring oscillator
circuit.
2.1 Power and Performance in CMOS Circuits
It is difficult to precisely model the performance of a digital CMOS logic circuit without
restoring to circuit simulations. However, RC delay models offer reasonable approximations for
delay of a CMOS circuit [3]. For a simple inverter circuit, the propagation delay is approximated
as
(2.1)
where, K is a constant that depends on the process, CL, is the total capacitance at the switching
node, is the supply voltage, is the transistor threshold voltage and αisgreater than1.
11
Assuming there are NL stages in the critical path (worst case) delay of the digital load, the
maximum frequency at which the circuit can operate is given by:
(2.2)
From this equation one can observe that the operating frequency of the circuit increases with
increasing supply voltage and decreasing threshold voltage.
The total power consumption in CMOS digital circuits consists of three main components shown
below [4]
(2.3)
where Pdynamic is the dynamic power, Pleakage is the leakage power and PSC is the short circuit
power.
The short circuit power is due to the short circuit current that flows from to GND (when both
PMOS and NMOS are on) while the logic is switching. For a well designed circuit, is a small
fraction of total power and can be neglected [3].
Dynamic power results from charging and discharging of the load capacitances as the gate
switches. In full-swing CMOS circuits, it is given by [3]
(2.4)
where f is the clock frequency and a, the activity factor, accounts for the fact that most gates do
not switch every clock cycle. As Eq.(2.4) shows, reducing the supply voltage lowers the power
consumption effectively due to the square relationship. The penalty, however, according to
Eq.(2.2) is lower maximum clock frequency. Consequently, in order to retain the performance of
the circuit, the threshold voltage of the transistors needs to be reduced along with the supply
voltage. Alternatively, the can be reduced by decreasing the clock frequency. Reducing
12
the frequency, however, does not result in true energy-savings from the source since the digital
load simply takes a longer time to finish the given task. As a matter of fact, it increases the
leakage energy since leakage current is now integrated over a longer period of time.
The third component of the total power consumption in the digital circuit is the leakage power.
The leakage power is due to the currents that flow through the device terminals when the gate is
off. The leakage current can be attributed to various components, but the dominant component is
subthreshold leakage given by [3]
(2.5)
where is a constant that depends on process and device geometries, is the drain-induced
barrier lowering (DIBL) coefficient, Vgs and Vds are gate-to-source and drain-to-source voltages
of the transistor and S is subthreshold slope given by
(2.6)
where n, depends on the process and VT is the thermal voltage. The leakage power has become
increasingly important in low-powercircuitdesignwithtechnologynode0.13μmandlower, as a
consequence of lower threshold voltages.
Power consumption is often a misleading metric in low-power circuit design since it can be
reduced by lowering the operating frequency and computing more slowly. Such an approach, as
discussed before, will actually increase the amount of energy drawn from the source for a given
operation. To avoid this situation, a more appropriate approach is to reduce the power
consumption while keeping the frequency constant. Since the time required to complete the
operation is constant, minimizing the power consumption, directly results in lower energy
consumption. Therefore the MiPP corresponds to the minimum energy point (MEP) of the
circuit. As a result, reducing power consumption under fixed-frequency condition can be used as
13
a meaningful metric1 in energy-performance constraint systems to compare different low-power
circuit techniques. This is the metric that will also be used throughout this thesis.
2.2 Supply Voltage Scaling with Fixed Threshold Voltage
The dynamic energy consumption of a circuit operation that takes N clock cycles to complete is
given by rearranging Eq.(2.4) as follows
(2.7)
This is also commonly referred to as energy/operation (EoP) [4]. Equation (2.4) and (2.7) show
that for a given performance target, operating the circuit above a minimum supply voltage
increases the power(energy) consumption. This is demonstrated more clearly by the plots shown
in Figure 2.1 and Figure 2.2. In Figure 2.1 the dynamic power is modeled based on Eq.(2.4) for
two cases over a range of target frequencies: For a fixed supply voltage and the minimum supply
voltage required for the desired performance. In Figure 2.2, the energy/operation is shown for the
similar two cases. For an application with lower target frequency than the maximum operating
frequency of the system, dynamic power consumption reduces linearly with frequency if the
supply voltage remains fixed. This, however, does not result in any energy saving from the
source as Figure 2.2 demonstrates. In the mean time, scaling the supply voltage as frequency
changes, reduces the dynamic power dissipation and improves energy efficiency. If, for instance,
the target frequency is reduced by 1/3, scaling the supply voltage will result in 60% lower energy
usage from the source.
1 Alternatively this metric is also referred to as minimizing the energy/operation
14
Dynam
i P
ow
er N
orm
aliz
ed
Frequency Normalized
With fixed
supply voltage
With supply
voltage scaling
Figure 2.1: Normalized dynamic power with variable and fixed supply voltage
En
erg
y N
orm
aliz
ed
Frequency Normalized
With fixed
supply voltage
With supply
voltage scaling
Figure 2.2: Normalized energy/operation with variable and fixed supply voltage
15
2.3 Supply Voltage Scaling and Threshold Voltage Scaling
Scaling the supply voltage to the optimum value, as the frequency changes, is called dynamic
voltage scaling (DVS) [29, 32-35]. Although this technique reduces the power consumption of
the circuit in a scalable manner, it does not result in minimum power consumption of the system.
The reason is that DVS does not address the leakage power in the circuit [10, 22]. This has
become particularly important in latest nanometer technology nodes, where the leakage current is
accountable for a significant portion of the total power consumption of the digital circuit.
Combining Eq.(2.4) and Eq.(2.5), the total power consumption of the digital load can be
expressed as
(2.8)
Reducing the supply voltage below the optimum value required for the target frequency can
further lower the dynamic power. In order to retain the performance of the circuit, Vth also needs
to be decreased as Eq.(2.2) shows. However a lower threshold voltage increases the
subthreshold leakage current and, consequently, the leakage power as shown by Eq.(2.5).
Essentially, applying supply and threshold voltage scaling allows for trading off the dynamic
power versus the leakage power. Consequently, an optimum ratio between these two power
components leads to the minimum power point (MiPP) for the digital circuit operating at a
certain frequency. In other words, there is an optimal supply and threshold voltage that meets the
frequency requirement of the digital load while minimizing its power consumption.
16
2.4 Variable Vth - Adaptive Body Biasing
Applying supply and threshold voltage scaling requires a mechanism that allows changing the
threshold voltage. This can be achieved by varying the body-bias voltages [3]. This technique is
called adaptive-body-biasing (ABB) [9-13, 19, 24, 27, 36-40]. The potential difference between
the source and the body terminal of the device, affects the threshold voltage as given by [3].
(2.9)
where is the transistor threshold voltage when the source is at the body potential, is the
surface potential, Vsb is the source-to-body voltage and γ is the body effect coefficient. The cross
section of a simple inverter with variable body-biasing is shown in Figure 2.3. The VBBP and
VBBN refer to the PMOS (nwell) and NMOS (pwell) body-voltages respectively and VDD is the
supply voltage of the digital circuit. Figure 2.4 demonstrates the simulated [41] threshold voltage
tuning range versus body-potential in CMOS 0.13 m technology.
For the NMOS and PMOS when VBBN is below Gnd and VBBP is above VDD respectively, the
devices are in Reverse Body Bias (RBB) mode where the threshold voltage increases [3]. On the
other hand, when VBBN rises above Gnd and VBBP is below VDD respectively, the transistors are in
Forward Body Bias (FBB) mode which reduces the threshold voltage [3]. Applying RBB
reduces the leakage current at the cost of slower performance in the circuit unless the supply
voltage VDD is increased to compensate for the delay. On the other hand, applying FBB will
improve the speed of the circuit (by lowering the threshold voltage) while increasing the leakage
current.
There is a limit to the maximum value of FBB voltage, which sets the minimum threshold
voltage that can be applied with this technique. This limit is defined by the forward-bias
17
VBBP
VBBP
VDD
Gnd
VBBN
inout
n-w
ellp
-well
n+
p+
p+
n+
n+
p+
inout
VDD
Gnd
VBBN
Gnd
VBBNFBB
GndRBB
VBBN
FBB
VDD VBBPRBB
VDDVBBP
Figure 2.3: Schematic and cross-section of a CMOS inverter with adaptive body biasing
NMOS PMOS Vth VS Body Bias
Vsb(V)
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
Vth
(V
-1.0
-0.5
0.0
0.5
1.0
NMOS
PMOS
RBB
RBB
FBB
FBB
0.4
0.8
- 0.4
- 0.8
0
- 0.8 - 0.6 - 0.4 - 0.2 0 0.4 0.8 0.2 0.6
Figure 2.4: Vth versus body-bias for NMOS and PMOS in 0.13µm
18
voltage of the source-to-body PN junction in Figure 2.3. If the PN junction becomes forward
biased, parasitic currents will flow in the wells, disrupting the operation of the circuit.
Additionally, the voltage across the pwell-nwell diode depends both on VDD and VBB. Since the
NMOS and PMOS transistors are body-biased at VBB and VDD-VBB respectively, this voltage is
equal to 2VBB -VDD. In other words, if the supply voltage is low, a large amount of FBB can
forward bias the pwell-nwell diode, disrupting the operation of the circuit. For this reason the
FBB voltage limit is lower when the supply voltage decreases.
2.5 49-Stage Ring Oscillator Simulation Results
To better demonstrate the feasibility of the supply and threshold voltage scaling technique in
reducing the power consumption, a simple 49stageringoscillatorissimulatedinCMOS0.13μm
process. The frequency of the ring oscillator is shown in Figure 2.5 as the supply and threshold
voltages change. The threshold voltage in the circuit is scaled by adjusting the NMOS and
PMOS body biases (VBBN = VBB and VBBP = VDD-VBB ) with equal steps. Although it is possible to
change Vth for PMOS and NMOS separately, it is a common technique to adjust the body-
voltages in fixed steps in order to simplify the ABB and the power minimization algorithm [10-
13, 18, 38]. As shown in Figure 2.5, higher supply voltage increases the frequency. The same
effect is achieved while reducing the threshold voltage by increasing VBB. Therefore, multiple
combinations of supply voltage and body-bias voltage will allow the circuit to operate at the
desired frequency as shown in Figure 2.6. In Figure 2.7, these points are plotted in VDD-Vth space
for different target frequencies. When the supply voltage is high, RBB can be applied to the
circuit, to increase the threshold voltage and reduce the leakage power. At lower supply voltages,
the optimum threshold voltage will also be lower. Therefore, body biases are adjusted and
19
Figure 2.5: FrequencyofringoscillatorsimulatedinCMOS0.13μmprocessasbody
potentials and the supply voltage change
0.6 0.7 0.8 0.9 1 1.1 1.2180
200
220
240
260
280
300
320
340
Fre
quen
cy (
MH
z)
VDD (V)
Increasin
g V
BB , V
DD-V
BB
ftarget = 270MHz
Figure 2.6: Frequency curves in VDD plane
20
eventually FBB is applied to decrease the threshold voltage. To meet the desired performance,
the ring oscillator can operate at any point on the constant frequency curves of Figure 2.7.
However, as Figure 2.8 shows, there is a definite single minimum power point where the trade-
off between leakage and dynamic power is optimized. The objective of the minimum power
point tracking algorithm is essentially to move along this curve (without any prior knowledge of
the load, except the VBB limits based on the process) and find the MiPP.
.
-0.6 -0.4 -0.2 0 0.2 0.4 0.60.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
VBB , VDD-VBB
VD
D (V
)
ftarget =350MHz
ftarget =300MHz
ftarget =250MHz
Figure 2.7: Constant frequency curves in VDD-Vth space
21
-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.83
4
5
6
7
8
9
10
Po
wer (µ
W)
VBB , VDD-VBB
ftarget =350MHz
ftarget =300MHz
ftarget =250MHz
VDD =1.5V
VDD =1.22V
VDD =1.4V
VDD =1.0V
VDD =0.82V
VDD =1.2V
100
150
200
250
300
350
Figure 2.8: Power in VDD-Vth space
2.6 Conclusion
In this chapter, after a brief overview of power consumption in CMOS circuit, different low-
power design techniques were discussed. In particular, it was shown that supply voltage and
threshold voltage scaling is a tractable approach in reducing the power consumption of the
circuit. The ABB technique, which can be used to tune the threshold voltage of the transistors,
was also discussed. To verify the effectiveness of this approach, simulation results of a ring
oscillator circuit were presented. As shown, different combinations of VDD-Vth voltage satisfy the
performance requirement. However from a power perspective there is an optimal VDD-Vth that
optimizes the trade-off between dynamic and leakage power such that the digital load operates at
the minimum power point.
22
Chapter 3 10 MHz Mixed-Signal Current
Mode DC-DC Converter IC
10 MHz Mixed-Signal Current Mode DC-
DC Converter IC
The focus of this chapter is design and implementation of the mixed-signal current-program
mode (CPM) controlled integrated dc-dc converter IC that features instantaneous efficiency
optimization. Main design constraints for dc-dc converters used in portable application are
presented in Section 3.1. Section 3.2 briefly reviews losses in dc-dc converters and describes the
criteria used for efficiency optimization. The design of the dc-dc converter IC with mixed-signal
23
current mode controller is presented in detail in Section 3.3. Finally, the experimental results of
the fabricated IC are shown in Section 3.4
3.1 DC-DC Converter Design for Portable Applications
The dc-dc converter design for portable electronics has become more challenging in recent years,
due to the opposing requirements and growing complexity of these devices. On the one hand,
increased processing power requires more efficient utilization of the energy source, in order to
sustain longer battery-powered operation. On the other hand, the new devices are expected to
have smaller size and lower cost. To meet these requirements, the dc-dc converters are designed
with two constraints in mind. First, the power efficiency of the converter should be improved
over a wide range of load currents. Second, the dc-dc converter should operate at the highest
possible switching frequency that allows minimization and cost reduction. It is, therefore,
desirable to propose a solution that combines high switching frequency operation with a multi-
mode efficiency improvement controller. Based on the load conditions, the multi-mode system
usually applies techniques such as variation of the number of power switch segments [42-44],
non-overlapping dead-time adjustment [45, 46], switching between pulse-width and pulse-
frequency modulation (PFM) [47-49], and gate voltage swing scaling [50-52], to improve
efficiency. These techniques, generally, minimize converter losses under light and medium
loads, as well as under other suboptimal conditions, where the efficiency of the converter is
below its peak value. Integrated dc-dc converters with voltage mode controllers, operating at
switching frequencies beyond 4 MHz [12] allow a small volume implementation but are not best
suited for on-line efficiency optimization, due to the highly dynamic nature of modern loads.
24
Since the high-frequency (HF), voltage-mode switch-mode-power-supplies (SMPS) usually do
not have reliable information about instantaneous load current, the efficiency improving mode
changes are usually performed in steady state, based on the estimated or slowly measured output
current value[44]. In this way, erroneous modes of operation during transients that can
potentially damage the power stage components are avoided. As a consequence, the benefits of
the multi-mode operation reduce or, in some cases, completely vanish as the load change
frequency increases.
To eliminate the drawbacks of voltage mode SMPS for efficiency improvement, a discrete
implementation of mixed-signal peak current-programmed mode (CPM) dc-dc converter that
provides instantaneous efficiency optimization was proposed in [52]. It utilizes an inherently
available current loop reference to determine instantaneous current for each switching cycle, and
accordingly, reconfigures the power-stage segments, adjusts the gate-swing voltage, and sets the
mode of operation such that the sum of conduction and switching losses is minimized.
The major drawback of this system as well as that of integrated mixed-signal [53] and analog
CPM solutions is significantly smaller switching frequency compared with the voltage-controlled
converters. Another important drawback of this solution [52], and other solutions that
implement efficiency optimization techniques, [51] is reliability issues related to floating gate of
power transistor or large number of transistor segments.
Mixed-signal CPM controllers have advantages over voltage-mode controllers [54] such as
inherent current-protection, reduced audio susceptibility, simpler controller implementation and
instantaneous efficiency optimization [43]. Despite these benefits, mixed-signal CPM solutions
operating at switching frequencies comparable to those of voltage-mode converter ICs do not
exist. This is caused by two unsolved implementation problems. The first problem is related to
25
power consumption of the high-bandwidth current sensing circuit, which reduces the SMPS
efficiency. The second is related to the design of a digital-to-analog converter (DAC) for the
current loop reference setting. It suffers from a tradeoff between power consumption and
accuracy, which affects the output voltage regulation.
Emulated CPM (E-CPM) controllers [55], which eliminate the need for conventional current
sensing, allow operation at switching frequencies comparable to voltage mode controllers.
However, they suffer from the major problem of mismatch between the actual and observed
inductor current slopes. This is an inherent disadvantage of E-CPM controllers. Due to the
integral nature of the controller, the mismatches grow over multiple switching cycles and
eventually saturate the controller. Therefore, sophisticated calibration techniques are required to
eliminate the mismatches, increasing complexity and power consumption of the system.
In this chapter, design and implementation of a mixed-signal CPM dc-dc converter IC is
presented [56]. The converter switching frequency at 10MHz is higher than the latest analog and
digital current-mode solutions by nearly a factor of two [53, 57]. At this frequency, the integrated
IC delivers a small form factor, reduces the cost of external components, and is suitable for
system-in-package(SiP) [58] solutions that are gaining popularity for high-efficiency conversion.
Additionally, the converter performs instantaneous efficiency optimization, by dynamically
changing modes of its operation over a wide load range. Depending on the load current, the dc-
dc converter automatically changes the number of segments of the power transistors,
dynamically adjusts power transistor gate voltages, and/or switches between continuous
conduction and pulse frequency mode of operation, to maximize efficiency for any given
operating point.
26
As described in the following sections, the high performance of the IC and its efficiency
optimization features are obtained by combining novel architectural solutions for the system
functional blocks and by modifying previous solutions. Namely, the current sensing circuit
design is optimized by utilizing advantages of instantaneous power transistor and gate-drive
segmentation. Equally important, the IC incorporates a novel gate swing scaling circuit (GSSC)
architecture that eliminates the two serious reliability issues existing in previous solutions. It
eliminates the floating gate problem causing undesirable triggering of transistors [51, 52]. It also
reduces the need for high-granularity transistor segmentation and, thus, prevents transistor burn-
out caused by delays in segments activation [43].
3.2 Efficiency Optimization
This section briefly reviews losses in the dc-dc converter and describes the criteria used for the
efficiency optimization.
The dominant sources of loss in high-frequency SMPS are the switching and conduction losses
associated with power transistors [30, 59]. The efficiency curve of a converter operating at a
fixed frequency is shown in Figure 3.1. Each loss component as a percentage of the total loss is
also shown in Figure 3.2 over the load range. As the figures demonstrate, the gate-drive and
switching losses are dominant at light load, and conduction losses are dominant in the medium to
heavy load region.
The conduction loss can be described with the following equation [43, 44, 51]
(3.1)
27
Eff
icie
ncy
Load Current (mA)
Conduction loss
dominates
Gate-drive &
switching loss
dominates
100 100010
C = 2µF
L = 0.5µH
Figure 3.1: Modeled efficiency of the converter ,Vin = 2.5,Vout =1, fs =10MHz
No
rmal
ized
Lo
ss
Load Current (mA)
Conduction loss
Gate-drive loss
Other losses
Switching loss
100 100010
Figure 3.2: Each loss component as a percentage of total loss
28
where Ron,P and Ron,N are PMOS and NMOS on-resistances and irms,P and irms,N are their respective
rms currents. Ignoring the interconnect resistance, the Ron of a segmented power stage having
equally sized transistors can be modeled as [51]
(3.2)
where Ron_0 is defined by process parameters and width of one segment, K is the number of
segments in the power-stage, Vswing is the gate-voltage swing of the transistor and Vth is the
device threshold voltage. The gate drive losses can be described with the following equation,
(3.3)
where Cg,P and Cg,N are PMOS and NMOS gate capacitances associated with charging and
discharging the transistor in one segment, Vg is the gate-drive supply voltage ,Vswing is the gate
voltage-swing on the power switch and fs is the switching frequency of the converter. For a
given process technology, the product of the gate charge and on-resistance is fixed [60]. Also,
Eq.(3.1)-(3.3) show that the conduction and gate-drive losses depend on both the number of
segments, K, and the voltage swing, Vswing. Therefore, to improve efficiency over the load range,
the number of segments in the power-stage and the gate voltage-swing can be continuously
changed such that the trade-off between the conduction and the gate drive loss is optimized [42,
44, 52]. As shown in Figure 3.3, increasing the gate-voltage swing reduces the conduction losses
(lower Ron) at the expense of higher switching losses. Therefore, the efficiency is improved at
higher currents, where the conduction loss becomes more dominant. Reducing the number of
segments, on the other hand, decreases the gate-drive losses while increasing the conduction
losses. As a result, the efficiency is improved at lower currents, as shown in Figure 3.4, where
gate-drive losses are more dominant. As mentioned before, to achieve high efficiency over the
29
Eff
icie
ncy
(%
)
Load Current (mA)
Increasing gate-
voltage swing
100 100010
Figure 3.3: Efficiency curves as the gate-voltage swing increases
Eff
icie
ncy
(%
)
Load Current (mA)
Increasing number
of segments
100 100010
Figure 3.4: Efficiency curves as the number of segments increase
30
full range by only using the segmentation technique, a large number of segments are required.
This results in a fairly complicated layout of the transistors and gate drivers in an on-chip
implementation. Even a bigger problem is that the parasitic components of the layout can cause
significant delays in some segments, unequal current distribution during switching transients,
and consequent current breakdown of the circuit under heavy load conditions.
The gate-swing scaling technique can be used to replace the segmentation technique. However,
implementation of such a circuit would require a variable-output source of relatively high power,
capable of charging the large gate capacitance of the power transistors. Such circuits usually
cause losses that partially or completely nullify the benefits of gate swing scaling [51].
In the following section an integrated dc-dc converter solution that combines the two power
saving techniques and eliminates the previously mentioned reliability and efficiency issues is
presented. As shown in Figure 3.5, combining both efficiency techniques will result in a far
better efficiency improvement over the load range. In addition to these two techniques, for the
light loads the controller operates the converter in PFM mode to achieve additional savings.
Eff
icie
ncy(%
)
Load Current (mA)
Dynamic gate-swing
scaling
100 100010
Dynamic segment
adjustment
Figure 3.5: Efficiency optimization achieved by the combination of the two methods
31
Current
Sensing Circuit
C
+
vout(t)Load
L
clk
_
Vin
Digital
Compensator
e[n]
vref (t)
+
∆ic[n]
R
SQclkProgrammable
Dead-time
Pg
ate
Ng
ate
Pen[1]
Ts
Charge
Pump DACWindowed
ADC
cmp
Gate-Swing
Scaling Circuit
Pgate
PFM
Controllerton [5:0]
c(t)
ic[n]
gssc_sl<2:0>
seg_sl<2:0>
ON CHIP
_
Sense
FET
c1(t)
c2(t)
Scan Chain
PC Interface
_+
vc(t)
Blanking
Time
Pen[2] Pen[3] Pen[4] Pen[5] Pen[6] Pen[7]
Nen[1] Nen[2] Nen[3] Nen[4] Nen[5] Nen[6] Nen[7]
Segment
Selector
Pen[7:1] Nen[7:1]
Efficiency
Optimization PFM_en
vsense(t)
Ngate
c1(t) c2(t)
gssc_en
Figure 3.6: Simplified architecture of the integrated dc-dc converter with mixed-signal CPM
controller
3.3 Mixed-Signal CPM DC-DC Converter IC
The architecture of the integrated dc-dc converter with the mixed-signal CPM controller that is
implemented in this work is shown in Figure 3.6. The controller is able to regulate the power
stage in continuous conduction mode (CCM), discontinuous conduction mode (DCM), and
operate as a pulse-frequency modulator (PFM). As proven in the previous art [43, 44, 48] such
multi-mode operation significantly improves system efficiency over the entire operating range.
The system operates as a modification of the mixed-signal peak current program mode controller
[61], where the voltage loop is digital and the internal current loop is analog. The output voltage
error is sampled and converted into its digital equivalent e[n] with a windowed analog-to-digital
32
converter (ADC) [62]. Based on the error signal, a digital compensator creates the differential
currentreferenceΔic[n]. This information is passed to the charge-pump DAC, which creates the
analog current reference. A fast asynchronous comparator [63, 64] compares the current
reference with the peak inductor current and resets the SR latch. A programmable dead-time
circuit generates the gating signals for the main switch, and the synchronous rectifier, based on
the output of the SR latch. Since, no slope compensation is employed, the steady-state duty-ratio
is limited to 50%. The digital compensator also creates the current reference ic[n] that is sent to
the efficiency optimization controller. The optimization controller in turn, governs the operation
of the segment selector, gate-swing scaling circuit and PFM controller blocks as follows: At
heavy loads, all transistor segments of Figure 3.6 are active. As the load current reduces, the
number of segments decreases. So a favourable trade-off between conduction and switching loss
is achieved. For medium-to-light loads, only one transistor segment is active and the
instantaneous efficiency optimization is obtained by changing the gate drive voltage swing with
the GSSC. For even lighter loads, the converter switches to pulse-frequency mode of operation
further minimizing switching losses and improving the overall efficiency.
3.3.1 Charge-Pump DAC
The charge pump DAC of Figure 3.6 operates as the interface between the digital voltage loop
and the analog current loop. The DAC resolution is selected based on the ADC resolution and
the load current to avoid limit cycle oscillations [53]. The DAC should also have a conversion
rate that allows the controller to operate at the switching frequency of 10MHz. With these
constraints in mind, the DAC required for the CPM controller of this work requires at least 8 bits
of resolution and a conversion period below 30ns.
33
Timing
controller
Vdd
Pass
d[3:0]
Δicn[8:0]
clk
isinkisink
isink
isink
isink isink
isink isink
0
1Programmable
Current Sink
d[3:0]×I0
Δicn[7:4]
Δicn[3:0]
Δicn[8]
01
s
s
s
16
xT
0
T0
isink
Q1
Ccp
s2
s1
Q2
Q3
Q4
Q5
Vout
Figure 3.7: CP-DAC block diagram
In current-mode control, the buck converter of Figure 3.6 can be approximated with a simple
first order plant model [54]. Therefore, a simple look-up table (LUT) based digital PI
compensator is used for steady-state regulation. The difference equation for the compensator is
given as follows:
(3.4)
where e[n] is the digital error from ADC, and A and B are the compensation coefficients. The
main advantage of the charge-pump DAC architecture is that it relies on the differential current
command value, for regulation. This significantly simplifies the architecture of the DAC.
Therefore, compared with sigma-delta [61] or flash DACs, the CP-DAC allows higher
conversion rates without excessive power consumption.
The application of CP-DAC for mixed-signal CPM dc-dc converters was proposed in [44]. The
34
resolution of the previously proposed CP-DAC decreases as the digital input increases.
Therefore, it suffers from inherent nonlinearity affecting voltage regulation and the gain of the
feedback loop. In the design introduced here 2[56], the CP-DAC is modified such that high
resolution is maintained throughout the whole operating range. This modification not only
improves the voltage regulation, but also allows implementation of fast dynamic response
control laws that usually require accurate control signals [65-68].
The CP-DAC of Figure 3.7 is a modified combination of a current-switched DAC and a
conventional charge pump circuit [69]. It operates as follows: The output voltage, i.e. analog
reference for the current loop, is changed by charging/discharging the output capacitor Ccp, with
transistors Q4 and Q5 that behave as current sources mirroring the current of the digitally
programmable current sink. The amount of charge is regulated by controlling both the charge
duration, and the current of the sink. In the previously presented design, [53] both the current and
timing are regulated in relatively crude discrete steps and the charge amount, determined based
on the product of the two, is changed in a single pulse. As a consequence, the minimum amount
of charge that can be changed in a single pulse and, hence, the quantization step of the DAC
reduces as the charging time increases. To overcome this problem, in this modification of the
CP-DAC, the amount of charge is modulated in two steps using the timing controller. In the first
step, the 4 least significant bits (LSB-s) of the signed input digital signal ic[8:0], i.e. ic[3:0]
are used to set up the current of the current sink and the charging/discharging is performed over
T0 interval. Then, in the following step, the 4 most significant bits (MSB-s), ic[7:4], are sent to
the current sink and during a 16T0-long time interval the capacitor charge is changed. As a result,
accurate charge control and high resolution of the DAC over the whole range is obtained.
2 The design, implementation and layout of the CP-DAC in this IC, is the work of Mr. Behzad Mahdavikhah.
35
3.3.1.1 Effect of CP-DAC non-idealities
As mentioned previously, in addition to ic[n], the digital compensator creates the current
reference ic[n] that is used as the control signal for instantaneous efficiency optimization. One
drawback of CP-DAC architecture [53] shown in Figure 3.7 is that the current paths for charging
and discharging the output capacitor are not exactly symmetrical. This introduces a mismatch in
the amount of charge that is transferred to and removed from the output capacitor during an
equivalent light to heavy and heavy to light load transient. For this reason, the digital current
command, ic[n], generated by the compensator does not accurately track the scaled peak inductor
current. This could result in ic[n] saturating. But more importantly, it could cause the
optimization controller to change the mode of operation based on ic[n] that is not a valid
representation of the instantaneous peak inductor current.
To overcome this problem, CP-DAC of Figure 3.7 was designed with cascode current mirrors
and layout techniques that minimize the effect of mismatches. Since the mismatch cannot be
completely eliminated during the design phase, the circuit of Figure 3.8 is used to calibrate the
digital current command ic[n] to the scaled peak inductor current.
The calibration is based on the principle that ic[n] can be periodically adjusted to match vc, the
CP-DAC output that accurately tracks the sensed peak inductor current. A ΣΔ DAC [70]
converts ic[n] to an analog voltage, vicn. When the calibration circuit is enabled (pwrDwn = 0),
the counter is incremented, and the new value of vicn based on ic[n] = ic[n-1]+δ ic[n] is compared
with vc. This process continues until the comparator output switches. At this point, the calibration
circuit is turned off, and δic[n] is stored in the digital compensator until the next calibration
phase. A similar procedure can be used to obtain a mismatch factor for calculating ic[n], as
follows: A new load is imposed on the system and subsequently removed such that the controller
36
responds to a symmetrical light-to-heavy and heavy-to-light transient. The calibration operation
is then performed to obtain δ ic[n] which precisely represents the mismatch between charging
and discharging path of the CP-DAC. The mismatch factor is then used in the digital
compensator for calculating a more accurate value for ic[n]. The ΣΔDAC has a simple, low-
power implementation as previously discussed in [70] and is powered down when the calibration
circuit is not operating. In this way, the overall power consumption of the calibration circuit
remains small, and a more accurate digital current command ic[n] is obtained for efficiency
optimization controller.
3.3.2 Current Sensing Circuit Design
In low-power on-chip integrated converters, the most common technique for sensing the inductor
current is to use a SenseFET in parallel with the high-side power transistor. Figure 3.9 shows the
simplified sensing circuit based on the architectures presented in [63, 71, 72]. The SenseFET
Digital
CompensatorCharge
Pump DAC
∆ic[n]vc
ic[n]
+_
pwrDwn
ΣΔ
modulator
RC
Filter
vicn
Counter
Logic
pwrDwn
clkcalib
clkcalib
pwrDwn
Calibration Circuit
δic[n]cmp_out
Figure 3.8: Calibration circuit for digital current command ic[n]
37
VX
K
Vin
MP
MN
+-
c1(t)
c2(t)Vb
Rsense
Isen Ip
Vsen(t)
+
-
Mps
M1
M2
M3
M4
Sense
FET
VaVb
1
Av
Figure 3.9: Current-sensing circuit block diagram
transistor, , which is embedded in the the high-side power transistor ( ) is chosen to be
times smaller than . When the high-side switch is on, is copied to the SenseFET
and therefore the voltage across the sensing resistor, , is
(3.5)
In order to achieve accurate current sensing at high switching frequencies, a high gain-bandwidth
(GBW) op-amp is required to force the drain of and to be equal. When is off,
and are used to provide a minimum bias current in the SenseFET transistor.
A major challenge in the design of the closed loop current sensing circuit of Figure 3.9 is
achieving the desired current accuracy over a wide load range [63, 72]. Generally, at medium to
38
high load currents, the current sensing circuit is designed with a high enough gain-bandwidth to
provide accurate current sensing for the desired switching frequency. However as the load
decreases, higher gain is required to achieve the same accuracy in the sensing current. For this
reason, the current sensing circuit is generally over-designed with large gain, increasing the
power consumption significantly. The following small-signal analysis makes this relationship
more clear.
The feedback network in the current sensing circuit of Figure 3.9 consists of the op-amp with
open-loop gain of , transistor and which is the on-resistance of the SenseFet. The loop
gain ( ) can be obtained by grounding and applying a test signal at the input of as
follows [73]:
(3.6)
The closed loop gain (
), therefore is
(3.7)
Additionally since the source of is small-signal ground, . Therefore,
(3.8)
For a general feedback system, the effect of loop gain variations on the closed loop gain can be
quantified as follows [73] :
(3.9)
Accordingly Eq.(3.8) becomes:
39
(3.10)
Since
and where is the mismatch in the sensed current,
based on Eq.(3.10):
(3.11)
(3.12)
where
is defined as the current sensing error. The loop gain in Eq.
(3.6) is designed based on two constraints: First to meet the required sensing accuracy based on
Eq.(3.12). Second, to achieve the unity-gain-bandwidth product (UGB) that is required for
accurate current sensing at the desired switching frequency. However as the load current
decreases from rated load to light load, decreases, reducing the loop gain. This means that at
lower currents both the accuracy and speed of the current sensing circuit reduce. The loop
gain of the circuit of Figure 3.9 is simulated and shown in Figure 3.10 versus the load
current.
Figure 3.11 shows the simulated versus the load current. As the simulation results
demonstrate, the current sensing accuracy reduces significantly at lower currents, as the loop
gain decreases.
To overcome this and relax the required GBW at lower currents, the segmented power transistors
of Figure 3.6 can be utilized. As the current decreases, the size of power transistors is reduced by
40
Figure 3.10: Simulated loop gain of the current sensing circuit vs. load
Figure 3.11: In accuracy of the current sensor versus the load
58
59
60
61
62
0 100 200 300 400
Loop G
ain (
dB
)
Output Current (mA)
0
5
10
15
20
25
30
35
40
10 100
Δse
nse
(%)
Output Current (mA)
41
turning off segments. Therefore, reduces and based on Eq.(3.12) the current sensing accuracy
improves at lower currents.
Figure 3.12 shows the simulated versus the load, for power transistors consisting of four
segments. As the segments dynamically turn-off at lower currents, the current sensing accuracy
is improved without requiring higher GBW for the sensing circuit. Therefore by utilizing
segmentation the current sensing circuit can be designed with lower power consumption and
smaller silicon area.
Figure 3.12: Current sensing error versus load for power-transistors with segmentation and
without segmentation
0
5
10
15
20
25
30
35
10 100
Δse
nse
(%)
Output Current (mA)
No Segmentation
Segmentation
42
It is important to also note that dynamic segment adjustment essentially reduces the variation
range of by copying a higher portion of the inductor current (smaller to , when
the segments turn off. This leads to two additional advantages: First the effect of op-amp offset
voltage on current sensing accuracy is also mitigated. This is simply because, at light loads, the
signal-to-offset ratio is now significantly improved compared with the non-segmented operation.
More importantly, the second advantage is that the resolution requirement of the CP-DAC is
reduced, allowing for simpler implementation with lower power consumption and smaller area.
The DAC resolution is generally chosen such that the limit cycle conditions in the controller are
avoided over different load conditions. This can be achieved when the DC output voltage change
due to one LSB change of the DAC input, , is smaller than ADC quantization step. In
other words [53]:
(3.13)
where is the dc gain of the control-to-output transfer function, is the DAC reference
voltage and is the DAC resolution. If the inductor current ripple is ignored, a simple transfer
function is obtained for where [54]. This means that at light loads, a higher
DAC resolution is required to avoid limit cycles [53]. For this reason, the DAC is generally over
designed with higher resolution, higher power consumption and larger area. On the other hand
with dynamic segment adjustment, reduces as increases. Therefore as Eq.(3.13) shows, a
lower DAC resolution, , is required to avoid limit cycle conditions. This results in reduced
power consumption of the CP-DAC, and a smaller area.
43
3.3.3 Windowed Analog-to-Digital Converter (ADC)
An important step in realizing a high performance mixed-signal controller for dc-dc converters is
ADC design and implementation. The ADC should be able to perform conversion in less than
100 ns to allow controller operation at 10MHz switching frequency and sense output voltage
variations of several millivolts. Furthermore, it is important that the ADC has a power and area
efficient architecture that does not significantly add to the complexity of the controller.
In a well designed controller, the regulated output voltage does not deviate significantly from the
reference voltage. Therefore, it is generally sufficient to quantize transient voltage excursions
Figure 3.13: ADC characteristics for mixed-signal controller of the dc-dc converter
44
within a window of the reference voltage to achieve fast dynamic response. The ADC
characteristic is shown in Figure 3.13 for a low-power mixed-signal controlled dc-dc converter.
During the steady-state operation, the converter output voltage remains in the steady-state bin,
ΔVq, the width of which is determined by voltage regulation specifications. Similarly under
transient-mode operation, the output voltage is processed by the ADC within a window of the
reference voltage denoted as ΔVmax. An important implication of this characteristic is that the
ADC requires only a few quantization bins to cover the error range employed by the digital
compensator. This significantly simplifies the design and implementation of the ADC.
The architecture of the differential delay-line ADC, used in this work, is shown in Figure 3.14
[70]. The ADC consists of two parallel delay-lines, each consisting of a series of current-starved
delay cells [74]. The propagation delay of the current-starved delay-cells can be controlled by
the amount of current supplied to them from the bias circuit. The bias current will, in turn,
depend on the control voltage at the input of the bias circuit. Therefore, the propagation delay of
cells in each delay-line changes as the input voltage of the bias circuit change.
The ADC operates based on the principle of converting continuous time voltage signal to
propagation delay, and obtaining a digital representation for the period of propagation. The input
bias stage converts the differential input voltage, , to the difference in
propagation delay of the two delay-lines. At the rising edge of the clk, a pulse begins propagating
in the delay-lines. Since, the pulse propagates with a different speed in each delay-line, its
position in the output delay-line with respect to the reference delay-line is proportional to the
differential input voltage. When the pulse in the reference delay-line reaches the cell, the
signal goes high, and samples the output delay-line. At this point, a snapshot of the
output delay-line is captured by the registers and converted into a 4-bit digital error signal. The
45
Reference delay line
Output delay line
e[n]
reset
tab[0]
Snapshot registers and
error encoder
reset
tab_ref
clk
Nth -cell
tab[1]
Nth -cell
1st -cell
1st -cell
vref (t)
Windowed ADC
Input Bias
Stage
vout(t)
tab[10] tab[12]
Figure 3.14: Differential delay-line ADC architecture
Pro
gra
mm
ab
le m
irror
VDD
vinvref R
Pro
gra
mm
ab
le m
irro
r
vc_invc_ref
CAL<1:0> CAL<1:0>
vb1
vb2
Figure 3.15: ADC input bias stage
46
ADC input bias stage is shown in Figure 3.15. The differential input stage creates two signals,
, , that control the propagation delay in the reference and output delay-lines. A two bit
calibration code, , can be used to adjust the quantization step of the ADC. The
shared degeneration resistor provides linearity and improves voltage-to-delay conversion
sensitivity [70, 75]. A detailed analysis of the delay-line ADC design is presented in [70].
3.3.4 Analog Comparator and Controller Timing
As shown in Figure 3.6, a comparator is required to compare the output of the CP-DAC with the
sensed peak inductor current. The schematic of the asynchronous CMOS comparator used in this
work is shown in Figure 3.16 [63, 64]. The circuit uses a source-coupled differential pair with
positive feedback to increase the switching speed as the polarity of the inputs change. The gain
of the positive feedback is given by [64]
(3.14)
where is the positive feedback factor that is responsible for increasing the
gain. A PMOS input pair is used to allow for low common-mode level of the sensed inductor
current. The inverter chain is used to restore the output of the comparator to the full swing. The
simulated delay of the comparator is 5ns, and its current consumption is 42µA from 2.5V supply
voltage.
The timing for the mixed-signal controller of Figure 3.6 is shown in Figure 3.17. When the
clkCPM rises, c(t) goes high, and the main switch turns on. Initially, a large current transient in the
switch causes a spike on the current-sensing output voltage, vsense(t), which can reset the SR latch
prematurely. To avoid this, a blanking circuit hides the output of the comparator from the SR
47
VDD
vin+vin-
vbias
M1
M3 M5
M2
M4M6
Figure 3.16: Asynchronous CMOS analog comparator
Ts=1/fs
c(t)
Δic[n-2] Δic[n-1] Δic[n]
Blanking Timetadc
tcomptdac
vc(t)
vsense(t)
clkcpm
Figure 3.17: Mixed-mode control loop timing
48
latch for the duration of the blanking-time. This sets a limit on the minimum duty ratio the
converter can operate with. Following the blanking-time, the ADC samples the output voltage
and sends the corresponding digital error, e[n], to the PI compensator. The compensator
calculates the change in the differential current command Δic[n] and sends the value to the CP-
DAC. The DAC updates the analog reference for the comparator, vc(t), by the end of the
blanking period, in the next clock cycle.
3.3.5 Gate Swing Scaling
As discussed previously, segmentation of power transistors and gate-drivers in low-power
SMPS, at light-to-medium loads, creates a favorable tradeoff between conduction and gate-drive
losses improving converter efficiency [42, 43, 76]. This improvement extends over a wider range
of loads as the number of segments increases. However, from the practical point of view, a high
level of transistor segmentation causes serious reliability issues. To minimize the mismatch
effect, an alternative solution proposed here is to combine dynamic adjustment of a smaller
number of segments with gate voltage swing scaling technique. In this section various
techniques to implement dynamic gate-swing scaling are discussed and compared.
3.3.5.1 Dual output switch-capacitor (SC) circuit
One proposed technique to limit the gate-voltage swing of the power switches is to lower the
supply voltage of the gate-driver circuit. This method is very effective in improving light-load
49
Gain
P
S
f =1MHz
Switches
1/2
gain_sl
[001]
2/3
gain_sl
[010]
3/4
gain_sl
[011]
4/5
gain_sl
[100]
1
gain_sl
[101]
S1 0 0 0 0 s
S2 1 p p p p
S3 p 1 p p p
S4 p p p p 1
S5 p p p p 1
S6 1 p p p p
S7 0 0 0 0 s
S8 0 s 0 s s
S9 p p p p p
S10 0 0 s s s
S11 s s s s 0
S12 1 p p p 1
S13 0 0 s s 0
S14 s s 0 0 0
S15 0 s 0 s 0
S16 1 p 1 p 1
S17 0 0 s 0 0
S [17:0]
Switch
Capacitor
Citcuit
Gate-Swing
Controller
FSM
gain_sl [2:0]
Switch Cap
Controller
Gate-Swing
Controller ic[n]
Vgate
Figure 3.18: Gate-Swing controller architecture, switch-capacitor circuit diagram and switch-
configurations for generating different gate-drive voltages
P(t)0
Vgate
Ngate
Vgate
Poff(t)Vin
0
PgateVin
Vin-VgatePswing
Nswing0
Ts
C
+
vout(t)
Lo
ad
L
_
P(t)
Vin
Ngate
Pgate
Vin
Cs
Poff (t)Q1
D 1-D
Figure 3.19: Circuit modifications and waveforms for simultaneous gate-voltage swing scaling
on both power MOSFETS
50
efficiency, due to the dependence of gate-drive switching losses on Vg2
as Eq.(3.3) shows.
However, to implement this technique, a secondary power-supply is required that allows
changing the gate-drive voltage in a certain range, without degrading the efficiency of the dc-dc
converter. A discrete switch-capacitor circuit was proposed in [43] that only operates at certain
discrete voltages and supplies the smallest segment in the power-stage. Figure 3.18 shows the
circuit diagram of the switch-capacitor circuit and the switch-configurations for generating
different gate-drive voltages. The SC circuit is controlled by the gate-swing controller block
shown in Figure 3.18, which consists of the gate swing controller FSM and the switch-cap
controller blocks. Based on the value of ic[n] the FSM block sets the 3-bit gain_sl signal that is
used by the switch-cap controller block to select the respective combination of switches S[17:0].
In order to adjust the gate voltage swing simultaneously on both power switches, a separate
switch-capacitor circuit is required for the PMOS transistor, increasing the size and cost of the
power stage considerably. To avoid this, a single switch-capacitor circuit was used by modifying
the power-stage as shown in Figure 3.19. As the associated waveforms show, an additional
PMOS transistor Q1 is used, to pull Pgate to Vin and turn the PMOS switch off during the second
subinterval. During the first subinterval, the gate-driver signal P(t), with voltage swing of Vgate,
is ac-coupled to the gate of the PMOS switch using capacitor Cx, thereby, adjusting the gate
voltage swing to Vin - Vgate as desired. A discrete implementation of this technique with
experimental results was demonstrated in [43]. However to achieve multiple voltage levels, a
larger number of switches, in addition to a large capacitor, is required. This increases the size
and cost of the power stage resulting in a system that is not feasible for on-chip implementation.
Furthermore, the losses on the switch-capacitor circuit mitigate the benefits of gate-drive voltage
scaling in improving light-load efficiency.
51
3.3.5.2 Pulse-Controlled Variable Gate-Swing
A different method for scaling the gate voltage of the power transistors is achieved by modifying
the gate-driver circuit as shown in Figure 3.20 [51, 52]. Also shown in the figure is the
configuration of signals required to operate the circuit. The basic idea behind this technique is
that by controlling the (dis)charging rate of the gate-drivers, a desired swing can be obtained on
the gate of the power transistors. The idea was originally proposed for low-swing interconnect
signalling in digital CMOS chips [77]. It was adopted in [51] to implement a charge-modulated
gate-drive circuit that improves efficiency of a dc-dc converter at light loads. A modified
implementation, more suitable for digitally controlled dc-dc converters was presented in [52]. As
the load current changes based on the value of ic[n] the digital controller adjusts the pulse widths
vout(t)
0
Vin
Ngate
Vin
0
PgateVin
Pswing
Nswing0
C
+
Lo
ad
L
_
Vin
Pgate
Vin
PPMOS
Vin
PNMOS
NNMOS0Vin
Pgate
Ngate
0
Vin
Vin
0
NPMOS
c(t)
PPMOS
NPMOS
PNMOS
NNMOS
tPMOS
tNMOS
Vin
0
Figure 3.20: Pulse-controlled variable gate-voltage swing circuit and associated waveforms
52
tPMOS and tNMOS and sets gating signals PPMOS, PNMOS, NPMOS, NNMOS. Consequently, the gate-
swing scaling circuit adjusts the voltage swings Pswing and Nswing, and sends the gate voltage
signals Pgate and Ngate to the power transistors. Compared with other techniques such as switch-
capacitor circuit, this method does not require additional switches or passive components.
Furthermore, it does not incur additional losses in the system.
The major drawback, however, is that in this architecture the gate of the power transistor is
floating during most of the period that it is on [43, 51]. Since there is no low-impedance path
driving the gate, it can easily be disturbed by voltage spikes or injection of charge from the
outside. This reliability concern has inhibited the application of this technique in low-power
integrated dc-dc converters.
3.3.5.3 Gate Swing Scaling Circuit (GSSC)
In this work, a new gate-swing scaling circuit (GSSC) architecture is proposed for the system of
Figure 3.6 that overcomes the drawbacks of the previous techniques. As shown in Figure 3.21
the new architecture is based on modifying a conventional gate-driver structure, such that a gate
voltage signal with programmable swing turns on the power transistors. To achieve this, three
new blocks i.e., the swing-controller, the class AB driver stage [78] and an analog multiplexer
switch are used in this new architecture. The architecture of Figure 3.21 shows the
implementation of GSSC for low-side power transistor; however, an equivalent implementation
is used for the high-side switch. The operation of GSSC shown in Figure 3.23, is described as
follows: The transistor gate can be driven either by the conventional gate-driver or GSSC circuit.
When gssc_en is enabled by the optimization controller, based on the control signal c2(t), the
53
Analog Multiplexer
gssc_en
c2(t)
Gate-Driver Circuit
SL1
0Swing-
Controller
Ngate
gssc_level
Pgate
Vg
Class AB
Driver
Stage
gssc_en
gssc_sl<2:0>
c2(t)
c2(t)
Figure 3.21: GSSC circuit architecture
gssc_enCharge-Controller
Logic
gssc_sl<2:0>
gssc_level
50 fF
OP-AMP
C =
c2(t)
s_sigs_sig
level
Figure 3.22: Block diagram of swing-controller block
c(t)Vg
0Vg
0
gssc_level Ngate
Nsw
ing
Nsw
ing
c2(t)
Gate signal with adjusted swing
Figure 3.23: Waveforms describing the operation of GSSC circuit
54
gate of the power transistor is either discharged to zero through the gate-driver circuit or charged
to gssc_level by the class AB driver stage. The swing-controller, shown in Figure 3.22, consists
of the charge-controller logic block, and a simple sample and hold circuit. The charge-controller
logic block architecture and waveforms describing its operation are shown in Figure 3.24. Based
on the efficiency optimization control signal, gssc_sl<2:0>, the delay-line-multiplexer
architecture [79-81] generates a programmable pulse, . This allows controlling the amount
of charge transferred to the capacitor C, when pgate turns on. Therefore, the gssc_level can be
adjusted to one of the 8 possible voltage swing levels.
The class AB driver provides the low-impedance path to the gate of the power transistor and
suppresses the effect of any voltage spike on the gate. Therefore, the gate of the power transistor
is never floating, and reliability problems of the previous designs are avoided.
8:1 MUXgssc_sl<2:0>
Δtd
dl_tune<1:0>
mux_out
VDD
mux_out
s_sig levelpgate
ngate
s_sig
level0
VDD
tgssc_sl
pgate
s_sig
ngate
level
Figure 3.24: Charge controller logic block and waveforms showing its operation
55
3.4 Mixed-Signal CPM IC Experimental Results
The integrated mixed-signal CPM of Figure 3.6 was fabricated in 0.13µm IBM technology. The
chip micrograph is shown in Figure 3.25 and Table 3.1 summarizes its main specifications. The
die measures 2.5 × 1.5 mm2, while the total active area of the mixed-signal CPM controller is
0.25 mm2. The total power consumption of the controller is around 1.6mW in CCM and 10µA in
PFM mode. The PI compensator and the efficiency optimization controller of Figure 3.6 are
implemented on the FGPA using only 350 logic gates. The FPGA also programs the scan-chain
on the chip, in order to set various configuration signals on the IC.
Mixed-Signal
CPM Controller
Segmented Power Transistor
and Gate-Driver , GSSC block
Power Stage
Input Cap
Figure 3.25: Die photo of the CPM dc-dc converter IC
56
3.4.1 Power-Stage Implementation
The power-stage of Figure 3.6 consists of a high-side PMOS transistor and a low-side NMOS
transistor. Each transistor is divided into eight identical segments. There is a dedicated gate-
driver for every segment that also enables/disables the segment. The basic layout design of the
Table 3.1: Characteristic summary and measurment results
Specifications Value Units
CMOS Process 0.13 µm
Area 3.75 mm2
Input Voltage 2.5 V
Output Voltage 0.5-1.3 V
Rated Load 500 mA
Filter L,C 400, 0.9 nH,µF
Switching Frequency 8-10 MHz
Ron PMOS , NMOS 0.26 , 0.234 Ω
Supply Analog , Digital 2.5, 1.2 V
Peak Efficiency 83 %
CPM Controller Current 550 µA
ADC Current 50 µA
Current Sensing 300 µA
GSSC Controller 100 µA
DAC Current 25 µA
PFM Controller Current 10 µA
Digital Core 100 µA
57
S D S
D S D
S D S
Wf
Diffusion
G
Gate Poly
Figure 3.26: Basic layout design for hybrid waffle structure
Figure 3.27: Die photo of power-stage with waffle structure
58
ADC_Clk
vout (t)
Vref
en[3]
en[2]
en[1]
en[0]
Figure 3.28: The transfer characteristic of ADC. Vref = 1V, e[n] is in gray encoding format.
Ch-1: ADC_clk, 2V/div. Ch-2: Vref, 200 mV/div. Ch-3: vout, 100 mV/div. Time Scale:
200µs/div
Fig 16: The transfer characteristic of ADC. Vref = 1V, e[n] is in gray encoding format. Ch-1:
power transistors called hybrid waffle structure [82-84] is shown in Figure 3.26 . The die photo
of the power-stage is also shown in Figure 3.27. The transistor fingers are arranged in a square
format such that they share the source and drain. Metal wires running at 45 degrees connect the
source and drain in adjacent cells. Compared with multi-fingered layout [85], hybrid waffle
structure allows reducing the contribution of routing wires to overall power switch Ron. This is
mainly because as shown in Figure 3.26, the cell pitch Wf, can be designed to trade-off and
optimize the contribution of the channel resistance versus routing resistance[84].
3.4.2 ADC Measurements
The transfer characteristic of ADC is shown in Figure 3.28. The steady-state error bin is around
10mV, and other error bins are around 12mV. The ADC has a two bit resolution control that can
59
be set through the scan chain. This allows reducing the steady-state error bin to 7mV as Figure
3.29 shows. The ADC delay-line outputs are converted to digital error, en[3:0], using gray
encoding. This way, the error toggles one bit at the time and encoder design is simplified. The
ADC current consumption is around 50µA, and it achieves conversion rate of 35ns in normal
operating conditions. The ADC is operational for 0.5V < Vref <1.8V.
3.4.3 Closed-Loop Transient Response
To verify the closed loop response of the converter in CPM and fast response of CP-DAC,
Figure 3.30 and Figure 3.31 show the results of the converter operation with near time-optimal
controller [65, 68, 86-88] to a 150mA-400mA load step. The light to heavy load transient is
h
Figure 3.29: ADC transfer characteristics for high and low resolution setting, Vref = 1V
-8
-6
-4
-2
0
2
4
6
900 950 1000 1050 1100
Dig
ital
Err
or
e[n]
Vout
Low Resolution ,
CAL= 2'b00
Steady State Error Bin:
7mV - 11mV
High Resolution , CAL= 2'b11
60
Vx (t)
vout (t)
Load_Step
error[n]
CPM_Clk
fs=10 MHz
vout (t)=1 V
150 mA 400 mA
Figure 3.30: Light to heavy transient response with time-optimal controller. Ch-1: CPM_Clk,
2V/div.Ch-2:Vx(t), 5V/div.Ch-3: vout(t), 50mV/div. Time Scale:0.5µs/div
Vx (t)
vout (t)
Load_Step
error[n]
CPM_Clk
fs=10 MHzvout (t)=1 V
150 mA400 mA
Figure 3.31: Heavy to light transient response with time-optimal controller. Ch-1: CPM_Clk,
2V/div.Ch-2:Vx(t), 5V/div.Ch-3: vout(t) 100 mV/div. Time Scale:0.5µs/div
61
shown in Figure 3.30. Upon detecting the load transient, the CP-DAC based on the calculated
Δic[n], sets the new peak current value and the main switch is turned on. The inductor current
rises until it reaches the new current command value. Subsequently the main switch is turned off
and the digital compensator resumes the operation. The controller performs a similar operation
for heavy to light load transient in Figure 3.31. As shown in the figures, the controller recovers
the output voltage to the new steady-state value in 500ns with voltage deviation of about 60mV.
3.4.4 PFM Operation
The PFM controller shown in Figure 3.6 consists of a conventional clocked comparator [89] and
a delay-line-multiplexer architecture to adjust the Ton with a five bit resolution [90]. The
operation of PFM controller is shown in Figure 3.32. When the PFM_en is activated, the
controller switches the mode of operation and regulates the output voltage in PFM mode. The
PFM controller consumes 10 µA of current.
Vx (t)
PFM_enCPM_Clk
vout (t)
Figure 3.32: Operation of the system in PFM mode. Ch-2:Vx(t), 1V/div. Ch-3: vout(t),
50mV/div . Time Scale:1 µs/div
62
3.4.5 GSSC Operation
The operation of the GSSC block with converter running in closed-loop is shown in Figure 3.33.
The output of the GSSC block is directly connected to power transistors of the smallest segment
as shown in Figure 3.6 and Figure 3.21. For the purpose of experimental verification, a copy of
GSSC block was also implemented on chip. The outputs of this block, Pgate(t) and Ngate(t) are
directly connected to output pads and shown in Figure 3.33. Before GSSC is enabled both
outputs are operating at full swing. It is clear from Figure 3.33 that the rise time of Ngate(t) is
larger compared to Pgate(t). The low-side GSSC circuit is designed for half the load capacitance
compared with the high-side GSSC circuit. However in the case of Figure 3.33 both circuits see
vout (t) fs=8 MHzvout (t)=1 V
Vx (t)
CPM_Clk
Pgate (t)
Ngate (t)
gssc_en
gssc_sl
<2:0>
Figure 3.33: The operation GSSC block with converter in closed loop. Ch-1: Pgate(t), 2V/div,
Ch-2:Vx(t), 5V/div.Ch-3: vout(t),100 mV/div. Ch-4: Ngate(t), 2V/div Time Scale:500 ns/div
63
the same pad capacitance and, therefore, Ngate(t) has a slower rise time. When the GSSC
circuit is enabled, gssc_sl<2:0> is changed randomly and as shown in Figure 3.33 the transistor
gate swing signals are scaled without causing any perturbations on the output voltage.
3.4.6 Efficiency Optimization
The efficiency measurements of the system operating at 10MHz are shown in Figure 3.34 with
the optimization techniques discussed in this work. While segment adjustment improves
efficiency by as much as 4%, i.e. reduces losses by 15%, at medium load currents, GSSC allows
for improvements of around 10% (loss reduction of 30%) at light to medium loads. For load
currents below 15mA, the controller operates the power-stage in PFM mode for additional
Figure 3.34: Efficiency measurements of the mixed-signal CPM IC
35
40
45
50
55
60
65
70
75
80
85
1 10 100
Eff
icie
ncy
(%
)
Output Current (mA)
PFM Operation
With Gate Voltage
Swing Adjustment
No Optimization
With Segment
Adjustment
10% 4%
Light Load Medium Load Full Load
64
CPM_Clk
Vx (t)
vout (t)
Load_Step
gssc_en
gssc_sl<2:0>
seg_sl<2:0>
error[n]
fs=8 MHzvout (t)=1 V
150mA20mA
Figure 3.35: Optimization controller during light to heavy transient with PI controller. Ch-
1:CPM_Clk,2V/div.Ch-2:Vx(t),5V/div. Ch-3: vout(t), 50mV/div. Time Scale:1µs/div.
CPM_Clk
Vx (t)vout (t)
Load_Step
gssc_en
gssc_sl<2:0>
seg_sl<2:0>error[n]
fs=8 MHzvout (t)=1 V
150mA 40mA
Figure 3.36: Operation of the optimization controller during heavy to light transient .Ch-
1:CPM_Clk,2V/div.Ch-2:Vx(t),5V/div. Ch-3:vout(t), 50mV/div. Time Sale:1µs/div
65
savings.
The dynamic operation of the converter with optimization controller is shown in Figure 3.35 and
Figure 3.36. Figure 3.35 shows the transient response of the system with a simple PI controller
as the load changes from light to heavy. Initially at light load, only one segment is on and the
GSSC block is enabled by the optimization controller. When the transient occurs, ic[n] increases
with the inductor current. Therefore, the optimization controller dynamically scales the gate
voltages to full swing, turns off the GSSC and turns on all the segments. For the heavy to light
transient shown in Figure 3.36, the controller turns off all the segments except the smallest, turns
on GSSC block and reduces the gate voltage swing. As the current command ic[n] reduces below
the final load current, the optimization controller scales the gate swings below their final value
CPM_Clk
Vx (t)
vout (t)
PFM_enLoad_Step
gssc_en
gssc_sl<2:0>
seg_sl<2:0>
150mA 7mA
Figure 3.37: Operation of the efficiency optimization controller in PFM mode. Ch-1: CPM_Clk,
2V/div.Ch-2:Vx(t),5V/div. Ch-3:vout(t), 100mV/div. Time Scale:2µs/div
66
for a short duration. The operation of the optimization controller in PFM mode is shown in
Figure 3.37. As the load changes from heavy to light, the optimization controller initially turns
off all the segments except the smallest, and enables GSSC operation. As the load current
reduces further, the controller detects the PFM mode based on the ic[n], disables GSSC block to
minimize power consumption and enables the PFM controller.
To demonstrate the benefits of the instantaneous efficiency optimization technique, the dynamic
response of the converter is compared under two different cases: With the instantaneous
optimization controller presented in this work and with steady-state estimation-based optimizer
[44]. The operation of the estimation-based optimizer is described as follows. Upon detecting a
load transient all segments are turned on to avoid over-stressing the power transistors for the
worst case scenario. The controller remains in this state until steady-state is detected. The
Figure 3.38: Energy savings with instantaneous efficiency optimization versus estimation-based
optimization
0
2
4
6
8
10
12
0 20 40 60 80
En
erg
y S
avin
g (
%)
Frequency (kHz)
67
controller then adjusts the segments for the new load current value. The energy consumption is
measured for each controller configuration at different load transient frequencies. The energy
savings achieved with instantaneous optimization controller versus the steady-state based
technique is demonstrated in Figure 3.38. As the figure shows, the energy savings increase when
the load switches more frequently, and the dynamic efficiency optimization controller results in
up to 11% energy usage reduction.
3.5 Conclusions
A mixed-signal current-programmed mode controlled 10MHz dc-dc converter IC has been
presented in this Chapter. The IC consists of segmented power transistors and gate drivers,
mixed-mode CPM controller and efficiency optimization blocks. An optimization controller,
based on inherent current information in the control loop, dynamically adjusts the number of
segments, scales the gate voltage swing of transistors and switches to PFM mode of operation in
order to improve efficiency at different operating points. To obtain reliable operation at such a
high switching frequency and achieve efficiency optimization, novel architecture of gate swing
scaling circuit is combined with modifications of known designs of other functional blocks.
Additionally segmentation of power transistors and gate drivers is utilized to simplify the design
of the current-sensing circuit and CP-DAC and reduce their power consumption. Experimental
verification of a 0.6 W, 10 MHz buck converter IC, fabricated in a 0.13 µm process, demonstrate
the peak efficiency of 83%, near time-optimal dynamic response, instantaneous efficiency
optimization that results in up to 20% efficiency improvement and 11% energy usage reduction .
68
Chapter 4 Digital Test Load Design
Digital Test Load Design
In the previous chapter, the design of the dc-dc converter was presented in detail. This chapter
describes the design and implementation of the digital test load IC that is supplied by the dc-dc
converter in the MiPPT system. The chapter is organized as follows. In Section 4.1, the
architecture and operation of the load circuit is presented. Section 4.2 discusses some of the
implementation issues associated with the digital load and finally experimental results of the
digital test load are presented in Section 4.3.
69
4.1 The MAC Circuit
In general, a simple digital circuit, such as a ring oscillator, can be used in simulation to study
the effectiveness of supply and threshold voltage scaling method in improving energy efficiency.
This approach was adopted in Chapter 2, and results and discussions were presented. However,
a more complicated circuit is required, as an actual test load, to replicate the interaction between
leakage and dynamic power in a real processor or DSP core. This load needs to be fully digital,
consisting of both combinational and sequential logic circuits. Furthermore in order to allow
adjustment of the body-bias voltage of the NMOS transistors independent of the substrate, the
digital load circuit requires custom design and layout in a triple well process. Generally in a
processor or a digital signal processing circuit, a large portion of the total power consumption is
associated with arithmetic operations such as multiplication and addition. With these constraints
in mind, a digital test load IC, described in this chapter, is designed to explore the benefits of
supply and threshold voltage scaling in reducing the power consumption of the logic circuit. The
circuit consists of 12 multiplier-accumulator (MAC) units [3]. The purpose of the MAC unit is to
perform the following computation: where X and Y are digital input data and Z is
the previously accumulated sum. While this can be done with a multiplier and an adder, it is
much more power and area efficient to modify the multiplier to take Z as another partial product.
This is called fused Multiplier Accumulator [3, 91]. The top level block diagram of the fused
MAC unit that is implemented in this work is shown in Figure 4.1. As shown in the figure, the
Multiply-Accumulate operation can be divided into three parts, where each part can be
implemented using various architectures. As the input registers are clocked, multiplier (X) and
multiplicand (Y) are passed to the partial product generation block, where partial
70
products are generated. In the next block, a tree topology [3] consisting of Carry Save Adder
(CSA) units is used to reduce the partial product arrays. A variety of CSA architectures can be
used for partial product reductions. In this work, the (3,2) counter is used which is the most
commonly used CSA construction. In the final stage, the reduced partial products and the current
accumulator outputs are added to produce the next accumulator result. Different adder
architectures can be used in this stage such as carry-look ahead adders, carry propagate adders,
tree adders and so on to optimize performance and reduce the power consumption. Since the
registersregisters
Partial Product Generator
X Y
m n
Partial Product Reduction Tree
Final Adder
P
Accumulator
clk
ZX.Y
Figure 4.1 : Block diagram of the MAC unit.
71
focus here is not on achieving the highest speed, a simple carry propagate architecture is used in
the final stage.
4.1.1 8-Bit Multiplier-Accumulator Design
The block diagram of the unsigned-8 bit multiplier is shown in Figure 4.2. Each cell, as shown in
Figure 4.3, contains a 2-input AND gate that forms the partial product and a carry-save adder
(CSA) to add the partial product to the previous sum. The 8 output least significant bits (LSB)
are available as summation results directly from CSAs. An 8-bit carry-propagate adder generates
the remaining most significant bits (MSB). The architecture of Figure 4.2 can be easily modified
into a MAC unit by using the first rows of CSAs to add an additional input, Z<15:0>, to the
partial products running sum. The simplified block diagram of the MAC load IC is shown in
Figure 4.4.
4.2 Digital Load IC Implementation
The MAC digital test load is fabricated in 0.13µm IBM triple well CMOS process. All the logic
gates are custom designed such that the body-bias of both PMOS and NMOS transistors can be
tuned. The layout of the MAC circuit is shown in Figure 4.5. The top level layout of the digital
load IC is shown in Figure 4.6. The pad-frame contains 46 pads with ESD protection and input
and output buffers for digital signals. Separate supply rails are provided for VDD, VBBP and VBBN.
The total chip area is 1.6 × 1.6 mm2. The area penalty, associated with implementing body-bias
scaling on the chip is limited. This is because the currents that flow through the p-well and n-
well of Figure 2.3 in RBB and FBB modes are very small. For the MAC digital load IC, the area
overhead is around 10% of the total area.
72
y0y1y2y3y4y5y6y7
x0
x1
x2
x3
x4
x5
x6
x7
p8p9p10p11p12p13p14p15
p0
p1
p2
p3
p4
p5
p6
p7
z0z1z2z3z4z5z6z7
z8
z9
z10
z11
z12
z13
z14
CSA
array
CPA
Figure 4.2:8 x 8 multiplier array
x
y CinSin
SoutCout Sout
Cout Cout
Sin
y x
Figure 4.3:CSA block diagram
73
Figure 4.5: Layout of the 3×4 MAC array
registersregisters
X Y8 8
clk
registers
x<7:0> y<7:0>
z<15:0>
PMAC<15:0>
Figure 4.4: Block diagram of 8-Bit MAC.
74
Figure 4.6: Top level layout of Digital Load IC
75
4.3 Digital Load IC Experimental Results
The die micrograph of the MAC IC is shown in Figure 4.7. Since the top level of the chip is
covered with metal fills, various blocks of the IC are not visible. The core supply voltage is
1.2V. The IC is tested using Verigy (Agilent) 93000 high-speed digital SOC Tester. The input
vectors are created by two pseudo-random bit sequence (PRBS) generators. The tester
continuously compares the outputs of the chip with the expected data and generates pass/fail
signals. A few selected output waveforms of the MAC are shown in Figure 4.8-4.9 for different
clock frequencies and supply voltages. The operation of the chip is verified for supply voltages
as low as 0.45V. The maximum clock frequency of the circuit is
MAC Units
Figure 4.7: Die photo of the MAC load IC
76
clkMAC = 125 MHz
PMAC[0]
PMAC[3]
VDD=1.3V
Figure 4.8: Selected MAC outputs (PMAC), for VDD=1.3V
clkMAC = 1 MHz
PMAC[0]
PMAC[2]
PMAC[4]
VDD=0.45V
Figure 4.9: Selected MAC outputs (PMAC), for VDD=0.45V
77
125MHz at 1.3V.
The tester is used to verify the operation of the MAC over VDD-VBB space for target frequency of
100MHz at room temperature (T= 25C). This is done by using the shmoo test. At every
operating point, the tester sends the input vectors to the circuit, and based on the received output
data from the IC, generates a pass/fail signal. The resulting shmoo diagram is shown in Figure
4.10 . Moving the operating point within a single column is essentially equivalent to applying
fixed-supply voltage, variable-threshold voltage technique. Consequently by applying RBB, i.e
moving down the column, the leakage power can be reduced (higher VTH) at the cost of slowing
down the circuit. Moving across each row corresponds to applying variable-supply voltage,
VBB
VDD
RBB
FBB
Decreasing Pdyn
Decreasing Pleak
Pass/Fail Boundary line
clkMAC=100MHz
Figure 4.10: Shmoo plot of MAC IC versus VDD and VBB
78
fixed-threshold voltage technique. For every supply voltage, there is one optimal threshold
voltage that minimizes the leakage power while meeting the target frequency. These points are
located at the stair-case pass/fail boundary shown in Figure 4.10. As the supply voltage is
lowered, the dynamic power decreases. However to keep the circuit operating in the green-zone
(pass-mode) the threshold voltage needs to decrease as well. This is achieved by increasing VBB
and eventually applying FBB. As discussed in Section 2.4, parasitic forward-bias currents limit
the amount of FBB that can be applied [10]. These currents cause the logic to slow-down
unexpectedly and disrupt the operation of the circuit. This is the reason that at low supply
voltages the circuit operation fails when FBB is applied above a certain level, as shown in Figure
4.10. Therefore, there is a limit for the minimum threshold voltage and consequently the
minimum supply voltage the circuit can operate at.
The circuit can operate at any point in the green-zone of Figure 4.10 to meet the performance
requirement, but the power consumption will be different at different operating points. This is
more clearly demonstrated in Figure 4.11 where the power of the MAC IC is measured in the
permissible VDD-VBB space of Figure 4.10. It clearly shows that there is a minimum power point,
which is located at the lower supply voltage and threshold voltage.
79
A particularly interesting region in Figure 4.10 and Figure 4.11 is the pass/fail boundary. As
discussed, these operating points achieve the lowest power consumption for a given supply
voltage (minimum leakage current). These operating points are measured and plotted in Figure
4.12. Finally, Figure 4.13 shows the power consumption across the fixed-frequency curve of
Figure 4.12. As the figure clearly demonstrates, there is a definite single minimum power
operating point where the trade-off between leakage and dynamic power is optimized.
VBB (V)VDD (V)
Po
we
r (m
W)
Minimum power
point
Figure 4.11: Power consumption of MAC IC at different operating points
80
Figure 4.12: Fixed frequency curve with variable supply and threshold voltage
Figure 4.13: Power consumption of the MAC IC with variable supply and threshold voltage
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
-0.65 -0.45 -0.25 -0.05 0.15 0.35
100MHz
VD
D (
V)
VBB (V)
3
3.5
4
4.5
5
5.5
6
6.5
0.9 1 1.1 1.2 1.3
100MHz
VB
B = -0
.62
VB
B = -0
.5
VB
B = -0
.35
VB
B = -0
.22
VB
B = -0
.1
VB
B = 0
.025
VB
B = 0
.175
VB
B = .3
75
Po
wer
(m
W)
VDD (V)
VB
B = 0
.325
VB
B = 0
.475
81
The measurements shown in Figure 4.10-4.13 are repeated for different target frequencies at
room temperature (T= 25C). The resulting power consumption curves of the digital load are
shown in Figure 4.14. As expected, for lower target frequencies the MiPP moves to lower supply
voltages. However for frequencies below 40MHz, the maximum value of FBB voltage that can
be applied reduces due to the parasitic forward-bias currents. For this reason, the supply voltage
cannot be reduced as much as required (or the leakage current increased enough) to reach the
minimum power operating point. Nonetheless, even at these frequencies significant energy-
savings can be achieved by operating at the lowest possible supply voltage.
It is also interesting to note that as temperature increases the MiPP, shown for different
Figure 4.14: Power consumption of MAC IC at different target frequencies
0
1
2
3
4
5
6
7
8
9
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
VBB= -0.62
VBB= 0.475
VBB= 0.325
VBB= -0.52
VBB= 0.475
VBB= 0.35 VBB= - 0.55
VBB= 0.5
VBB= 0.2 VBB= -0.5
VBB= -0.7 VBB= 0.3
VBB= 0.375
Po
wer
(mW
)
VDD (V)
125MHz
110MHz
80MHz
40MHz 20MHz
82
frequencies in Figure 4.14, will move to the right (i.e. higher supply voltages). This is because,
the threshold voltage reduces at higher temperatures [3]. Therefore the subthreshold leakage
current increases and moves MiPP to the right.
Finally it is important to note that as technologies scale, leakage power constitutes a more
significant portion of the total power consumption in the circuit. In that situation also, the
minimum operating point of the circuit will move to the right, and body-biasing techniques can
be used to balance dynamic and leakage power more effectively.
4.4 Conclusion
The design and implementation of the digital test load is presented in this chapter. For the test
load, a more sophisticated circuit based on multipliers and adders is designed to replicate the
interaction between the leakage and dynamic power in a real circuit, more accurately. The digital
test load is implemented in IBM CMOS 0.13µm technology. Experimental results from the
fabricated IC verify the operation of digital load and show the effectiveness of applying VDD-VTH
voltage scaling in minimizing the power consumption of the circuit.
83
Chapter 5 Minimum Power Point Tracking
System
Minimum Power Point Tracking System
This chapter discusses the implementation of the minimum power point (MiPPT) tracking
system. The chapter is organized as follows: In Section 5.1, the challenges of implementing
MiPPT systems for digital CMOS circuits are explained. In particular, the issue of
measuring/estimating the power consumption of the digital circuit in real-time for MiPPT is
84
discussed. The architecture of the MiPPT system which addresses this challenge is described in
Section 5.2. The MiPPT controller and algorithm are discussed in section 5.3. Finally the
experimental results of the system are presented in section 5.3.
5.1 Approaches to Minimum Power Point Tracking
The design and implementation of a digital test load IC was presented in Chapter 4. As the
measured results demonstrated, the power consumption of a digital load can be substantially
reduced with supply and threshold voltage scaling. As described earlier, the trade-off between
the leakage and dynamic power that is achieved as a result of applying this technique, leads to
the minimum power point operating point (MiPP) for the circuit. As mentioned, the MiPP
changes when the operating conditions and the workload of the digital circuit change. Therefore
to minimize power over varying situations it becomes necessary to dynamically track MiPP.
This, points to the need for developing algorithms and circuits that can operate the digital load at
the optimal VDD-Vth point. To achieve this, the simplest technique is to characterize the load as
shown in Chapter 4 and use a look-up table to set the optimal VDD-Vth voltages. However, this
would require characterizing each chip individually, significantly complicating the IC
verification and testing process. Additionally to track the MiPP, the load needs to be
characterized versus parameter variations (ex. temperature). This would result in a large look-up
table which needs to be updated after the design has been fabricated, complicating the
implementation of the open-loop approach. For these reasons, this technique is not a practical
approach for dynamic MiPP tracking and is rarely used [10].
The more appropriate approach is to use a closed-loop system where the circuit conditions are
continuously measured and the supply and bias voltages are set accordingly to minimize the
85
power consumption. Consequently, a critical part of designing this closed-loop system is
developing circuits that can detect, and measure the changing operating conditions of the digital
processor load. While it is easier to design temperature sensors [31, 92, 93], measuring the
power consumption of the load in real-time has proven to be a more challenging task.
To accurately implement the minimum power point tracking algorithm, the simplest approach is
to directly measure the power consumption of the digital load. As discussed briefly before, one
technique is to use sense resistors [31] and measure the circuit current. However, this approach
results in significant losses reducing the energy-saving gains. Since, the value of the resistor
changes over process and temperature variations, additional calibration circuitry is also needed to
compensate for these effects. More importantly one or two analog-to-digital (ADC) converters
are required to quantize the measured current and supply voltage. These significantly increase
the area and power overhead of the minimum power point tracking (MiPPT) algorithm, making
direct measurement impractical. To overcome this, a different approach is commonly proposed
to indirectly estimate the leakage and dynamic power by using a smaller replica circuit [10, 11,
13, 18, 19, 24]. The basic idea is to use simple sensory circuits to measure the transistors Ion and
Ioff currents. The minimum power point is then obtained by maintaining a specified Ion/Ioff ratio
while satisfying the speed requirement. Although relatively simple, this approach suffers from
fundamental drawbacks. First, the optimal Ion/Ioff ratio needs to be known and adjusted as the
operating conditions change. More importantly, it is exceedingly difficult to track the interaction
between the leakage and dynamic power across the entire chip accurately using local, simple
sensory circuits. Process and temperature variations across the die can cause significant
mismatch in estimated power and result in inaccurate MiPP tracking. For these reasons, it is
86
more desirable to implement the MiPPT algorithm based on more accurate measurement of the
total power consumption of the digital load.
5.2 Minimum Power Point Tracking System Architecture
The architecture of the MiPPT system implemented in this work is shown in Figure 5.1. The
mixed-signal CPM dc-dc converter IC regulates the supply voltage of the digital load IC. The
power consumption is calculated instantaneously based on the information available in the CPM
C
VDD
L
Vin
Digital
Compensator
e[n]
+
∆ic[n]
clkcpm
Pen[1]
Pgate
ic[n]
gssc_sl<2:0> seg_sl<2:0>
ON CHIP
_
c1(t)
c2(t)
Pen[2] Pen[3]
Nen[1] Nen[2] Nen[3]
Pen[n]Nen[n]
DC-DC Efficiency
Optimization
pfm
en
Ngate
MAC Units
ILoad
MAC
Controller
PassAUXMiPPT Controller
Mixed-Signal CPM Controller
vout (t)
Sense
FET
Pgate
Ngate
ABB
DAC
VBB[n]
VBB
VBBN VBBP
Vref [n]
FPGA
VDD-VBB
clkM
AC
Xin [7
:0]
Yin [7
:0]
PM
AC
_A
UX
[15:0
]
Digital Load
PM
AC
[15:0
]
Pass
DC-DC Converter
Figure 5.1: Block diagram of the system implemented in this work
87
controller without requiring additional power measurement or estimation circuitry. The key
block of this system is the MiPPT controller. The controller algorithm sets the load parameters
(supply and the body-bias voltage) to minimize its power consumption while maintaining the
target speed. Additionally it selects the most efficient mode of operation for the dc-dc converter
as the load changes. The key functional blocks of the system and the MiPPT algorithm are
described in the following sections.
5.2.1 ABB_DAC block
As discussed in Chapter 4, the digital load is custom designed such that the body-bias of both
NMOS and PMOS transistors (VBBN, VBBP) and consequently their threshold voltages can be
adjusted. Since the digital load IC was initially designed to investigate the effectiveness of
supply and threshold voltage scaling in open-loop fashion, the body-bias generators were not
implemented on chip. Therefore in the system shown in Figure 5.1 they are implemented using
discrete components. The MiPPT controller sends the digital command VBB[n] to the ABB_DAC
block which then generates the corresponding body-bias voltages, for NMOS (VBB) and PMOS
(VDD-VBB) devices. On-chip implementation of body-bias generators has been demonstrated in
numerous publications [8, 10-13, 19, 24, 25, 27, 38, 40, 94, 95]. Since the currents that flow
through the body of the devices are very small, the overall power and area overhead of the bias
generators remain very small.
5.2.2 The MAC Controller
In Chapter 4, an advanced high-speed tester was used to characterize the digital load and verify
its functionality. However, the closed-loop system shown in Figure 5.1 cannot rely on the tester
88
or the measured results, for its operation. Therefore, a different approach is required to
continuously verify the operation of the MAC and monitor its frequency. The MAC controller
block, is used for this purpose. The target clock frequency is generated by the MAC controller.
The input vectors Xin and Yin are created using pseudo-random bit sequence (PRBS) generators
[3] in the controller block and are continuously sent to the MAC IC. The MAC controller
compares the output of the digital load, PMAC_AUX, with the output of an ideal MAC block
implemented on the FPGA, and generates the Passaux signal. If, for a given input vector,
PMAC_AUX does not match the correct output value, Passaux is immediately set to zero. However
to generate a Pass signal, the MAC controller will check the outputs for a sufficiently large set of
input vectors. In this way, the controller insures that it does not generate a false Pass signal based
on only a few selected inputs. The Passaux is sent to the MiPPT controller of Figure 5.1. It is used
to track the operation at the target speed as the MiPPT controller changes the supply and
threshold voltage of the digital load. Therefore, the MAC controller serves two purposes: First to
generate the clock and the inputs for the load IC and the ideal MAC unit; second to compare the
outputs and continuously generate a signal that informs the MiPPT controller whether the MAC
circuit is functional at the given operating conditions. As will be explained shortly, this
information enables the controller to maintain the target frequency during the optimization
operation.
For on-chip implementation, the MAC controller block can be considerably simplified. The input
vectors can be generated using PRBS circuits that are implemented on chip. Additionally a
different approach can be used to track the circuit speed and eliminate the need for the ideal
MAC. This is commonly achieved by using the critical path replica method [8, 10-13, 17-19, 23,
24, 26]. The basic idea is that, the critical (worst case) delay path of the circuit is determined
89
through simulations. This path is replicated, with an additional delay margin, using basic logic
cells such as an inverter chain. The replica path is clocked at the same frequency as the rest of
the digital load. A phase detector compares the output of the replica path with the target clock
and determines whether it is running faster, slower or equal to the target clock speed. The control
parameters (for example threshold voltage) are then adjusted accordingly to meet the target
frequency. Although relatively simple, the replica path delay technique suffers from drawbacks.
Mainly, it is challenging to design a replica path that matches and tracks the critical delay over
process, voltage and temperature variations. This is particularly important in latest nano-scale
technologies, where these variations are larger, and the circuits are more complex. To overcome
the problem associated with the critical path replica method other techniques such as embedded
sensors or Razor have also been introduced in literature [96-98]. In this work, since part of the
MiPPT system was off chip, the MAC controller approach was adopted to accurately track the
circuit speed.
5.2.3 Dual MAC Digital Load
The current consumption of the MAC IC presented in Chapter 4 is around 5mA at 100MHz
clock frequency. This poses two concerns: First, any meaningful digital load in a portable
application consumes significantly higher power. Second, the dc-dc converter IC and the
efficiency optimization techniques are designed for output current range of 30mA-300mA. With
this load current, the dc-dc converter will always operate in PFM mode. This is an unrealistic
situation for a digital load unless it is constantly in sleep mode. To overcome this problem, the
system of Figure 5.1 can be designed such that the dc-dc converter supplies multiple MAC ICs.
Alternatively to increase the power consumption of the load, a simpler solution is to modify the
90
system as shown in Figure 5.2. In the modified architecture, two MAC ICs are used as the digital
load of the dc-dc converter. The current of the auxiliary MAC is replicated by an adjustable
factor using the resistor ratio and added to the current of the main MAC. Therefore, the total load
current is given by
(5.1)
where R1/R2 is the resistor ratio. The MAC controller is also modified to compare the outputs of
both ICs, PMAC and PMAC_AUX with the expected results and generate the Pass and Passaux
signals. Additionally R1 is selected such that the supply voltage of the main MAC is slightly (1
LSB of the voltage resolution of the MiPPT algorithm) higher than the auxiliary MAC. This
ensures that the main MAC unit always functions properly (Pass =1) even as the auxiliary MAC
output fails briefly (Passaux =0) due to the operation of the MiPPT controller.
R1
+_
R2 MAC
AUX
IMAC_AUX
MAC
DC-DC
Converter
VDD VDD -R1×IMAC_AUX
R3
MAC Controller
clkMAC
clkM
AC
Xin [7
:0]
Yin [7
:0]
Xin [7
:0]
Yin [7
:0]
PMAC[15:0] PMAC_AUX[15:0]
PassAUXPass
Iload=R1/R2×IMAC_AUX+IMAC
Figure 5.2: Dual MAC IC digital load architecture
91
5.3 MiPPT controller
As discussed previously, the objective of the MiPPT controller is to minimize the power of the
system while meeting the target frequency. The MiPPT controller consists of two separate loops.
The ABB_loop constantly adjusts the threshold voltage and the MiPPT loop minimizes the
power consumption. The operation of the MiPPT controller is described in the following
sections.
5.3.1 ABB loop
A critical element of the MiPPT algorithm is the ABB loop. The function of this loop is to set
the optimal threshold voltage that enables the load to operate at the target frequency (Pass =1
and Passaux =1). The flowchart for the ABB loop is shown in Figure 5.3 and Figure 5.4 describes
the operation of the ABB loop using shmoo plot of the digital load. As discussed previously, the
threshold voltage of the digital logic in the load is adjusted by changing the body-bias of the
transistors. In order to simplify the optimization algorithm, it is a common technique to adjust
the body-bias of NMOS and PMOS in fixed steps (VBB) [10, 11, 25]. The MiPPT controller
continuously sets the VBB[n]. Based on this value the ABB_DAC generates the body bias voltages
for PMOS and NMOS transistors.
When the ABB loop is enabled, zero-body-biasing (ZBB) is applied. The controller then checks
the value of Passaux. If the auxiliary MAC is working properly (Passaux =1), VBB is decremented
by 1 LSB unit, and the digital load is biased in RBB mode. In other words, the threshold voltage
increases and the leakage current of the load slightly decreases. This is equivalent to moving
from point A to B in shmoo plot of Figure 5.4 (variable-threshold voltage, fixed-supply voltage).
92
FBB
VBB Limit
OK?
Start-up
ZBB
PassAUX=1?Yes
VBB = VBB -1 VBB = VBB +1
No
PassAUX=1?
Yes
No
Yes
VBB = VBB +1
Freq_Lock = 1No
PassAUX=1?
No
Yes
Freq_Lock = 1
Yes
VDD is lowNoRBB
VBB Limit
OK?
Figure 5.3: Flowchart showing the operation of the ABB loop
RBB
FBB
Decreasing Pdyn
A
B
C
Decreasing Pleak
VBBN,VDD-VBBP
VDD
Figure 5.4: Operation of the ABB loop on shmoo plot
93
This operation continues until the auxiliary MAC fails ( Passaux =0), indicating that the MAC has
reached the Pass/Fail boundary in Figure 5.4. At this point, the threshold voltages are set to the
previous value (VBB is incremented by 1 LSB unit) and Freq_lock signal is set to high (point C).
This indicates that at the current supply voltage, the load is operating with minimum leakage
current (maximum threshold voltage allowed for target frequency). On the other hand if upon
start-up the load is in fail state (Passaux =0), the controller increments VBB, thereby reducing the
threshold voltage until either Passaux turns high or it reaches the maximum FBB voltage
allowed.
5.3.2 MiPPT Algorithm
The flowchart shown in Figure 5.5 and the shmoo plot of Figure 5.6 demonstrate the operation of
the MiPPT loop. When the MiPPT controller is enabled (point A), initially the ABB loop is
activated. After the body-bias voltages are set (Point B), the power consumption of the load is
calculated based on the real-time information obtained from the CPM controller of the dc-dc
converter IC. The supply voltage, VDD, is then decremented (perturbed) by changing the voltage
reference of the dc-dc converter loop, Vref[n]. At lower supply voltage the digital load is slower,
therefore, the operation of the auxiliary MAC fails (Passaux =0, although the actual MAC
remains operational since its supply voltage is 1 LSB above the auxiliary MAC). At this point,
the ABB loop is activated again. To meet the target frequency it adjusts the body-biases and
lowers the threshold voltage. When the operation of the ABB loop is completed, the power
consumption of the load is measured and compared with the initial stored value. If the power of
the load is decreasing, the supply voltage is further decremented by the controller. The ABB loop
94
Start-up
ABB_Loop Cont.
Freq_Lock=1?No
Freq_Lock=1?
Yes
No
Pn
decreasing
Increasing
YesVDD = VDD -1
ABB_Loop Cont.
Freq_Lock=1?
Yes
Pn
decreasing
Perturb
Observe
VDD = VDD -1
Optimization
ABB_Loop Cont.
VDD = VDD +1
Optim_Done = 1
increasing
Freq_Lock=1?
Yes
No
Pn
decreasing
Increasing
VDD = VDD +1
Optimization
ABB_Loop Cont.
VDD = VDD -1
Optim_Done = 1
Figure 5.5: Flowchart showing the operation of the MiPPT loop
95
is activated again, and the threshold voltage is scaled lower. This cycle repeats until the power of
the load begins to rise. At this point, the loop stops and sets the previous values for the supply
and threshold voltage to operate the load at the minimum power point (point C).
As discussed in Chapter 2 and 4, lowering the supply voltage reduces the dynamic power while
lowering threshold voltage to keep the speed constant, increases the leakage power. Therefore,
the MiPPT loop is essentially trading-off dynamic power versus leakage power. This trade-off
leads to a single minimum power point that is detected by the controller due to the concave
nature of the load power consumption curve shown in Figure 4.13.
If the initial supply voltage is lower than the optimal supply voltage, then the load power
increases when the supply voltage is decremented. The controller detects this and changes
VBBN,VDD-VBBP
RBB
FBB
Decreasing Pdyn
Decreasing Pleak
clk =100MHz
A
B
C
Figure 5.6: Operation of the MiPPT algorithm on shmoo plot
96
direction to move toward the MiPP. Now the supply voltage is incremented, and ABB loop
increases the threshold voltage. The loop stops when the power of the load starts increasing.
The MiPPT controller also governs the operation of the dc-dc efficiency optimization controller.
As long as the digital load is operational (Pass =1 and Passaux =1), the efficiency controller
continuously reconfigures the dc-dc converter to minimize converter losses for the given load
current. Therefore, when the MiPPT loop settles to the minimum power point and the dc-dc
converter efficiency is maximized, the power taken from the battery source will be minimized.
The MiPPT loop can be slightly modified to take into account the effect of temperature on the
circuit. As discussed briefly before, the MiPP of the circuit shifts as temperature changes. A
simple temperature sensor [31, 99] consisting of a PTAT circuit and oscillator can be used to
measure the temperature changes. Based on this measurement the MiPPT loop can be enabled to
find the new MiPP and track the temperature variations.
5.4 Experimental Results
A prototype system based on the architecture of Figure 5.1 is built to verify the operation of the
MiPPT system presented in this thesis. The experimental waveforms of the system are shown in
Figure 5.7. The CPM controlled dc-dc converter IC is running at 8MHz. The input voltage of the
system is 2.6V. The dc-dc converter regulates the supply voltage of the main MAC at 1.2V. The
supply voltage of the auxiliary MAC at 1.18V is slightly lower as desired. The digital error,
error[n], indicates that the dc-dc converter is running in steady-state. The MAC is running at
100MHz. A selected number of MAC input vectors are also shown in Figure 5.7. The Pass signal
from the MAC controller shows that at this supply voltage with zero-body-biasing (ZBB), the
main MAC IC is functional. The operation of the MAC controller is shown in Figure 5.8 using
97
embedded logic analyzer of the FGPA. The logic analyzer samples the data using a 400MHz
internal FPGA clock. The waveforms are shown for the main MAC IC, but the results are similar
for the secondary MAC. The test vectors are generated randomly and sent to the chip. The output
data from the chip is sampled, and compared with expected results to generate the Pass signal.
The operation of the system when the reference voltage of dc-dc converter loop, Vref[n], changes
is shown in Figure 5.9. As the waveforms show, the closed-loop operation of the CPM controller
scales the supply voltage of the MAC to the new value and the dc-dc converter returns to
steady-state operation. In this case, since the new supply voltage is higher (by around 150mV),
the digital load continues to work properly. During the testing phase, extra decoupling capacitors
are used at supply voltages of the MAC ICs for additional protection. These capacitors also load
the dc-dc converter chip. This is the reason that voltage scaling response time is slow at around
6µs. However, this is not a concern since the objective here is not to design a fast dynamic-
voltage-scaling (DVS) system, and the MiPPT algorithm runs at a much slower speed.
The MiPPT algorithm and the ABB loop have simple implementations in FGPA. They can also
be easily implemented on-chip. To verify this, both blocks were synthesized in 0.13µm IBM
process using Artisan standard cell library. The total area of the MiPPT controller is about
0.0078 mm2
and its power consumption is estimated to be around 250µA. The total number of
gates are around 500. Since no additional circuitry is used for power sensing, the overall power
and area over head of the MiPPT controller remains small.
98
Vx (t)
vout (t) , VDD_MAC
CPM_Clk
fs=8 MHz
VDD_MAC_AUX
Pass
clkMAC
error[n]
Selected input vectors
1.2V
1.18V
Figure 5.7: Operation of digital load IC supplied with dc-dc converter IC. Ch-1: CPM_Clk,
2V/div. Ch-2: Vx(t), 5V/div. Ch-3: vout(t), 50mV/div.. Time Scale: 1ms/div.
ClkMAC comp clk
Xin
PMAC [15:0]
Pass
Yin
Expected outputs
ClkMAC comp clk
Xin
PMAC [15:0]
Pass
Yin
Expected outputs
ClkMAC comp clk
Xin
PMAC [15:0]
Pass
Yin
Expected outputs
ClkMAC comp clk
Xin
PMAC [15:0]
Pass
Yin
Expected outputs
Figure 5.8: Operation of the MAC controller implemented on FPGA
99
5.4.1 ABB Loop Operation
The closed-loop operation of the ABB loop is shown in Figure 5.10 and Figure 5.11. In Figure
5.10 the supply voltage of the digital load is at 1.20V. Initially ZBB is applied to the MAC. Since
the MAC is functional at this voltage when the ABB loop is enabled, the controller decrements
the value of VBB[n]. Consequently the ABB_DAC block generates the bias voltages for the MAC
chip. The PMOS and NMOS bias voltages, VBBP and VBBN, are adjusted in equal steps of 30mV
based on the value of VBB[n]. Since the load is biased in RBB mode now, the threshold voltage
increases, hence lowering the leakage current of the digital load. This is equivalent to moving the
operating point of the digital load down the column shown in Figure 4.10 at 1.20V. The loop
continues decrementing VBB[n] until the auxiliary MAC fails (Passaux =0), indicating that the
Vx (t)
vout (t) , VDD_MAC
error[n]
CPM_Clk
fs=8 MHz
PassAUX
Pass
clkMAC
Selected input vectors
Figure 5.9: Operation of the system with voltage scaling
100
VDD
VBBP (VDD-VBB)
VBBN (VBB)
1.20V
1.48V
0V
-0.3V
= 1.20V
en
Freq-LockPassAUX
Pass
VBB [n]
Figure 5.10: Operation of the ABB loop: Ch-1: VBBN, 0.2V/div. Ch-2: VBBP, 0.2V/div. Ch-3:
ABB loop enable, Ch-4: VDD, 0.2V/div. Time Scale: 1ms/div
VDD
VBBP (VDD-VBB)
VBBN (VBB)
1.03V
0.720V
0V
0.260V
= 1.03V
en
Freq-LockPassAUX
VBB [n]
Figure 5.11: Operation of the ABB loop: Ch-1: VBBN, 0.2V/div. Ch-2: VBBP, 0.2V/div. Ch-3:
ABB loop enable, Ch-4: VDD, 0.2V/div. Time Scale: 1ms/div
101
threshold voltage has increased above the optimum value. At this point, VBB is incremented by 1
LSB unit and Freq_lock signal is set to high. This indicates that the load is operating at the most
energy-efficient point for the given supply voltage. As shown, the output of the main MAC IC
does not fail (Pass =1) during the operation of the ABB loop.
The opposite process of the ABB loop is shown in Figure 5.11. The supply voltage for the MAC
is lower than the value required to operate correctly in ZBB mode. The ABB loop , therefore,
reduces the threshold voltage (increases VBB) and operates the load in FBB mode. The loop stops
when the speed of the logic is fast enough such that the auxiliary MAC operates correctly at the
target frequency (Passaux =1).
5.4.2 MiPPT Controller
The closed-loop operation of the system of Figure 5.1 with the MiPPT controller is shown in
Figures 5.12-15. The measured input power of the system is also shown in the figures. Since the
digital load operates at constant target frequency, reducing the input power will result in true
energy savings from the battery source. In Figure 5.12, when the controller is enabled, the ABB
loop is first activated to adjust the body-bias voltages. When the Freq_Lock signal is set to high,
the supply voltage is decremented, and the power of the load is measured. The operation of the
auxiliary MAC fails (Passaux =0) at the lower supply voltage, and ABB loop is enabled again to
adjust the threshold voltages. Since the power consumption of the load is decreasing, this process
is repeated until it reaches the MiPP. This results in about 30% reduction in the power
consumption from the source. Figure 5.13 shows the dc-dc converter waveforms during the
MiPPT controller operation. After the ABB loop locks the target frequency, the controller
decrements the reference voltage of the converter. The dc-dc converter immediately scales the
102
VDD =1.23V
0.98V VBBP (VDD-VBB)
VBBN (VBB)0.41V
0.54V
Pin
Optim_Done
Freq-Lock
Pass
clkMAC = 100 MHz
clkCPM = 8 MHz
PassAUX
Figure 5.12: Closed-loop operation of the energy minimization controller and dc-dc
converter: Ch-1: VBBN, 1V/div. Ch-2: VBBP, 1V/div. Ch-3: VDD, 130mV/div, Ch-4: Pin,
30mW/div. Time Scale: 7ms/div.
Freq-Lock
PassAUX
clkCPM = 8 MHz
VX(t)
VDD
Figure 5.13: The dc-dc converter waveforms during minimum energy tracking operation. Ch-
1: CPM_Clk, 2V/div. Ch-2: vout(t), 50mV/div. Ch-4:Vx(t), 2V/div. Time Scale: 1ms/div.
103
supply voltage of the digital load. The controller then waits for the next Freq-lock signal to scale
the supply voltage lower. The time between these intervals defines the speed of the MiPPT loop.
It essentially depends on the time the MAC controller takes to process the input vectors, before
generating a new Pass signal. Figure 5.14 shows the operation of the system at the target
frequency of 50MHz. The initial supply voltage of the MAC IC is at 0.96V. Similar to the
previous case, in phase A, the ABB loop applies RBB to the circuit to increase the threshold
voltage. However to reach the optimal threshold value, (just before Passaux =0) the amount of
RBB required is larger than the reverse-bias limit set in the controller. The ABB loop, therefore,
stops when it reaches the VBB limit and asserts the Freq-lock signal. In the next phase, the MiPPT
algorithm begins by scaling the supply voltage lower. In phase B, since the supply voltage is still
high and the auxiliary MAC is still functional (Passaux =1) there is no need to scale the threshold
voltages lower (by increasing VBB). Therefore, the ABB loop raises the Freq-lock signal, and the
supply voltage is scaled again. Eventually in phase C, the supply voltage is low enough that the
auxiliary MAC fails. From this point on, the controller continues its operation as described in the
previous case until it reaches the MiPP and shuts down. This results in 34% energy savings from
the source.
In Figure 5.15, the initial supply voltage is below the optimal supply voltage. After the ABB
loop adjusts the body bias voltages by applying FBB, the supply voltage is lowered. This results
in a higher power taken by the digital load as expected from Figure 4.13 and also verified by the
sudden increase in the input power shown in the figure. The controller detects this, changes
direction and instead increases the supply voltage to reduce the load power. With each VDD step,
the ABB loop also adjusts the body biases (increases the threshold voltage). When the load
power begins to rise again, the loop shuts down. As a result of the loop operation,
104
=0.96V clkMAC = 50 MHz
clkCPM = 8 MHz VDD
VBBP (VDD-VBB)
VBBN (VBB)
Pin
0.45V
0.24V
Optim_Done
Pass
PassAUX
Freq-Lock
Vref[n]
A B C
0.7V
Figure 5.14: Operation of the energy minimization controller with MAC IC running at
50MHz: Ch-1: VBBN, 1V/div. Ch-2: VBBP, 1V/div. Ch-3: VDD, 130mV/div, Ch-4: Pin,
30mW/div. Time Scale: 5ms/div
VBBP (VDD-VBB)
VBBN (VBB)
VDD =0.93V
Freq-Lock
en_optim
Optim_Done
PassAUX
Vref[n]
0.99V
Pin
0.35V
0.61V 0.58V
0.42V
clkMAC = 100 MHz
Figure 5.15: Operation of the energy minimization controller when VDD is below the
optimum value. Ch-1: VBBN, 1V/div. Ch-2: VBBP, 1V/div. Ch-3: VDD, 100mV/div, Ch-4: Pin,
50mW/div. Time Scale: 3.5ms/div
105
the power consumption is reduced by 12%.
The supply voltage step used by the MiPPT algorithm is set to around 20mV. As Figure 4.13
shows, the load power curve is flatter around the minimum point. Therefore, high resolution is
not required, and the selected step leads to a reasonable approximation of the MiPP.
The speed of the minimization algorithm is primarily limited by the length of input vectors that
the MAC controller processes before generating a Pass signal for the auxiliary MAC. Finally, as
shown in Figure 5.12 and Figure 5.14, the operation of the actual MAC is not disrupted (Pass
=1) during the minimization process.
5.4.3 Comparison with DVS
In DVS, as the workload conditions change, the supply voltage is scaled such that the system
operates only as fast as necessary. As shown in previous works, this results in significant energy
savings compared with fixed-supply voltage operation [6]. However, performing DVS on the
digital load will not yield the MiPP since the effect of threshold leakage current is entirely
ignored [10]. This has become particularly important in latest nano-scale technology nodes,
where the leakage current accounts for a significantly larger portion of total power consumption
of the digital circuit. The approach discussed here is more general than DVS technique. The
algorithm, similar to DVS, eventually scales the supply voltage to the optimal value for the target
speed. But additionally, it also adjusts the threshold voltage to optimize the ratio of dynamic and
leakage power that results in minimum power point consumption. The net benefits of the MiPPT
algorithm are compared with applying DVS only technique to the MAC IC at different
frequencies. As shown in Figure 5.16 -5.17 significant additional energy savings are achievable
using the techniques discussed in this work.
106
Figure 5.16: Comparison of DVS with MPT controller presented in this work
Figure 5.17: Additional energy savings achieved compared with DVS
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
10 30 50 70 90 110 130
Frequency (MHz)
Ener
gy /
op
era
tio
n (
nJ)
VD
D=
1.1
7V
VDD= 1.3V
VDD=0.62V
VD
D=
0.6
8V
VD
D=
0.9
4 7
V
VD
D=
0.8
2V
DVS
MPT Algorithm
1
2
3
4
5
6
7
8
10 20 30 40 50 60 70 80 90 100 110 120
Ad
ditio
na
l E
ne
rgy S
avin
g (
%)
Frequency (MHz)
107
5.5 Conclusions
A system level solution is presented in this chapter that tracks the minimum power point of a
digital load circuit. The system consists of a dc-dc converter IC that supplies a digital load IC.
The 8MHz integrated dc-dc converter utilizes a mixed-signal current mode (CPM) controller to
regulate the supply voltage and measure the power consumption of the load. A key block of this
system is the MiPPT controller that is implemented on FPGA. Based on the information
available in the CPM controller, the controller algorithm sets the load parameters (supply and
threshold voltage) to minimize its power consumption at the target frequency. Additionally, an
efficiency optimization controller dynamically reconfigures the dc-dc converter to maximize the
efficiency as the load conditions change instantaneously. Experimental results of the system
verify the operation of the MiPPT controller and the efficiency optimization controller which
results in 30% reduction in the power consumption from the source.
108
Chapter 6 Conclusions
Conclusions
As portable devices become more complex, extending the battery life-time becomes more
challenging. In order to meet this challenge, it is necessary to reduce the power consumption of
these systems without sacrificing the required performance. Generally, a considerable portion of
the power consumption in these devices is associated with one or more digital processors. The
most effective approach to minimize the power consumption in this situation is to find the
optimal ratio of the dynamic power to the leakage power while meeting the speed requirement.
This can be achieved by applying supply and threshold voltage scaling to the digital logic circuit.
The work presented in this thesis proposes a new approach to minimize the power consumption
109
of a digital logic circuit based on this technique. In this approach, the system consists of the
digital logic load as well as its power supply which is used to simplify the implementation of the
minimum power point tracking algorithm.
The main contributions of this thesis are summarized as follows:
1. 10MHz Current-Program Mode Dc-dc Converter IC: In portable applications, the
power supply of the digital processor is generally a dc-dc converter which faces two
important design challenges. Compared with existing solutions, the power processing
efficiency of the converter needs to be improved over a wide range of conditions,
including frequently varying loads. At the same time, the dc-dc converter should be able
to operate at the highest possible switching frequency that allows minimization and cost
reduction. In this thesis, design and implementation of a mixed-signal current-program
mode (CPM) controlled dc-dc converter IC with instantaneous efficiency optimization
was presented that addresses these challenges. The dc-dc converter operates at 10MHz
switching frequency, which is about two times higher than the previously implemented
analog and digital current-mode solutions. The CPM controlled dc-dc converter IC
performs instantaneous efficiency optimization, by dynamically changing modes of its
operation over a wide load range. Depending on the load current, the dc-dc converter
automatically changes the number of segments of the power transistors, dynamically
adjusts power transistor gate voltages, and switches between continuous conduction and
pulse frequency mode of operation to maximize efficiency for any given operating point.
Additionally, a new design approach was presented that utilizes the advantages of the
instantaneous power transistor and gate-drive segmentation to reduce the power
110
consumption of the current sensing circuit. The dc-dc converter IC also incorporates a
novel gate swing scaling circuit (GSSC) architecture that eliminates the floating gate
problem of the previous solutions and, at the same time, reduces the need for a high level
of transistor segmentation, both of which cause serious reliability problems. The mixed-
signal CPM controlled dc-dc converter is fabricated in a 0.13 µm process. Experimental
results demonstrate the peak efficiency of 83%, near time-optimal dynamic response,
instantaneous efficiency optimization and up to 20% efficiency improvement due to the
action of the novel efficiency optimization controller.
2. Minimum Power Point Tracking of a Digital Load with an Integrated Power Supply
The thesis described the motivation and challenges for implementing MiPPT for a digital
circuit. To address these challenges, a novel approach was presented where the power
supply of the digital load is utilized as part of the optimization process. In addition to
regulating the supply voltage, the mixed-signal CPM controlled dc-dc converter measures
the power consumption of the digital load in real-time. A MiPPT controller was also
implemented in this work that uses this information to minimize the power consumption
of the digital load while operating it at a target frequency. Additionally based on the
operation of the digital load, the controller reconfigures the multi-mode dc-dc converter
to maximize its efficiency. Experimental results of the system verify the operation of the
MiPPT controller which results in 30% reduction in the energy consumption from the
battery source.
111
6.1 Suggestions for Future Work
High switching frequency operation, combined with high efficiency, will remain an important
design issue for dc-dc converters for the foreseeable future. The main driving force for
increasing the switching frequency is to reduce the output filter volume and cost. For these
reasons, investigating the limitations of designing a CPM controlled dc-dc converter at
frequencies above 10MHz can be useful. Additionally, the dc-dc converter IC implemented in
this work does not employ slope compensation. Therefore, the duty-ratio is limited to below
50%. Implementing slope compensation for a mixed-signal current mode controller operating at
high frequencies is challenging and requires further research.
The MiPPT loop can also be implemented on-chip to investigate its power and area overhead
more accurately. It would be more suitable to implement the digital load in a smaller feature
technology (45nm or below) where the leakage currents are significantly larger and investigate
the effectiveness of the proposed approach. The dc-dc converter can also be implemented in the
same technology. This poses new challenges for the CPM controller implementation due to the
lower supply voltage available which requires further investigation. For on-chip implementation
of the MiPPT system, critical path replica delay technique can be used to lock the target
frequency and the body-bias generators should also be implemented on chip.
Additionally the measurement of the load can be repeated for different temperatures to observe
how temperature changes affecttheloadcircuit’sMiPP. A temperature sensor can be added on
chip to measure the temperature changes and run the MiPPT controller in closed-loop in order to
track the temperature variations.
112
As technologies scale, the ability of body-bias voltage scaling to tune the threshold voltages
diminishes. Therefore, other techniques are required to trade-off dynamic and leakage power of
the digital circuits. One approach that is gaining interest is operating devices in subthreshold
region by scaling the supply voltage down to the threshold voltage. This is particularly suitable
for an emerging set of energy-constraint applications that are not performance-constrained, such
as biomedical implants and remote wireless sensors [8, 15, 16, 20-22]. To obtain the minimum
energy operating point in real-time, the challenges of implementing the energy sensor remains.
Therefore, similar to the approach presented in this work, it would be beneficial to investigate
different dc-dc converter and controller architectures that would simplify implementation of the
minimum energy tracking loop.
113
Peak Current Mode DC-DC Converter IC
with Current Observer
A.1. Introduction
Peak current-program mode (CPM) controllers are widely used in dc-dc converters for their
advantages over voltage mode controllers such as inherent current-protection, reduced audio
susceptibility and simpler controller implementation [54, 100-102]. Despite these benefits, CPM
controllers have found limited use in low-power high frequency switch-mode power supplies
(SMPS). This is due to the requirement of a high bandwidth current sensing circuit that
significantly increases the power consumption and reduces the overall system efficiency
compared to a voltage mode controller [63, 103]. Observer based CPM controllers eliminate the
Appendix A: Peak Current Mode DC-DC
Converter IC with Current Observer
114
need for an explicit current sensing and are therefore suitable for low-power high frequency
SMPS. In [104, 105] an emulated current program mode (ECM) controller is proposed where
the inductor current is artificially reconstructed by integrating the time varying inductor voltage.
This technique, which relies entirely on analog circuitry for reconstructing the inductor current,
does not take advantage of the full capabilities of modern low-voltage digital CMOS processes.
In [106] a digital sensorless current mode (SCM) controller based on a bi-directional delay-line
architecture was presented. The design was implemented on a CPLD device as a proof of
concept. However due to the limited speed and flexibility of the device, the proposed architecture
is only suitable for DC-DC converters operating below 1 MHz. An additional drawback of the
designs proposed in [104-106] is that no calibration circuit was implemented in order to
eliminate mismatches between the actual and observed inductor current slopes. In general this is
Vg
+_
P[2]P[1]P[0]
N[2]N[1]N[0]
Sense
FET
Segmented Power-Stage
VDD_PWR
Gate Driver
C
Lo
ad
L = 400nH
+
_vout(t)
Digital
compensator
e[n]ADC
ic[n]_pi
Mixed-Signal
Current Observer
st_pulse
Ts
vout(t)Vg
CNProgrammable
Dead-time
td [n]
c1[t]
c2[t]
Ibias
Calibration Circuit
Vx Vdsense
pw
rDw
n
cmp_cl
k
Calibration
Controller
st_cal
cmp
_out
clk
cal[n]
Nonlinear
Ct
ic[n]
Scan Chain
PC
Interface
ON CHIP
Vref
Figure A.1: Architecture of mixed-signal ECM controller
115
an inherent disadvantage of ECM techniques. The mismatches grow over multiple switching
cycles due to the integral nature of the ECM controller, and eventually saturate the ECM causing
stability problems. Therefore any implementation of ECM controller requires a calibration circuit
for proper operation. In this Appendix, a mixed-signal ECM integrated circuit (IC) [55] is
presented that consists of a current observer, a calibration circuit and integrated power-stage as
shown in Figure A.1. The main feature of this work is a simple and power efficient CPM
controller that is capable of operating with an integrated dc-dc converter switching at 10 MHz.
The proposed architecture eliminates the need for a high gain-bandwidth sensing circuit and
therefore is suitable for integration with the latest CMOS technologies. The current observer
provides an instantaneous mapping of the inductor current in the digital domain. Since the
observed current, iobs, and controller reference ic[n] are both digital, the high speed analog
comparator is also eliminated. Additionally a novel calibration circuit is introduced to mitigate
the mismatches between observed and actual inductor current slopes.
A.2. Mixed Signal Current Observer Module
A key block of mixed-signal ECM IC is the current observer module as shown in Figure A.1.
This section discusses the design of the current observer and its key building blocks and also
explains its operation as illustrated in Figure A.2.
A.2.1. Hybrid Bi-Directional Delay-Line-Counter Architecture
The current observer architecture is essentially a mixed-signal equivalent of the analog ECM
controller [104, 105]. The observer module shown in Figure A.3 consists of a delay bias control
block and a hybrid bi-directional delay-line-counter architecture that maps the instantaneous
inductor current.
116
The schematic of the bi-directional delay element used in the observer delay-line is also shown
in Figure A.3. Similar to voltage mode digital pulse-width modulator (DPWM) architectures [48,
80, 81, 107], a hybrid combination of delay-line and counter is used in the design of the current
observer. The hybrid structure reduces the total number of delay cells required to map the entire
range of the instantaneous inductor current, significantly decreasing the power consumption and
area of the current observer. The operation of the current observer is as follows: Upon start-up, a
pulse, st_pulse, is injected in the delay-line. The pulse propagates in the forward (FW/BW, DIR
= 1) direction with a propagation delay, td1, which is inversely proportional to the slope of rising
inductor current:
A.1
When the pulse reaches the last delay-cell it clocks and increments the counter as demonstrated
in Figure A.3. The pulse continues to wrap around the delay-line until the counter output is
equal to ic<9:6> and the pulse reaches the delay cell selected by the 6 LSB bits of ic[n], ic<5:0>.
At this point the reset pulse goes high and the direction of the pulse in the hybrid delay-line-
counter structure is reversed (FW/BW, DIR = 0). Subsequently, the pulse propagates in the
backward direction with a propagation delay td2 that is inversely proportional to the slope of
falling inductor current:
A.2
The propagation delay in the backward direction is tunable using the 5-bit calibration signal
which is used for adjusting the slope ratios. The dynamic range of the hybrid delay-line defines
the range of inductor current mapping form iLmin to iLmax. The quantization interval of iL(t) is
hence given by
117
iobsm1 m2
ic[n] ic[n+1]
reset
Δt
CN
RS_CLK
Figure A.2: Simplified operation of current observer module
vout (t)
Cn
DL[n-1]
st_pulse
2j to 1 MUX
Counter
Digital Comparator
SR Latch
FW/BW
ic[n]
Delay Bias
Control
Vg
Vctrl
DIR
MU
X_O
UT
ic<j-1:0>
ic<N-1:j>
clk
_cp
m
Cn
FWst
BW
stF
Wrs
BWrs
DL
DL
Vc FW/BW
FWst
BW
stF
Wrs
BWrs
DL
DL
Vc FW/BW
FWst
BW
stF
Wrs
BWrs
DL
DL
Vc FW/BW
FWst
BW
stF
Wrs
BWrs
DL
DL
Vc FW/BW
FWstB
Wst
FW
rsBWrs
DL
DL
Vc FW/BW
BWrs
FW
FW
FWst BWst
BW
BW
FWrsVctrl
DLDL
Bi-Directional Logic Current Starved Delay Cell
Figure A.3: Architecture of the mixed-signal current observer
118
A.3
A.2.2. Delay Bias Control Block
The delay bias control block shown in Figure A.4 sets the propagation delay of the pulse in both
directions proportional to the inductor current slopes m1and m2. The circuit is a modified version
of the architecture used in [106]. The transistor Mcs mirrors currents Im1 and Im2 to the current
starved delay element of Figure A.3, when the current observer operates in forward and
backward direction, respectively. A combination of level-shifters and wide-swing current mirrors
Adjustable
Mirror
CAL[4:0]
Vbm2
Vbm1
Vbcas
Vbcas
Vbm2
Vbm1
Analog
Switch
DIR
Vb
Vbcas
Vctrl
DL_ADJ
[2:0]
Vg
Vg
Vg
Vg
vout(t)
Vg
RR
RR
Im1
Im2
V/I Conv
Level Shift
Mcs
Current Starved
Cell Mirror
Figure A.4: Delay bias control block
119
are used to create offset-free V/I converters that generate Im1 and Im2 as given below:
A.4
A.5
Where K is adjusted by 5-bit calibration code, CAL[4:0]. Therefore for the forward operation of
the current observer shown in Figure A.2, Im1 is mirrored to current starved delay element and
. Similarly for the backward operation . A 3-bit delay
calibration code, DL_ADJ [2:0] is programmed using the scan chain shown in Figure A.1 in
order to compensate for td1 and td2 due to process, voltage and temperature (PVT) variations.
A.2.3. Current Observer Simulation
Transistor-level Spectre simulation of mixed-mode ECM IC of Figure A.1 with power-stage
operating in open voltage loop is shown in Figure A.5. When the load transient occurs at t = 10
µs, ic[n] is also changed to reflect the change in the load current. The operation of current
observer in closed current loop is shown in Figure A.5. An analog version of the observed
current, iobs , is reconstructed in the simulator test-bench based on the delay-line and counter
outputs to simplify comparison with actual inductor current iL. When the RS_CLK goes high at
the beginning of the switching period, the main switch turns on and the pulse propagates in the
forward direction with propagation speed proportional to m1. When the observed current, iobs
reaches the current command ic[n], the direction of the pulse reverses. As shown in Figure A.5
the current observer provides an instantaneous mapping of the inductor current in both directions
with power-stage running at 10 MHz.
120
As discussed before, if the current observer is not calibrated periodically, the ratio of observer
slopes defined by the ratio of propagation delays td2/td1 , will differ from the ideal inductor
current slope ratio m1/m2. In this case as the controller tries to regulate the output voltage by
adjusting ic[n], the observer saturates due to its limited dynamic range causing stability problems.
This situation is demonstrated in the simulation waveforms of Figure A.6. The CAL[4:0] is
selected such that the observer slope ratio is different from the actual inductor current slope ratio.
The converter initially operates in open loop. When the loop is closed at tcl, iobs gradually
saturates to zero as the error between iL(t) and iobs grows with each cycle and the output voltage
starts to oscillate. In this case the observer incorrectly predicts that the inductor current is
RS_CLK
Load_tric[n]
Counter <3:0>
Sa
mp
le D
ela
y-L
ine
o
utp
uts
CN
Vx
iobs
FWD BWDVx
m1m2
100ns
ic[n]
Mapped Inductor Current
IL
Figure A.5: Open loop simulation of current observer with integrated power stage. When the load
transient occurs ic[n] also changes
121
discontinuous. Under this condition the controller does not operate in current-mode and the
current observer module behaves as a DPWM.
A.3. Calibrating The Observer Slopes
Various sources contribute to the mismatch between the reconstructed and actual inductor
current slopes. The most important factor is the non-linearity of the voltage to delay conversion
within the hybrid delay-line. Additionally inductor parasitic introduces non idealities in the
actual inductor current waveform that are not mapped onto the observed current. Propagation
delays due to gate drivers, Rdson variations and other power-stage related non-idealities also
contribute to errors in the observed inductor current. If the ideal ratio of m1/m2 is not accurately
implemented by the observer, the error is accumulated every switching cycle. Since the digital
CN
Vx
Vout
IL
Iobs
ic[n]
tcl
Figure A.6: Closed loop Simulation of the current observer where the actual slope ratio is
different from the ideal slope ratio.
122
current observer has a finite range, this will eventually saturate ic[n]. The schematic of the
calibration block proposed in this work and implemented in mixed-signal IC of Figure A.1 is
shown in Figure A.7. To perform calibration, an accurate senseFet is used to periodically
ic[n]
pwrDwn
ΣΔ
modulatorRC
Filter
Vref+
_
Pro
gra
mm
ab
le
Rs
SL[n]
pwrDwn
+
_
cmp_cl
k
P[1] VDD_PWR
c1[t] Vx
VdsenseIbias
pw
rDw
n
cmp_out
Sense FET
Figure A.7: Schematic of calibration circuit
Cn
cmp_CLK
Vref – output of sigma Delta DAC
Vx Vdsense
cmp_out
Change in Vre due to change in ic[n]
Figure A.8: Simulation waveforms of calibration circuit for a step in ic[n] (Converter is
running in open loop with fixed duty)
123
compare the peak observed current with the actual peak inductor current and adjust the observer
slopes until the peaks are equal. The simulation of calibration scheme with a step input in ic[n] is
shown in Figure A.8. A simple sigma-delta DAC [14] converts the ic[n] to an analog voltage that
is fed to a V/I converter. The V/I converter, which does not require high bandwidth analog
circuits, creates a bias current based on the analog representation of ic[n] and tunable resistor
value Rs. This bias current is mirrored to a senseFET that is K times smaller than the PMOS
switch. The voltage drop across the Rdson of senseFET is then compared with Vx when the main
switch turns off using a clocked comparator. Since the sampling point corresponds to the peak
inductor current, this calibration circuit allows adjusting the peak of the observed current with
the actual inductor current as follows: During calibration mode, the current through senseFET
can be represented by
A.6
If this current is smaller than the peak inductor current (IBias < ILp), the voltage drop across
senseFET is smaller compared to the PMOS switch. Therefore the Vdsense is larger than the Vx and
the comparator output is equal to zero. The calibration controller, shown in Figure A.1 then
updates the 5-bit calibration code which changes the propagation delay of the reconstructed
current’sfallingslopem2 such that ic[n] increases. This process continues until the comparator
output becomes one, at which point ILp = IBias. Due to the integral nature of observer controller
the mismatches accumulate over many switching cycles. Therefore the calibration phase needs to
repeat with a minimum frequency to prevent saturation of observer controller. When the
calibration phase is completed all calibration circuits are powered down to reduce the power
consumption of the controller.
124
A.4. Experimental Results
The digital current observer architecture with the proposed calibration mechanism and a
segmented power-stage were fabricated in 0.13µm technology. The chip micrograph is shown in
Figure A.9 and Table A.1 summarizes its main specifications. While the power-stage can operate
above 10 MHz, the current observer is designed for operation at or below 10 MHz. The total
current consumption of the observer block is 210 µA. The sigma-delta modulator in the
calibration circuit was synthesized using Artisan standard cell library. Unfortunately, due to a
flaw in the digital flow of this process, the sigma-delta modulator is not functional in the
fabricated IC. Therefore it was not possible to test the calibration circuit and measure its overall
Table A.1: ECM IC Specifications
Specifications Value Units
CMOS Process 0.13 µm
Area 1 x 2 mm2
Input Voltage 2.5 V
Output Voltage 0.8-1.3 V
Rated Load 350 mA
Filter L,C 400, 2 nH, µF
Switching Frequency , 10 MHz
Ron Pmos , Nmos 0.272 , 0.22 Ω
Supply Analog , Digital 1.2, 2.5 V
Peak Efficiency 87 %
Current Observer consumption 210 uA
Calibration circuit consumption
(simulated)
250 uA
125
Digital SCM and
Calib blocks
Segmented Power Stage
Power Stage
Input Cap
Figure A.9: Die photo of ECM IC, 1 x 2 mm2
power consumption. Consequently, the effectiveness of the proposed calibration technique
requires further investigation. In simulations, the calibration circuit consumes around 250 µA of
current during the calibration phase and nearly zero when powered down. The measured
propagation delay of the hybrid delay-line observer in both forward and reverse directions and
versus different output voltages and calibration codes is shown in Figure A.10. It also
demonstrates the full range of variations in propagation delay based on the highest and lowest
calibration codes.
126
Comparison of ideal steady- state slope ratios with that of the observed current is given in Figure
A.11, for different output voltage and calibration code. In order to demonstrate the operation of
the digital observer controller with integrated power-stage in closed loop and verify the current
loop operation, a simple nonlinear time-optimal controller [65, 68, 86, 108] is used. Compared to
voltage mode, a time-optimal controller can be easily implemented in CPM since only two
values of ic[n] are required for the peak current and new steady state value. Figure A.12 shows
the results of the converter operation with time optimal controller. Before load transient occurs,
the digital observer block is switching the converter at 10 MHz in closed-loop steady-state mode.
Upon receiving the load-transient signal, ic[n] is set to the new calculated peak value. The pulse
then propagates through the hybrid observer over multiple switching cycles, until it reaches the
new current command value. Subsequently, the main switch is turned off and observer is
reconfigured so that the pulse propagates in the reverse direction until it reaches the new steady-
state ic[n] value. At this point the PI controller resumes its operation. The inductor current iL(t) is
reconstructed graphically based on the switching waveform, since there is currently no current
probe with sufficient bandwidth and current capability to properly show the inductor current at
10 MHz. Figure A.12 demonstrates that the system recovers to the new steady-state value in a
single on-off switch operation. Figure A.13 shows the efficiency of the converter running at 10
MHz for various output voltages. As shown the peak efficiency of 87% is achieved with all
segments enabled.
127
Figure A.10: Propagation delays of hybrid delay-line-counter observer
Figure A.11: Ideal steady state slope ratio of inductor current and observed current
0.30
0.32
0.34
0.36
0.38
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
0.62
0.64
0.8 0.9 1 1.1 1.2 1.3 vout
De
lay C
alib
ratio
n R
an
ge
t d(n
s)
0
0.5
1
1.5
2
2.5
0.8 0.9 1 1.1 1.2 1.3
Slo
pe
Calib
ratio
n R
an
ge
Ideal Slope m1/m2
Reconstructed slope m1/m2
vout
m1/m
2
128
RS_CLK
CN
Vx(t)
vout (t)
load_tr150 mA
300 mA
iL (t)
500 ns
icn [n]
Figure A.12: Light to heavy load step response of ECM IC with time-optimal controller.
Ch2: CN, 1V/div. Ch4: Vx , 5V/div. Ch3: vout(t) , 100mV/div
Figure A.13: The efficiency of the converter running 10MHz, Vg = 2.5
30
40
50
60
70
80
90
5 20 60 100 150 200 250 300
Peak ή = 87% vout= 1.3 V
vout= 0.9 V
vout= 1.1 V
Eff
icie
ncy
Iload(mA)
129
References
[1] A. Euromonitor_International. Global Market Insight [Online]. Available:
www.euromonitor.com
[2] J. Lopez, M. Gonzalez, J. C. Viera, and C. Blanco, "Fast-charge in lithium-ion batteries
for portable applications," in Telecommunications Energy Conference, 2004. INTELEC
2004. 26th Annual International, 2004, pp. 19-24.
[3] N. H. E. Weste and D. M. Harris, CMOS VLSI design : a circuits and systems
perspective, 4th ed. Boston: Addison Wesley, 2011.
[4] J.M.Rabaey,A.P.Chandrakasan,andB.Nikolić,Digital integrated circuits : a design
perspective, 2nd ed. Upper Saddle River, N.J.: Prentice Hall, 2003.
[5] J. M. Rabaey, Low power design essentials. New York ; London: Springer, 2009.
[6] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design,"
Solid-State Circuits, IEEE Journal of, vol. 27, pp. 473-484, 1992.
[7] A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital
CMOS circuits," Proceedings of the IEEE, vol. 83, pp. 498-523, 1995.
[8] A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-threshold design for ultra low-
power systems. New York: Springer, 2006.
[9] S. G. Narendra and A. P. Chandrakasan, Leakage in nanometer CMOS technologies. New
York: Springer, 2006.
[10] J. T. Kao, M. Miyazaki, and A. R. Chandrakasan, "A 175-MV multiply-accumulate unit
using an adaptive supply voltage and body bias architecture," Solid-State Circuits, IEEE
Journal of, vol. 37, pp. 1545-1554, 2002.
[11] T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K.
Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, "Variable supply-voltage scheme for
low-power high-speed CMOS digital design," Solid-State Circuits, IEEE Journal of, vol.
33, pp. 454-462, 1998.
[12] N. Mehta and B. Amrutur, "Dynamic Supply and Threshold Voltage Scaling for CMOS
Digital Circuits Using In-Situ Power Monitor," Very Large Scale Integration (VLSI)
Systems, IEEE Transactions on, vol. PP, pp. 1-10, 2011.
[13] M. Miyazaki, G. Ono, and K. Ishibashi, "A 1.2-GIPS/W microprocessor using speed-
adaptive threshold-voltage CMOS with forward bias," Solid-State Circuits, IEEE Journal
of, vol. 37, pp. 210-217, 2002.
[14] D. Markovic, C. C. Wang, L. P. Alarcon, L. Tsung-Te, and J. M. Rabaey, "Ultralow-
Power Design in Near-Threshold Region," Proceedings of the IEEE, vol. 98, pp. 237-
252, 2010.
[15] A. P. Chandrakasan, D. C. Daly, D. F. Finchelstein, J. Kwong, Y. K. Ramadass, M. E.
Sinangil, V. Sze, and N. Verma, "Technologies for Ultradynamic Voltage Scaling,"
Proceedings of the IEEE, vol. 98, pp. 191-214, 2010.
[16] B. H. Calhoun, J. F. Ryan, S. Khanna, M. Putic, and J. Lach, "Flexible Circuits and
Architectures for Ultralow Power," Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
130
[17] Y. K. Ramadass and A. P. Chandrakasan, "Minimum Energy Tracking Loop With
Embedded DC-;DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV
in 65 nm CMOS," Solid-State Circuits, IEEE Journal of, vol. 43, pp. 256-265, 2008.
[18] Y. Ikenaga, M. Nomura, Y. Nakazawa, and Y. Hagihara, "A Circuit for Determining the
Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations,"
Solid-State Circuits, IEEE Journal of, vol. 43, pp. 911-918, 2008.
[19] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara, "Delay
and power monitoring schemes for minimizing power consumption by means of supply
and threshold voltage control in active and standby modes," Solid-State Circuits, IEEE
Journal of, vol. 41, pp. 805-814, 2006.
[20] B. H. Calhoun and A. P. Chandrakasan, "Ultra-dynamic Voltage scaling (UDVS) using
sub-threshold operation and local Voltage dithering," Solid-State Circuits, IEEE Journal
of, vol. 41, pp. 238-245, 2006.
[21] A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a
minimum energy design methodology," Solid-State Circuits, IEEE Journal of, vol. 40,
pp. 310-319, 2005.
[22] B. H. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum
energy operation in subthreshold circuits," Solid-State Circuits, IEEE Journal of, vol. 40,
pp. 1778-1786, 2005.
[23] D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods
for true energy-performance optimization," Solid-State Circuits, IEEE Journal of, vol. 39,
pp. 1282-1293, 2004.
[24] K. Nose and T. Sakurai, "Optimization of VDD and VTH for low-power and high-speed
applications," in Design Automation Conference, 2000. Proceedings of the ASP-DAC
2000. Asia and South Pacific, 2000, pp. 469-474.
[25] M. Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama, and K. Ishibashi, "A 1000-
MIPS microprocessor using speed adaptive threshold-voltage CMOS with forward bias,"
in Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE
International, 2000, pp. 420-421, 475.
[26] R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling
for low power CMOS," Solid-State Circuits, IEEE Journal of, vol. 32, pp. 1210-1216,
1997.
[27] T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M.
Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V,
150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable
threshold-voltage (VT) scheme," Solid-State Circuits, IEEE Journal of, vol. 31, pp. 1770-
1779, 1996.
[28] S. Bandyopadhyay, Y. K. Ramadass, and A. P. Chandrakasan, "20 uA to 100 mA DC-DC
Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS,"
Solid-State Circuits, IEEE Journal of, vol. 46, pp. 2807-2820, 2011.
[29] T. Burd, T. Pering, A. Stratakos, and R. Brodersen, "A dynamic voltage scaled
microprocessor system," in Solid-State Circuits Conference, 2000. Digest of Technical
Papers. ISSCC. 2000 IEEE International, 2000, pp. 294-295, 466.
131
[30] A. J. Stratakos, "High-efficiency low-voltage DC-DC conversion for portable
applications," Ph D in Engineering--Electrical Engineering and Computer Sciences,
University of California, Berkeley, 1998.
[31] R. McGowen, C. A. Poirier, C. Bostak, J. Ignowski, M. Millican, W. H. Parks, and S.
Naffziger, "Power and temperature control on a 90-nm Itanium family processor," Solid-
State Circuits, IEEE Journal of, vol. 41, pp. 229-237, 2006.
[32] K. Wonyoung, D. Brooks, and W. Gu-Yeon, "A Fully-Integrated 3-Level DC-DC
Converter for Nanosecond-Scale DVFS," Solid-State Circuits, IEEE Journal of, vol. 47,
pp. 206-219, 2012.
[33] Z. Chen and M. Dongsheng, "A 10-MHz Green-Mode Automatic Reconfigurable
Switching Converter for DVS-Enabled VLSI Systems," Solid-State Circuits, IEEE
Journal of, vol. 46, pp. 1464-1477, 2011.
[34] L. Yu-Huei, W. Shih-Jung, Y. Yao-Yi, Z. Kuo-Lin, C. Po-Fung, H. Chun-Yu, K. Yu-
Zhou, C. Ke-Horng, C. Yi-Kuang, H. Chen-Chih, and L. Ying-Hsi, "A DVS embedded
power management for high efficiency integrated SOC in UWB system," in Solid-State
Circuits Conference, 2009. A-SSCC 2009. IEEE Asian, 2009, pp. 321-324.
[35] A. J. Stratakos, S. R. Sanders, and R. W. Brodersen, "A low-voltage CMOS DC-DC
converter for a portable battery-operated system," in Power Electronics Specialists
Conference, PESC '94 Record., 25th Annual IEEE, 1994, pp. 619-626 vol.1.
[36] G. Gammie, A. Wang, H. Mair, R. Lagerquist, C. Minh, P. Royannez, S. Gururajarao,
and K. Uming, "SmartReflex Power and Performance Management Technologies for 90
nm, 65 nm, and 45 nm Mobile Application Processors," Proceedings of the IEEE, vol.
98, pp. 144-159, 2010.
[37] K. Kyung Ki and K. Yong-Bin, "A Novel Adaptive Design Methodology for Minimum
Leakage Power Considering PVT Variations on Nanoscale VLSI Systems," Very Large
Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, pp. 517-528, 2009.
[38] S. Narendra, A. Keshavarzi, B. A. Bloechel, S. Borkar, and V. De, "Forward body bias
for microprocessors in 130-nm technology generation and beyond," Solid-State Circuits,
IEEE Journal of, vol. 38, pp. 696-701, 2003.
[39] K. Roy, "Leakage power reduction in low-voltage CMOS designs," in Electronics,
Circuits and Systems, 1998 IEEE International Conference on, 1998, pp. 167-173 vol.2.
[40] A. Keshavarzi, K. Roy, and C. F. Hawkins, "Intrinsic leakage in low power deep
submicron CMOS ICs," in Test Conference, 1997. Proceedings., International, 1997, pp.
146-155.
[41] X. Zhou, K. Y. Lim, and D. Lim, "A simple and unambiguous definition of threshold
voltage and its implications in deep-submicron MOS device modeling," Electron
Devices, IEEE Transactions on, vol. 46, pp. 807-809, 1999.
[42] S. Musunuri and P. L. Chapman, "Improvement of light-load efficiency using width-
switching scheme for CMOS transistors," Power Electronics Letters, IEEE, vol. 3, pp.
105-110, 2005.
[43] A. Parayandeh, P. Chu, and A. Prodic, "Digitally Controlled Low-Power DC-DC
Converter with Instantaneous On-Line Efficiency Optimization," in Applied Power
Electronics Conference and Exposition, 2009. APEC 2009. Twenty-Fourth Annual IEEE,
2009, pp. 159-163.
132
[44] O. Trescases, N. Wai Tung, H. Nishio, M. Edo, and T. Kawashima, "A Digitally
Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized
Efficiency," in Power Semiconductor Devices and IC's, 2006. ISPSD 2006. IEEE
International Symposium on, 2006, pp. 1-4.
[45] A. V. Peterchev and S. R. Sanders, "Digital Multimode Buck Converter Control With
Loss-Minimizing Synchronous Rectifier Adaptation," Power Electronics, IEEE
Transactions on, vol. 21, pp. 1588-1599, 2006.
[46] V. Yousefzadeh and D. Maksimovic, "Sensorless optimization of dead times in DC-DC
converters with synchronous rectifiers," Power Electronics, IEEE Transactions on, vol.
21, pp. 994-1002, 2006.
[47] X. Jinwen, A. V. Peterchev, Z. Jianhui, and S. R. Sanders, "A 4A quiescent-current
dual-mode digitally controlled buck converter IC for cellular phone applications," Solid-
State Circuits, IEEE Journal of, vol. 39, pp. 2342-2348, 2004.
[48] N. Rahman, A. Parayandeh, W. Kun, and A. Prodic, "Multimode digital SMPS controller
IC for low-power management," in Circuits and Systems, 2006. ISCAS 2006.
Proceedings. 2006 IEEE International Symposium on, 2006, p. 4 pp.
[49] B. Sahu and G. A. Rincon-Mora, "An Accurate, Low-Voltage, CMOS Switching Power
Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control," Circuits
and Systems I: Regular Papers, IEEE Transactions on, vol. 54, pp. 312-321, 2007.
[50] V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Low-voltage-swing
monolithic dc-dc conversion," Circuits and Systems II: Express Briefs, IEEE
Transactions on, vol. 51, pp. 241-248, 2004.
[51] M. D. Mulligan, B. Broach, and T. H. Lee, "A constant-frequency method for improving
light-load efficiency in synchronous buck converters," Power Electronics Letters, IEEE,
vol. 3, pp. 24-29, 2005.
[52] A. Parayandeh and A. Prodic, "Digitally controlled low-power DC-DC converter with
segmented output stage and gate charge based instantaneous efficiency optimization," in
Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE, 2009, pp. 3870-
3875.
[53] O. Trescases, Prodic, x, A., and N. Wai Tung, "Digitally Controlled Current-Mode DC-
DC Converter IC," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.
58, pp. 219-231, 2011.
[54] R. . rickson and D. Maksimo ić, Fundamentals of power electronics, 2nd ed.
Norwell, Mass.: Kluwer Academic, 2001.
[55] A. Parayandeh, O. Trescases, and A. Prodic, "10 MHz peak current mode dc-dc converter
IC with calibrated current observer," in Applied Power Electronics Conference and
Exposition (APEC), 2011 Twenty-Sixth Annual IEEE, 2011, pp. 897-903.
[56] A. Parayandeh, B. Mahdavikkhah, S. M. Ahsanuzzaman, A. Radic, and A. Prodic, "A 10
MHz mixed-signal CPM controlled DC-DC converter IC with novel gate swing circuit
and instantaneous efficiency optimization," in Energy Conversion Congress and
Exposition (ECCE), 2011 IEEE, 2011, pp. 1229-1235.
[57] D. Mengmeng, L. Hoi, and L. Jin, "A 5-MHz 91% Peak-Power-Efficiency Buck
Regulator With Auto-Selectable Peak- and Valley-Current Control," Solid-State Circuits,
IEEE Journal of, vol. 46, pp. 1928-1939, 2011.
133
[58] Z. Hayashi, Y. Katayama, M. Edo, and H. Nishio, "High-efficiency dc-dc converter chip
size module with integrated soft ferrite," Magnetics, IEEE Transactions on, vol. 39, pp.
3068-3072, 2003.
[59] O. Trescases, "Integrated power-supplies for portable applications," Thesis (Ph D ),
University of Toronto, 2007., 2007.
[60] B. J. Baliga, "Power semiconductor device figure of merit for high-frequency
applications," Electron Device Letters, IEEE, vol. 10, pp. 455-457, 1989.
[61] O. Trescases, Z. Lukic, N. Wai Tung, and A. Prodic, "A low-power mixed-signal current-
mode DC-DC converter using a one-bit DAC," in Applied Power Electronics
Conference and Exposition, 2006. APEC '06. Twenty-First Annual IEEE, 2006, p. 5 pp.
[62] A. Parayandeh and A. Prodic, "Programmable Analog-to-Digital Converter for Low-
Power DC-;DC SMPS," Power Electronics, IEEE Transactions on, vol. 23, pp. 500-505,
2008.
[63] L. Cheung Fai and P. K. T. Mok, "A monolithic current-mode CMOS DC-DC converter
with on-chip current-sensing technique," Solid-State Circuits, IEEE Journal of, vol. 39,
pp. 3-14, 2004.
[64] R. Gregorian, Introduction to CMOS OP-AMPs and comparators. New York: Wiley,
1999.
[65] Y. Wen and O. Trescases, "DC-DC Converter with Digital Adaptive Slope Control in
Auxiliary Phase for Optimal Transient Response and Improved Efficiency," Power
Electronics, IEEE Transactions on, vol. PP, pp. 1-1, 2011.
[66] L. Yan-Fei, E. Meyer, and L. Xiaodong, "Recent Developments in Digital Control
Strategies for DC/DC Switching Power Converters," Power Electronics, IEEE
Transactions on, vol. 24, pp. 2567-2577, 2009.
[67] V. Yousefzadeh, A. Babazadeh, B. Ramachandran, E. Alarcon, L. Pao, and D.
Maksimovic, "Proximate Time-Optimal Digital Control for Synchronous Buck
DC–DC Converters," Power Electronics, IEEE Transactions on, vol. 23, pp.
2018-2026, 2008.
[68] Z. Zhenyu and A. Prodic, "Continuous-Time Digital Controller for High-Frequency DC-
DC Converters," Power Electronics, IEEE Transactions on, vol. 23, pp. 564-573, 2008.
[69] D. Johns and K. W. Martin, Analog integrated circuit design. New York: John Wiley &
Sons, 1997.
[70] A. Parayandeh, "Programmable application-specific ADC for digitally controlled switch-
mode power supplies," Thesis (M A Sc ), University of Toronto, 2006., 2006.
[71] P. Givelin, M. Bafleur, E. Tournier, T. Laopoulos, and S. Siskos, "Application of a
CMOS current mode approach to on-chip current sensing in smart power circuits,"
Circuits, Devices and Systems, IEE Proceedings -, vol. 142, pp. 357-363, 1995.
[72] D. Mengmeng and L. Hoi, "A 2.5MHz, 97%-accuracy on-chip current sensor with
dynamically-biased shunt feedback for current-mode switching DC-DC converters," in
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, 2008, pp.
3274-3277.
[73] B. Razavi, Design of analog CMOS integrated circuits. Boston, MA: McGraw-Hill,
2001.
[74] M. Maymandi-Nejad and M. Sachdev, "A monotonic digitally controlled delay element,"
Solid-State Circuits, IEEE Journal of, vol. 40, pp. 2212-2219, 2005.
134
[75] C. Man Pun and P. Mok, "Fully integrated digital controller IC for buck converter with a
differential-sensing ADC," in Electron Devices and Solid-State Circuits, 2008. EDSSC
2008. IEEE International Conference on, 2008, pp. 1-4.
[76] O. Trescases, G. Wei, A. Prodic, W. T. Ng, K. Takasuka, T. Sugimoto, and H. Nishio, "A
digital predictive on-line energy optimization scheme for dc-dc converters," in Applied
Power Electronics Conference, APEC 2007 - Twenty Second Annual IEEE, 2007, pp.
557-562.
[77] H. Zhang, V. George, and J. M. Rabaey, "Low-swing on-chip signaling techniques:
effectiveness and robustness," Very Large Scale Integration (VLSI) Systems, IEEE
Transactions on, vol. 8, pp. 264-272, 2000.
[78] P. R. Gray, P.J .Hurst, S.H Lewis, R.G .Meyer, Analysis and design of analog integrated
circuits, 5th ed. Chichester: John Wiley, 2009.
[79] Z. Lukic, N. Rahman, and A. Prodic, "Multibit PWM Digital Controller IC for DC-
DC Converters Operating at Switching Frequencies Beyond 10 MHz," Power
Electronics, IEEE Transactions on, vol. 22, pp. 1693-1707, 2007.
[80] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, "High-frequency digital PWM
controller IC for DC-DC converters," Power Electronics, IEEE Transactions on, vol. 18,
pp. 438-446, 2003.
[81] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, "Digital pulse width modulator
architectures," in Power Electronics Specialists Conference, 2004. PESC 04. 2004 IEEE
35th Annual, 2004, pp. 4689-4695 Vol.6.
[82] M. Darwish, J. Huang, M. Liu, M. S. Shekar, R. Williams, and M. Cornell, "Scaling
issues in lateral power MOSFETs," in Power Semiconductor Devices and ICs, 1998.
ISPSD 98. Proceedings of the 10th International Symposium on, 1998, pp. 329-332.
[83] L. Sang, K. Wing Hung, K. Ka Chun, and C. Mansun, "Realization of Compact
MOSFET Structure by Waffle-Layout," in Solid-State Device Research Conference,
2001. Proceeding of the 31st European, 2001, pp. 119-122.
[84] A. Yoo, M. Chang, O. Trescases, and N. Wai Tung, "High Performance Low-Voltage
Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25μ Standard
CMOS Process," in Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th
International Symposium on, 2008, pp. 95-98.
[85] A. Hastings, The art of analog layout, 2nd ed. Upper Saddle River, NJ: Pearson/Prentice
Hall, 2006.
[86] A. Babazadeh, L. Corradini, and D. Maksimovic, "Near time-optimal transient response
in DC-DC buck converters taking into account the inductor current limit," in Energy
Conversion Congress and Exposition, 2009. ECCE 2009. IEEE, 2009, pp. 3328-3335.
[87] E. Meyer, W. Dong, J. Liang, and L. Yan-Fei, "Digital charge balance controller with an
auxiliary circuit for superior unloading transient performance of Buck converters," in
Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth
Annual IEEE, 2010, pp. 124-131.
[88] A. Radic, Z. Lukic, A. Prodic, and R. de Nie, "Minimum deviation digital controller IC
for single and two phase dc-dc switch-mode power supplies," in Applied Power
Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE, 2010,
pp. 1-6.
[89] B. Razavi, Principles of data conversion system design. New York: IEEE Press, 1995.
135
[90] A. Parayandeh, A. Stupar, and A. Prodic, "Programmable Digital Controller for Multi-
Output DC-DC Converters with a Time-Shared Inductor," in Power Electronics
Specialists Conference, 2006. PESC '06. 37th IEEE, 2006, pp. 1-6.
[91] M. D. Ercegovac and T. Lang, Digital arithmetic. San Francisco, CA
Oxford: Morgan Kaufmann ;
Elsevier Science, 2004.
[92] A. Bakker and J. H. Huijsing, "Micropower CMOS temperature sensor with digital
output," Solid-State Circuits, IEEE Journal of, vol. 31, pp. 933-937, 1996.
[93] C. Poki, C. Chun-Chi, T. Chin-Chung, and L. Wen-Fu, "A time-to-digital-converter-
based CMOS smart temperature sensor," Solid-State Circuits, IEEE Journal of, vol. 40,
pp. 1642-1648, 2005.
[94] H. Mostafa, M. Anis, and M. Elmasry, "On-Chip Process Variations Compensation Using
an Analog Adaptive Body Bias (A-ABB)," Very Large Scale Integration (VLSI) Systems,
IEEE Transactions on, vol. PP, pp. 1-5, 2011.
[95] M. Sumita, S. Sakiyama, M. Kinoshita, Y. Araki, Y. Ikeda, and K. Fukuoka, "Mixed
body bias techniques with fixed Vthand Ids generation circuits," Solid-State Circuits, IEEE
Journal of, vol. 40, pp. 60-66, 2005.
[96] T. Kehl, "Hardware self-tuning and circuit performance monitoring," in Computer
Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE
International Conference on, 1993, pp. 188-192.
[97] S. Das, D. Roberts, L. Seokwoo, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T.
Mudge, "A self-tuning DVS processor using delay-error detection and correction," Solid-
State Circuits, IEEE Journal of, vol. 41, pp. 792-804, 2006.
[98] D. Ernst, K. Nam Sung, S. Das, S. Pant, R. Rao, P. Toan, C. Ziesler, D. Blaauw, T.
Austin, K. Flautner, and T. Mudge, "Razor: a low-power pipeline based on circuit-level
timing speculation," in Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual
IEEE/ACM International Symposium on, 2003, pp. 7-18.
[99] S. D. Naffziger, "SAMPLING CHIP ACTIVITY FOR REAL TIME POWER
ESTIMATION," US 2009/0259869 A1, 2009.
[100] S. Bibian and H. Jin, "High performance predictive dead-beat digital controller for DC
power supplies," in Applied Power Electronics Conference and Exposition, 2001. APEC
2001. Sixteenth Annual IEEE, 2001, pp. 67-73 vol.1.
[101] H. Peng and D. Maksimovic, "Digital current-mode controller for DC-DC converters," in
Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth
Annual IEEE, 2005, pp. 899-905 Vol. 2.
[102] O. Trescases, Z. Lukic, N. Wai Tung, and A. Prodic, "A low-power mixed-signal current-
mode DC-DC converter using a one-bit ΔΣ DAC," in Applied Power
Electronics Conference and Exposition, 2006. APEC '06. Twenty-First Annual IEEE,
2006, p. 5 pp.
[103] S. Yuvarajan and L. Wang, "Performance analysis and signal processing in a current
sensing power MOSFET (SENSEFET)," in Industry Applications Society Annual
Meeting, 1991., Conference Record of the 1991 IEEE, 1991, pp. 1445-1450 vol.2.
[104] P. Midya, P. T. Krein, and M. F. Greuel, "Sensorless current mode control-an observer-
based technique for," Power Electronics, IEEE Transactions on, vol. 16, pp. 522-526,
2001.
136
[105] Datasheet, "Simple switcher, 75V, 3A Step-Down Switching Regulator, LM5576,"
EP5388QI ed. National semiconductors., 2010.
[106] O. Trescases, A. Parayandeh, A. Prodic, and N. Wai Tung, "Sensorless Digital Peak
Current Controller for Low-Power DC-DC SMPS Based on a Bi-Directional Delay
Line," in Power Electronics Specialists Conference, 2007. PESC 2007. IEEE, 2007, pp.
1670-1676.
[107] A. P. Dancy and A. P. Chandrakasan, "Ultra low power control circuits for PWM
converters," in Power Electronics Specialists Conference, 1997. PESC '97 Record., 28th
Annual IEEE, 1997, pp. 21-27 vol.1.
[108] J. Alico and A. Prodic, "Multiphase optimal response mixed-signal current-programmed
mode controller," in Applied Power Electronics Conference and Exposition (APEC),
2010 Twenty-Fifth Annual IEEE, 2010, pp. 1113-1118.