Reliability and failure mechanism of copper pillar jointsunder current stressing

Hui-Cai Ma1 • Jing-Dong Guo1 • Jian-Qiang Chen1 • Di Wu1 • Zhi-Quan Liu1 •

Qing-Sheng Zhu1 • Jian Ku Shang1,2 • Li Zhang3 • Hong-Yan Guo3

Received: 7 April 2015 / Accepted: 23 June 2015 / Published online: 3 July 2015

� Springer Science+Business Media New York 2015

Abstract The electromigration (EM) lifetime of copper

pillars were investigated by orthogonal tests. According to

the Black’s mean-time-to-failure equation, the activation

energy and exponent of current density were calculated to

be 0.88 eV and 1.64, respectively. The microstructure

evolution of the joints under current stressing was

observed. It was found that the Sn solder was usually

depleted before the joint failed, which means the joint was

only composed of Cu6Sn5 and Cu3Sn phases as a Cu/

Cu3Sn/Cu6Sn5/Cu3Sn/Cu structure after a period of EM

test. Three failure modes were observed: failure along the

Cu/Cu3Sn interface at the cathode side, failure along the

Cu/Cu3Sn interface at the anode side and brittle fracture

through the IMCs. The percentages of these three failure

modes are 55, 24 and 21 %, respectively. The formation of

Kirkendall voids was suggested to be the key factor for the

EM failure of the Cu pillar joints. Before the Sn solder was

depleted, voids were mainly formed at the Cu6Sn5/Sn

interface at the cathode, which is dominated by the Cu flux

induced by current; while after the Sn solder was depleted,

voids formation is dominated by the chemical diffusion.

1 Introduction

To meet the relentless drive for the miniaturization and

high performance of cheaper, faster, portable, and multi-

features electronic consumer devices, smaller solder bump

interconnects at fine pitch have been adopted for high-

density packaging [1]. Due to its excellent electrical

characteristic and superior heat dissipation capability, Cu

pillar bump was widely used recently in the high density

packaging. The Cu pillar bump structure consists of a

copper cylinder and a solder cap which substitutes the

traditional solder bump. Serving as the support structure

and electrical conductor, Cu pillar structure can provide

fine pitch with superior electric and thermal characteristics

over the conventional solder ball [1–6], and can reduce the

amount of solder required to form interconnect. The solder

cap is usually only about 20–35 lm in height, which means

the IMCs growth and formation of Kirkendall voids will

play a more important role in the reliability of the joints.

Besides, Cu pillar may introduce higher stress than con-

ventional solder joint because Cu is harder than solder

material [3–7]. Thus its lifetime and reliability are expected

to be different from those of the conventional line-to-bump

structures.

It is generally accepted that the common failure mech-

anism of electromigration (EM) in flip chip is the rapid loss

of under bump metallization (UBM) and the interfacial

void formation caused by current crowding effect [8–12].

However, relevant research has confirmed that there is no

current crowding in the copper pillar interconnects and the

dissipation of UMB is not the decisive failure mechanism

any more [13–18]. Instead, void formation and cracking at

Cu/Cu3Sn and Cu6Sn5/solder interfaces became the domi-

nant failure modes under current stressing [13, 14, 17].

Because of the superior heat dissipation capability of

& Jing-Dong Guo

jdguo@imr.ac.cn

& Jian Ku Shang

jkshang@imr.ac.cn

1 Shenyang National Laboratory for Materials Science,

Institute of Metal Research, Chinese Academy of Sciences,

Shenyang 110016, China

2 Department of Materials Science and Engineering, University

of Illinois at Urbana-Champaign, Urbana, IL 61801, USA

3 Jiangyin Changdian Advanced Packaging Co., Ltd,

Jiangyin 214431, China

123

J Mater Sci: Mater Electron (2015) 26:7690–7697

DOI 10.1007/s10854-015-3410-8

copper pillar structure and no current crowding location,

Cu pillar can handle larger current density and experience a

longer lifetime. Several studies have shown that copper

pillar had strong resistance against EM induced failure and

its lifetime was above 720 h under 10 kA cm-2 above

125 �C [13, 14, 16, 17, 19]. Jiang estimated that its mean

time to failure (MTTF) is 2.3 times higher than the con-

ventional line-to-bump interconnects [20, 21]. In addition,

the IMC growth in Cu pillar bump under annealing and

current stressing was also different from that in solder

bumps of line-to-bump structure [14, 16–18, 22–24]. Due

to its longer lifetime and smaller solder bump, the solder

cap will be depleted and totally transformed to Cu6Sn5 and

Cu3Sn during its lifespan, and then Cu6Sn5 phase will

continually transform to Cu3Sn. The total (Cu6Sn5 ?

Cu3Sn) IMC thickness increases linearly with current-

stressing time rather than increasing linearly with the

square root of annealing time on the anode side, which

indicates that the current stressing accelerates the interfa-

cial reaction [25].

Although Cu pillar interconnects have been studied by

many researchers, a detailed study of the lifetime of the

copper pillar will be more necessary and valuable. In this

paper, an EM test platform was set up to explore the life-

time data of Cu pillar bumps. Further studies about the

interfacial reliability were carried out by statistical analysis

of a great number of samples. A finite element modeling

was used to simulate the current density and the stress

distribution. In combination of microstructure evolution

analysis with FEA results, the failure mechanisms of Cu

pillar under current stressing were discussed.

2 Experiments

The flip chip structure was adopted in the present experi-

ment. The dimension of the chip die is 2 mm 9 1 mm 9

0.35 mm with four copper pillars on each die, and the pitch

between adjacent copper pillars is 400 lm. The diameter

and height of the Cu pillar are 160 and 100 lm, respec-

tively. The Sn solder cap is 30 lm in height. The test

substrate employed in EM experiments is 9.2 mm 9

6.4 mm in shape of rectangle and 1 mm in thickness. The

chip die was reflowed with Cu bonding pad on the PCB at

260 �C. The cross-sectional view of an as-assembled Cu

pillar solder joint is shown in Fig. 1.

The samples were electrified with a constant direct-

current (DC) electric current. The electrical resistance of

the sample was monitored in situ by a HIOKI LR8400-21

recorder, and open circuit was set as the failure criterion.

To prevent oxidation, the samples were immersed in an oil

bath during the test. A K-type thermocouple was attached

to Si die surface to monitor the sample temperature. The

EM lifetime of copper pillars were investigated by

orthogonal tests. The condition matrix is shown in Table 1.

For each of the nine test series, 30 samples were tested.

After current stressing, the microstructure of the samples

was examined by scanning electron microscopy (SEM),

and the IMCs were identified by energy dispersive spec-

trometer (EDS).

3 Results and discussions

3.1 Lifetime statistics

Figure 2 shows the typical variation in resistance of the

samples with time at temperature 70 and 90 �C, respec-

tively. It can be seen that the resistance initially experi-

ences a long incubation time with very little resistance

change, and then the resistance increased quickly, leading

to an open circuit in a short time. The temperature variation

of the sample was almost synchronous with the resistance

change, as indicated in Fig. 3. It also experienced a long

incubation time and a sudden rising period. Besides, some

unstable fluctuations, as marked by arrows in Figs. 2 and 3,

appeared in resistance versus time or temperature versus

Fig. 1 Cross-sectional view of an as-assembled Cu pillar solder joint

Table 1 EM test matrixj (kA cm-2) A.T. (�C)

50 70 90

S.T. (�C)

27.4 138 169 186

29.8 160 178 197

32.3 180 190 211

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123

curves, which may be attributed to simultaneous damage

evolution and recovery process in solder joint.

Figure 4 illustrates the Weibull distribution function of

lifetime under various current densities at 50, 70 and

90 �C, respectively. The characteristics lifetime of the

samples based on the Weibull analysis were listed in

Table 2. A MTTF estimation of copper pillar interconnect

was made according to the Black’s equation [26].

MTTF ¼ A1

jmexp

Q

kT

� �

where A is a constant, j is the current density in the solder,

m is an exponent for current density, Q is the activation

energy for EM, k is Boltzmann’s constant, and T is the

average temperature.

The measured MTTF was plotted against temperature

as shown in Fig. 5. From the plots, the activation energy

Q was obtained from calculation as 0. 88 eV. However,

it is hard to keep the same temperature for the samples

in different group because the temperature rise caused by

Joule heating is different for the nine test conditions.

Therefore, the current density exponent cannot be

determined by plotting MTTF against current density. To

solve this question, a numerical analysis method was

introduced in this study to calculate the current density

exponent via Matlab software. By applying the lifetime

data in Black’s equation, the current density exponent

was calculated to be 1.64 for copper pillar interconnect

structure.

3.2 EM reliability

Figure 6 shows the SEM images of a Cu-pillar joint after cur-

rent stressing for different time under 2.74 9 104 A cm-2 and

at 186 �C. After current stressing for 360 h, as shown in

Fig. 6a, it can be seen that most of the Sn solder was consumed.

On the anode side, the thicknesses of Cu3Sn and Cu6Sn5 layers

were 2 and 7 lm, respectively, while on the cathode side, the

thicknesses of Cu3Sn and Cu6Sn5 layers were 0.79 and

0.75 lm, respectively, indicated an obvious polarity effect on

the growth of both Cu3Sn and Cu6Sn5 under current stressing.

Several voids were formed at Cu6Sn5/Sn interface on the

cathode side, which may be attributed to the EM of Sn; a great

number of smaller voids were observed at Cu/Cu3Sn interface

on both sides, and the amount of voids on the cathode is more

than that on the anode side; besides, there almost no voids

observed at Cu3Sn/Cu6Sn5 interface.

Fig. 2 The resistance curve of interconnects

Fig. 3 The temperature of interconnects

Fig. 4 Weibull cumulative distribution

Table 2 Lifetime data of copper pillars

j (kA cm-2) A.T. (�C)

50 �C 70 �C 90 �C

MTTF (h)

27.4 4070 1509 1027

29.8 1770 806 606

32.3 1410 636 156

7692 J Mater Sci: Mater Electron (2015) 26:7690–7697

123

After current stressing for 700 h, as shown in Fig. 6b,

although the joint is still not failed, the Sn solder has

already been depleted. The joint was only composed of

Cu6Sn5 and Cu3Sn phases as a Cu/Cu3Sn/Cu6Sn5/Cu3Sn/

Cu structure, which means IMCs play a key role in its

reliability. The thickness of the Cu6Sn5 phase is 15 lm,

while that of Cu3Sn on the cathode and the anode sides are

4.94 and 5.35 lm, respectively, both increased during the

EM test. At Cu6Sn5/Cu3Sn interface on the cathode side,

the voids were enlarged during the test, some voids were

also observed in the middle of the Cu6Sn5. At Cu/Cu3Sn

interface, the number of voids also increased on both sides,

and some of the voids were already linked up to form a

long crack along the interface.

From our observation on the failed joints, there were

three failure modes for the Cu-pillar joints under current

stressing. (1) Failure took place along the Cu/Cu3Sn

interface at the cathode side, as shown in Fig. 7a. During

the EM test, a great number of Kirkendall voids formed at

Cu3Sn/Cu interface due to the EM effect along with the

voids caused by the chemical diffusion of Cu and Sn,

which may weaken the strength of the interface. Under

thermal stress, cracks will be easily initiated and propa-

gated along the interface and cause the joints to be failed.

According to our statistics, about 55 % of samples failed in

this mode. (2) Failure occurred along the Cu/Cu3Sn inter-

face at the anode side, as shown in Fig. 7b, and about 24 %

of samples failed in this mode. At this side, the Kirkendall

voids were mainly induced by the chemical diffusion of Cu

and Sn. Because the EM effect inhabited the formation of

Kirkendall voids at the anode, the amount of voids at the

anode is less than that at the cathode. Thus the percentage

of samples failed in this mode is much less than mode 1.

Otherwise, almost all the fractures along the Cu/Cu3Sn

interface occurred at the PCB side, which suggested that

the stress in the PCB side is larger than that in the die side.

(3) Brittle fracture occurred through IMCs in copper pil-

lars, as shown in Fig. 8. Due to the EM of the Sn solder

before it was depleted,some large voids formed at the

Cu6Sn5/Sn interface on the cathode side. As the current

stressing continued, these voids grew larger as solder Sn

transformed to Cu6Sn5 phase and even interlinked up to

form macro-cracks along the interface. However, unlike

EM induced failure in conventional solder joint [27], EM

induced voids and macro-cracks in the present case cannot

cover the whole joint area and cause failure individually at

Cu6Sn5/solder Cu6Sn5/solder interface due to the limited

solder. But the mechanical properties will be deteriorated

because of these defects. This feature in combination with

the high thermal stress due to different thermal expansion

coefficients between Cu and the substrate will lead to the

IMC brittle fracture. About 21 % of samples failed in this

mode.

To clarify the mechanism of the failure of joints under

current stressing, FEM method was used to analyze the

current distribution and thermal stress in the joints. As

Fig. 5 Plots of MTTF against 1/kT

Fig. 6 Interfacial morphology before failure occurs. a After 360 h with a current density of 27.4 kA cm-2 at 186 �C, b after 600 h

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shown in Fig. 9a, the average current density in the joint is

3 9 104 A cm-2 and the highest current density is about

5.7 9 105 A cm-2 located on the corner of the Cu pillar

adjacent to the chip, which is far away from the solder cap.

The maximum current density in solder cap is just

3.8 9 104 A cm-2, located on the lower corner adjacent to

Fig. 7 SEM images of the cross-sectioned flip chip joints of Cu pillar bumps with Sn solder bumps. a After 500 h with a current density of

29.8 kA cm-2 at 197 �C, b another Cu pillar with opposite electron flow direction, and c the enlarge view of the interfaces of a, d close-up of b

Fig. 8 Brittle fracture of IMC in copper pillars. a After 870 h with a current density of 29.8 kA cm-2 at 197 �C, b another Cu pillar with

opposite electron flow direction, c the enlarge view of the interfaces of a, and d close-up of b

7694 J Mater Sci: Mater Electron (2015) 26:7690–7697

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the PCB board as indicated in Fig. 9b. Thus it is suggested

that the current crowding effect was not severe to be the

main factor for the failure of the joints under current

stressing. Figure 10 shows the thermal shear stress distri-

bution in solder cap. The maximum stress point is located

at the brim of solder cap adjacent to the PCB board, which

can be attributed to the large difference of the thermal

expansion coefficients between solder and substrate. This is

well agreed with the experimental results that almost all the

failure occurred at the PCB side.

From the failure modes given above, the formation of

Kirkendall voids is the key factor for the EM failure of the Cu

pillar joints. To analyze the IMC growth and Kirkendall void

formation under EM, the vacancy flux is taken into account

in diffusion analysis. For each phase of the Cu–Sn system,

vacancy transport is considered in the following relationship:

Jv þ JCu þ JSn ¼ 0 ð1Þ

where Jv, JCu and JSn denote the diffusional flux of

vacancy, Cu and Sn atoms, respectively. And the fluxes of

atom Cu and Sn comprise the atomic flux due to chemical

diffusion and current.

For chemical diffusion induced flux, it can be expressed

as:

JchemCu ¼ �DCu

oCCu

oxð2Þ

JchemSn ¼ �DSn

oCSn

ox¼ DSn

oCCu

oxð3Þ

Minho has analyzed the vacancy flow in the solder joints

under annealing, and suggested that the difference between

the diffusion rates of Cu and Sn results in the formation of

atomic vacancies at the Cu/Cu3Sn and Cu6Sn5/Sn interface

due to the Kirkendall effect [28]. While under current

stressing, directional atomic flux induced by electronic

wind force should be considered. The current induced

atomic flux can be expressed as:

JEMCu ¼ DCu

CCu

kTZ�Cueqj ¼ CCuDCu/Cuj ð4Þ

JEMSn ¼ DSn

CSn

kTZ�Sneqj ¼ CSnDSn/Snj ð5Þ

where / ¼ ðZ�Sn

�kTÞeq is the effective inter-diffusion EM

coefficient.

Figure 11a illustrated the mass fluxes in solder joints

undergoing EM before the Sn solder was depleted. Because

the fast diffusion of Cu in Sn, the Cu flux induced by current

predominated in voids formation, which enhanced the for-

mation of voids at the cathode and retard that at the anode.

Thus a great number of Kirkendall voids formed at the Cu6

Sn5/Sn interface at the cathode. Besides, voids formed also at

the Cu/Cu3Sn interface, but the number of voids at the cath-

ode was more than that at the anode. In addition, the direc-

tional Cu flux also caused the polarity effect of IMC growth.

Figure 12 illustrated the mass fluxes after the Sn solder

was depleted. Because the diffusivity of Cu and Sn in

Fig. 9 Current density

distribution: a in copper pillar,

b in solder Sn cap

Fig. 10 Thermal shear stress distribution in solder cap

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Cu6Sn5 and Cu3Sn is much lower than that in Sn, as shown

in Table 3 [29–35], the directional atomic flux caused by

EM in Cu6Sn5 phase is much lower. As shown in Table 4,

under a current stress of 30 kA cm-2, the EM-driven

copper atomic flux in Sn phase is 46.8 9 1016 atom s-1

m-2, which is 3 and 15.6 time of that in Cu3Sn and Cu6Sn5

phase, respectively; Sn atomic flux in Sn phase is also

larger than that in Cu3Sn and Cu6Sn5 phases. In addition,

due to the higher strength of Cu6Sn5, back stress effect in

the Cu6Sn5 is also stronger than that in the Sn solder.

According to Gan’s work [36], the EM critical length of

Cu6Sn5 was calculated to be 16 lm, while the critical

length of Sn is \5.4 lm under 30 kA cm-2 [37, 38]. In

such condition, the formation of Kirkendall voids is dom-

inated by chemical diffusion, and consequently a great

number of Kirkendall voids are accumulated at Cu/Cu3Sn

interface on both cathode and anode sides. And the polar

growth also gradually slows down as Cu6Sn5 turned into

Cu3Sn because of the gradually enlarged back stress, as

shown in Fig. 6b.

4 Conclusion

Electromigration tests were conducted to study the lifetime

of Cu pillar joints under orthogonal test conditions. The

activation energy and exponent of current density were

calculated to be 0.88 eV and 1.64 based on the Black’s

equation. Three failure modes were observed for the joints

under current stressing: failure along the Cu/Cu3Sn inter-

face at the cathode side, failure along the Cu/Cu3Sn

interface at the anode side and brittle fracture through

IMCs in the joints. The percentages of these three failure

modes are 55, 24 and 21 %, respectively. The formation of

Kirkendall voids was suggested to be the key factor for the

EM failure of the Cu pillar joints. Before the Sn solder was

depleted, voids formed mainly at the Cu6Sn5/Sn interface

at the cathode, which was dominated by the Cu flux

induced by current and this process played a role in brittle

fracture; while after the Sn solder was depleted, voids

Fig. 11 Mass fluxes in solder connects undergoing EM

Fig. 12 Mass fluxes in IMCs connects undergoing EM

Table 3 Diffusion coefficients,

effective charge number and

resistivity

Phase Diffusant Z* D (m2 s-1) q (X m-1)

Cu Cu

Sn

2–7 [29, 30]

0.6–3.25 [31]

5.83 9 10-31 [32]

1.67 9 10-28 [32]

1.7 9 10-8

Cu3Sn Cu

Sn

26.5 [33]

23.6 [33]

1.47 9 10-17 [37]

5.09 9 10-19 [34]

8.9 9 10-8

Cu6Sn5 Cu

Sn

26 [33]

36 [33]

3.23 9 10-17 [34]

8.81 9 10-17 [34]

17.5 9 10-8

Sn Cu 2 [35] 3.74 9 10-11 [32] 11 9 10-8

Table 4 EM atomic fluxes in each phase under current stressing of

30 kA cm-2

Atomic flux (atom s-1 m-2) Cathode

Cu3Sn Cu6Sn5 Sn

JEMCu

15 3 46.8

JEMSn

1.4 15.5 20.2

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formation was dominated by the chemical diffusion and a

great number of Kirkendall voids were accumulated at Cu/

Cu3Sn interfaces at both cathode and anode sides, which

mainly accounted for the failure along the Cu/Cu3Sn

interface.

Acknowledgments This work was supported by the Natural Sci-

ence Foundation of China, Grant Nos. 51171191 and 51101161, the

National Basic Research Program of China, Grant No. 2010CB63

1006, the Major National Science and Technology Program of China,

Grant No. 2011ZX02602, National Key Scientific Instrument and

Equipment Development Projects of China, Grant No. 2013YQ

120355, and Natural Science Foundation of Liaoning Province, Grant

No. 2013020015.

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