The reliability of copper pillar under the coupling of thermalcycling and electric current stressing

Hui-Cai Ma1 • Jing-Dong Guo1 • Jian-Qiang Chen1 • Di Wu1 • Zhi-Quan Liu1 •

Qing-Sheng Zhu1 • Li Zhang2 • Hong-Yan Guo2

Received: 22 February 2016 / Accepted: 21 May 2016 / Published online: 27 May 2016

� Springer Science+Business Media New York 2016

Abstract Cu pillar samples were subject to the thermal

cycling test along with current stressing to investigate its

reliability issues under the coupling effect. Analysis of

scanning electron microscopy (SEM) pictures of Cu pillar

bumps showed the evolution of interfacial microstructure.

The finite element analysis pointed out the probable site of

cracks initiation based on the strain and stress distribution.

Three failure modes, electromigration (EM) induced cracks

at Cu6Sn5/Sn interface on cathode, cracking of Cu/Cu3Sn

interface on anode side, and fatigue-creep induced cracks

in Sn solder, took place at the interfaces of copper pillar

interconnect under electric current and thermal cycling. In

addition, EM induced failure increased while fatigue-creep

failure decreased with electric current density. The failure

mechanisms were analyzed from stress concentration,

interfacial morphology and voids formation respects.

1 Introduction

The solder bumps, in the microelectronic devices, play a

significant role in both mechanical support and electrical

connection. The coupling effect of thermo-mechanical

stresses and electric current yields new reliability issues. Its

corresponding failure mechanisms were usually investi-

gated separately for thermo-mechanical stresses or electric

current stress. The coupling effect of these two factors,

however, was rarely under consideration. Under the driving

of higher requirements for multifunctional as well as

portable devices, the miniaturization of solder bumps is

prevailing today. With the decreasing of solder bumps size

and its pitch, dramatic increase occurs in thermo-mechan-

ical stresses [1] and electric current density [2]. Under this

circumstance, the coupling effect is becoming increasingly

critical and indispensable to the reliability of solder joints.

The failure mechanisms for electromigration (EM) and

thermal cycling have already been thoroughly studied

separately, but these mechanisms may not account for the

coupling condition. Under the coupling of thermal cycling

and electric current, both EM and thermal stress induced

creep-fatigue process may cause failure of the bumps

[3–7]. Moreover, EM and creep-fatigue controlling process

usually entangles with each other when the solder joints

undergo electric current and temperature cycling. The

electric current induced void flow weakens the strength of

the solder [8], accelerates the creep strain rate and

decreases the activation energy. Simultaneously, thermo-

mechanical stress also affects EM failure: the tensile stress

enhances EM failure whereas the compressive stress

retards it [9]. In our previous work [10], the lifetime of the

bumps under the coupled condition was much less than that

of thermal cycling and EM, which suggests that the failure

mechanisms under the coupled condition may be different

and more complicated. Zuo et al. and Ma et al. [11, 12]

studied the coupling effect of thermal cycling and high

electric current density on Sn58Bi and SnAgCu (SAC)

solders. The results revealed that cracks had more impact

on the resistance increase than phase segregation. Cracks

were inclined to form and propagate along the interface

between intermetallic compound layers and solder matrix

in SAC solder. In SnBi solder, however, grain boundaries

& Jing-Dong Guo

jdguo@imr.ac.cn

1 Shenyang National Laboratory for Materials Science,

Institute of Metal Research, Chinese Academy of Sciences,

Shenyang 110016, China

2 Jiangyin Changdian Advanced Packaging Co., Ltd.,

Jiangyin 214431, China

123

J Mater Sci: Mater Electron (2016) 27:9748–9754

DOI 10.1007/s10854-016-5038-8

were regarded as the nucleation sites for micro cracks.

They also reported that high electric current density alle-

viated the deterioration of the solder at the beginning stage

of coupling stressing through Joule heating effect. Laurila

et al. [13]. investigated the failure mechanism of solder

interconnects in power cycling tests, but they suggested

that the failure modes of coupling tests were the same with

that of thermal cycling tests. Although the results are

fruitful, the failure mechanism of solder bumps under

coupling effect is still unclear.

Thus, the present study attempts to probe failure

mechanisms of solder bumps under thermal cycling com-

bined with electric current stressing using copper pillar

with Sn cap structure. Specifically, the effects of electric

current density, temperature, stress and IMCs on the atomic

migration and failure process will be carried on.

2 Experimental

The configuration and dimensions of the cross-section of

flip-chip solder joint samples with a daisy-chained circuit

are illustrated in Fig. 1. The pitch between adjacent pillars

is 400 lm. The heights of copper pillar and Sn solder are

100 and 30 lm, respectively. And their diameters are all

160 lm. The thickness of Cu trace on the chip is 10 lm and

on PCB side, 30 lm.

Multi-field coupling failure tests were conducted using a

series of samples. The electric current densities of 12.4,

17.4, 19.9 and 22.4 kA/cm2 corresponding to constant DC

electric current stressing of 2.5, 3.5, 4.0 and 4.5 A,

respectively, were applied on the samples. For comparison,

tests without electric current, viz., only thermal cycling

tests were also conducted as reference group. Based on the

JEDEC standards, the accelerated temperature cycling

condition was provided by Temperature Cycling Test

Chamber. Figure 2 shows the thermal profile of the

accelerated thermal cycling. A sound cycle would take

50 min. The dwell time at high and low extreme temper-

atures was 10 min, and the heating and cooling rates were

11 �C/min. The resistance and temperature data were

monitored in situ. After multi-field stressing, the interfaces

between solder and substrate were examined by scanning

electron microscopy (SEM).

To understand the crack extension process of copper

pillar joint with voided interface due to EM enhanced

Kirkendall effect, the stress and strain were studied with a

finite element (FE) model of a voided IMC layer with

different thicknesses. Using ANSYS14.0 as the finite ele-

ment analysis tool, Sn cap was meshed using the

VISCO107 elements, whereas all the other package mate-

rials were meshed using SOLID45 elements. To authenti-

cally reflect the nature of creep and fatigue behavior under

thermal cycling, herein, the unified viscoplastic law was

used to describe the material properties in FEM modelling.

Anand constitutive model was applied to solder material

and its detailed data was given is our previous work

[10, 14]. The rest materials are assumed to be linear elastic

and their material data was presented in Table 1. The finite

element analysis contained five heating/cooling cycles

since the stress and strain on joints generally stabilized

after the third cycle during thermal cycling.

3 Results

According to our previous work [10], after experiencing a

long resistance-hardly-increase period which accounts

most part of lifespan of copper pillar interconnects under

thermal cycling and electric current, the resistance of most

samples rose abruptly to an open circuit. Thus, it is

Fig. 1 Cross-sectional view of an as-assembled Cu pillar solder joint

Fig. 2 Accelerated thermal cycle with load steps

Table 1 Material properties

Materials CTE (ppm/k) Poisson’s ratio E (GPa)

Si 2.6 0.28 162

Cu 16.5 0.33 85.56

Sn 23.5 0.2 42

FR4 16 0.28 27.9

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reasonable to set open failure as the failure criterion for

each sample. For each set of test, the lifetime data of

experiment under the coupled condition were analyzed

statistically by using a two-parameter Weibull distribution

(Fig. 3) [15, 16]. Its scale parameter, g, and shape

parameter, b were used to determine the mean time. The

lifetime data are presented in the third column of Table 2

[10]. From the table, the lifetime drops quickly with the

increase of electric current density. This trend reveals EM

accelerated failure of Cu pillar bump in the coupling tests.

After statistically analyzing the morphologies of cross-

sectioned samples with SEM, three failure modes were

discovered in copper pillar interconnects under the coupled

condition. The first failure mode was EM induced failure

on cathode side. The second was cracking of Cu/Cu3Sn

interface on anode side. And the third was fatigue-creep

failure of solder. The proportion of each kind of failure

mode for each set is tabulated in Table 3. From the table, it

can be noted that EM induced failure increased from 31 to

44 % with electric current density increased from 12.4 to

22.4 kA/cm2, on the other hand, fatigue-creep failure

decreased from 56 to 19 % with electric current density

increased from 12.4 to 22.4 kA/cm2. The failure mecha-

nism shifted from fatigue-creep dominated failure to EM

dominated failure when electric current density increases

from 12.4 to 22.4 kA/cm2.

The first failure mode, EM-induced cracks on the cath-

ode, is presented in Fig. 4. As the arrows indicated, PCB

side is the cathode in Fig. 4a, whereas copper pillar side is

the cathode in Fig. 4b. Cracks appeared on the cathode side

in both Fig. 4a, b. Specifically, cracks appeared at Cu6Sn5/

Sn and Cu3Sn/Cu6Sn5 interfaces. The polarity effect, which

is commonly observed in conventional solder bumps, also

existed in copper pillar interconnects during electric cur-

rent stressing. Cu6Sn5 and Cu3Sn IMC layers formed on

both sides in both joints. Samples failed in such mode

usually have a shorter lifespan.

The second failure mode is cracking of Cu/Cu3Sn

interface on the anode side, as indicated in Fig. 5. This

kind of failure is the unique failure mode for copper pillar

interconnects rather than conventional solder ball inter-

connects. Because the limited Sn cap transformed into

intermetallic compound layers on the anode due to the

polarity effect of EM in copper pillar interconnects. In

addition, this brittle fracture mode often occurred on the

PCB substrate side.

Figure 6 shows third failure mode, that is, fatigue crack

forms in solder. In this case, though the polarity effect also

existed and Kirdendall voids appeared at the interface and

in Cu3Sn phase, cracks were found in solder section instead

of the interface that discussed above. From the picture, Sn

is unexhausted when crack took place. This failure mode is

similar with that of interconnect experiencing only thermal

cycling, but its lifetime has been significantly reduced. The

foremost reason is that EM effect greatly increases the

density of voids and internal defects such as micro cracks

in the solder. As a consequence, the strength of solder

decreased and the failure process was accelerated under the

alternating thermal stress. This failure mode mainly

appears in multi-field tests with low electric current den-

sity, 17.4 kA/cm2 in this study.

4 Discussion

For the first failure mode, cracking of the Cu6Sn5/Sn

interface owes to EM induced voids, fatiguing the serrated

interface and the microcracks in Cu6Sn5 phase. First of all,

due to the effect of electric current, the in-migrating atomic

flux cannot counterbalance the emigrating Cu flux atFig. 3 The Weibull cumulative distribution curve

Table 2 Lifetime statistics of Cu pillar bumps [10]

J (kA/cm2) T (�C) b N (cycles)

0 -40–125 13,390

12.4 -29–154 0.93 5800

17.4 -15–163 1.02 2158

19.9 1–176 1.22 599

22.4 15–190 1.30 118

Table 3 Statistics of each failure mode under different coupling tests

j (kA/cm2) EM (%) Anode crack (%) Fatigue-creep (%)

12.4 31 12 56

17.4 40 20 40

19.9 42 21 37

22.4 44 37 19

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Cu6Sn5/Sn interface on the cathode side. Therefore, an

increasing number of vacancies accumulated at this inter-

face and gradually condensed into voids with time of EM.

Noticeably, when failure occurred, Sn was unexhausted

(Fig. 4). This differs from EM induced failure of copper

pillar subjecting to only electric current, in which cracks

Fig. 4 Cracks formation on the cathode side a cathode side on the PCB side, b cathode side on the copper pillar side, c close-up of a, d close-up

of b

Fig. 5 Cracking of Cu/Cu3Sn interface a fracture on anode side, b close-up view of a

Fig. 6 Failure in solder

a initiation site of crack,

b extension of crack, c open

failure in solder

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form at Cu/Cu3Sn interface and all Sn cap has been

transformed to IMCs [17]. Moreover, the lifetime of copper

pillar under the coupled condition is shorter than that under

electric current [10]. This disparity suggests that copper

pillar interconnect is more vulnerable to the coupled con-

dition than single field (electric current stressing). In detail,

in addition to the EM effect on the cathode interface,

thermal cycling also has an effect on the reliability of this

interface under the coupled condition. First, the fatigue

crack accelerates the cracking process of Cu6Sn5/Sn

interface. During thermal cycling, due to the mismatch of

coefficient of thermal expansion between Cu6Sn5(aCu6Sn5 = 16.3 9 10-6) and Sn (aSn = 23.5 9 10-6), a

larger stress builds up at Cu6Sn5/Sn interface (Fig. 8).

Furthermore, the serrated morphology of this interface

provides an easy path for fatigue crack propagation. Thus,

fatigue-creep crack extends along the serrated interface

between Sn and Cu6Sn5 scallops, as marked by the red

wavy line in Fig. 7a. The second factor accelerating the

cracking process of this interface is microcracks in Cu6Sn5,

as shown in Fig. 7b. This kind of microcracks also existed

in samples stressing only with thermal cycling. Thus, the

final failure results from EM induced voids, cracks in

Cu6Sn5 scallops and fatigue crack propagation among these

voids and micro cracks. This failure mode dominates the

lifetime of Cu pillar when the electric current density is

high because high electric current density means more

voids and thicker Cu6Sn5.

Furthermore, this kind of crack is mode I cracking

judging from the stress and strain analysis as indicated in

Fig. 8a. The y-stress distribution shows that the maximum

stress site locates at Cu6Sn5/Sn interface regardless of the

IMC thickness from our calculation. In addition to ther-

momechanical loading, this stress is also attributed to

volume change induced by IMC formation. The y-stress,

perpendicular to the interface, drives the crack to propagate

as a mode I crack. On the other hand, the stress may also

cause Cu6Sn5 cracking as shown in Fig. 7b, which aggra-

vates the mode I cracking propagation.

Meanwhile, accompanying with the IMC decomposition

and atoms emigration at interfaces on cathode, atoms

immigrate and IMC forms at interfaces on anode side.

Especially, the formation of Cu3Sn is always accompanied

by a great number of Kirkendall voids formation at Cu/

Cu3Sn interface, which degrades the strength of intercon-

nect. The mechanism and formation process of these voids

can be found in our previous study [17]. Further, these

voids connects into a crack and propagates along Cu/Cu3Sn

interface, as indicated in Fig. 6, under the larger stress

which can be derived from the result of finite element

simulation, as shown in Fig. 8a. This failure mode is

always combined with the first failure modes because the

large amount of IMC formation on the anode side is always

at the cost of severe IMC decomposition and atoms

migration on cathode side.

The mechanism of cracking of solder Sn is stress con-

centration induced crack rather than recrystallization-as-

sisted crack nucleation and propagation. The

microstructure was inspected by using EBSD technique

after tests, as shown in Fig. 9. It is found that the

microstructure of the interconnection, especially near the

cracks, had not changed after thermal cycling. It is different

from the failure mode of conventional solder balls in which

the cracks extended along the grain boundaries caused by

recrystallization. Tin grains near the cracks still remain the

same morphology and there are no recrystallization grains.

In fact, the crack initiates from the edge of the solder

section, as shown in Fig. 6a, which may be attribute to the

larger stress and strain at this site, as indicated in stress

distribution map of FEA result (Fig. 8b, c). Then it prop-

agates gradually with the number of cycles in solder till

open failure occurs across solder interconnect. This kind of

failure is the mix of mode I and mode II cracking. As

shown in Fig. 6c, there is a relative horizontal displace-

ment between site A and site B which are supposed to be

one site before cracking. The shear stress, as shown in

Fig. 8b, drives the horizontal displacement in solder. At the

same time, the solder also subjects to a perpendicular stress

so that mode I cracking process also contribute to the final

open failure in solder.

These three failure modes exist in each group with

different proportions as listed in Table 2. In each group,

Fig. 7 a Fatigue crack at Cu6Sn5/Sn interface, b microcracks in Cu6Sn5 scallops

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according to our statistics, the time to failure of the first and

second failure modes is usually shorter than that of the

third failure mode. The orientation of Sn solder may

account for the difference of time to failure. Under current

stressing, the growth of the interfacial intermetallic com-

pound was Sn grain orientation dependant [18]. When the

current flow aligns to the c-axes of most Sn grains it causes

a severe polarity effect, i.e., thicker Cu6Sn5 layer on anode

(Fig. 9a, b). On cathode side, however, IMCs decompose

quickly so that the first failure mode occurs. On the other

hand, along with thicker layers of IMCs formation on

anode, large number of Kirkendall voids form and coa-

lescence at Cu/Cu3Sn interface so that the second mode of

failure occurs. But when the c-axes of the Sn grains deviate

from the current direction, as illustrated in Fig. 9c, d, the

polarity effect became less pronounced, as well as EM

induced failure. Creep-fatigue, instead, dominates the

failure process in such orientated samples. Thus, this kind

of samples is inclined to have longer lifetime and fail in the

third mode.

Thus, the failure modes are more complicated for the

coupled condition, which comprises failure characteristics

of thermal cycling and EM. EM leads to increasing the

density of voids in solder, reducing the strength of solder

joints and accelerating the solder joint failure process under

thermal cycling. The introduction of cyclic thermal stress,

on the other hand, also deteriorates the interface subjecting

to EM. Furthermore, the microstructure of solder joints

also affects its reliability.

5 Conclusion

Failure mechanisms in copper pillar bumps during multi-

field coupling tests are examined. The result shows that

there are three failure mechanisms: (a) EM induced cracks

formation on the cathode side under high electric current

density, (b) cracking of Cu/Cu3Sn interface on anode side,

and (c) fatigue crack formation in the solder tending to

appear under low electric current density. The first and

second failure modes are mainly caused by EM which is

related to the electric current density and the orientation of

solder Sn. The third failure mode is attributed to fatigue-

creep of solder Sn with crack initiating at the middle brim

of solder Sn part because of stress concentration. In each

test set, these failure modes mingle the characteristics of

EM and thermal cycling together with different propor-

tions. Thermal stress and potential failure sites of copper

pillar interconnect are investigated by FEA. The results

reveal that the maximum y-stress locates at the interface

Fig. 8 FEA simulated deformation and stress a y-stress, b xz-stress, c xz-strain

Fig. 9 EBSD map of solder Sn with a crack a SEM picture of Sn

grains with c-axes long current direction, b EBSD map of a, c SEM

picture of Sn grains with c-axes deviate from current direction,

d EBSD map of c

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between Cu pad on the PCB side and solder Sn, the max-

imum shear stress, whereas, locates at the middle brim of

solder Sn. These places are potential to crack under cou-

pling of thermal cycling and electric current tests.

Acknowledgments This work was supported by the Natural Science

Foundation of China, Grant Nos. 51171191 and 51471180, the Major

National Science and Technology Program of China, Grant No.

2011ZX02602.

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