Conclusions 1. The a-c output voltage waveshape must approach that of a sine wave.

switchings per half-cycle do not produce excessive losses.

This paper has presented techniques for generating an alternating, notched, voltage waveform, using controlled recti­fiers or transistors, that nullify the two lowest harmonics otherwise present in the load voltage. The 2-harmonic reduc­tion techniques presented here are ap­plicable in those cases where the d-c to a-c inverter must fulfill the following requirements.

2. The a-c power requirement of the system is such that the use of paralleled inverters or "stepped-wave" inverters is not justified.3

3. The voltage control range required to maintain a constant value of load voltage during input voltage variations is several to one or less.

4. The fundamental frequency is low enough so that the added semiconductor

References 1. A SILICON CONTROLLED RECTIFIER INVERTER WITH IMPROVED COMMUTATION, W. McMurray, D. P. Shattuck. AIEE Transactions, pt. I {Com­munication and Electronics), vol. 80, Nov. 1961, pp. 531-42. 2. CONTROLLED RECTIFIER MANUAL (book), F· W. Gutzwilier, Editor. General Electric Com­pany, Auburn, N. Y., second edition, 1961. 3. STATIC INVERTER WITH NEUTRALIZATION OF HARMONICS, A. Kernick, J. L. Roof, T. M. Heinrich. AIEE Transactions, pt. I I (Applications and Indus­try), vol. 81, May 1962. pp. 59-68.

Read—Write Nondestructive Read-out

Memory

D. L. WILEY

THIS PAPER describes a read-write nondestructive read-out (NDRO) fer-

rite-core memory system with a 1.5-mc (megacycle) read cycle and a 160-kc write cycle. The evolution of this sys­tem (Fig. 1) was a result of demand on memories by higher speed data processing.

NDRO increases system speed by eliminating the write segment of a de­structive read cycle. In the majority of computer programs, more than 90% of total memory operation time is devoted to read-restore operations, and hence, faster computer operations are possible when NDRO techniques are utilized.

The word-organized random-access sys­tem has a storage capacity of 512 15-bit words and stores information in a non­volatile mode; therefore, words or bits will not be altered in case of power failure. All active circuit elements are solid-state devices.

Nondestructive Reading

Nondestructive reading1 is achieved by the interaction of flux paths within the multiaperture core; this takes place when a disturb flux φΌ causes a transient change

A paper recommended by the IEEE Nonlinear Magnetics Committee and approved by the IEEE Technical Operations Committee for presentation at the IEEE International Conference on Non­linear Magnetics, Washington, D. C , April 17-19, 1963. Manuscript submitted January 7, 1963; made available for printing September 18, 1963. R. L. WILEY and R. D. PIERCE were both with the Air Arm Division, Westinghouse Electric Corpora­tion, Baltimore, Md., when the paper was written. The authors would like to thank E. R. Higgins, R. E. Noll, W. F. Eiseman, and all those who contributed to this memory development program.

R. D. PIERCE MEMBER

in the residual flux éR. The polarity of the output signal resulting from this transient flux change denotes the state of the core. Upon removal of the disturb flux, the residual flux resumes the original éR state, resulting in a flux change in the opposite direction from the original tran­sient flux change (Fig. 2).

NDRO 'MULTIAPERTURE CORE MEMORY SYSTEM

Fig. 1 (above). Pro­totype memory system

The internal action of the core during a nondestructive read-out is shown graph­ically in Fig. 3. By passing a current through the major aperture, the core is saturated in the direction shown by the residual flux d>R. The read pulse, passing through the minor aperture, then creates a disturb flux which is superimposed on the residual flux in Fig. 3(B). Since the flux changes in legs A and B are the same as those in legs C and D, respectively, reference will be made to legs A and B only. The disturb flux attempts to drive leg A further into the saturated state, and therefore, the flux change ΑφΑ is very small. In leg B, however, the flux change is much greater since φΏ opposes the residual flux in the leg. Fig. 3(C) shows the resultant flux in the core during the existence of the disturb flux. The tran­sient flux change is in the direction shown by Δφ, where Δφ is proportional to ΔφΒ— ΑΦΑ. The output signal is induced on the sense line by the time rate of change of the transient flux άφ.

The output signal is dependent only on the direction of the residual flux φΒ. Two examples readily demonstrate this: If the cores are rotated 180 degrees about the Z axis (Fig. 3), neither the residual flux φΗ nor the transient flux Δφ changes direction. Only the direction of the

? 400

MILLIAMPS

Fig. 2 (right). Read-current pulse and read­

out signals

READ CURRENT PULSE

"ZERO"

H - I U S E C -

~ \

/

/

\

^

^

w\

140 MILLIVOLTS

378 Wiley, Pierce—Read-Write Nondestructive Read-out Memory J U L Y 1964

(A)

Fig. 3 (above). Flux interaction in the mul tiaperture core

y^ Fig. 4 (above). Read-out signal degradation

Fig. 5 (right). Hysteresis curve

Organization

Fig. 6 shows the two distinct cycles in this word-organized system, a write cycle and a read cycle. The circuitry associated with each is isolated to achieve optimum speed. The system obtains read- and write-cycle times of 0.67 ^sec (microsecond) and 6.0 ^sec, respectively; a timing diagram is shown in Fig. 7.

The memory stack is designed on a frame basis; each frame consists of two digit planes of 64 15-bit words, and eight modular replaceable frames are required to form the 512-word stack. The digit planes are orthogonal in structure (Fig. 8). Along the word axis, the read and write lines thread through the 15 bits of the word; the read line passes through the minor apertures, while the write line goes through the major aperture. Along the bit axis, the sense and digit lines are con­tained within a copper tube. The sense

disturb flux 4>D is changed; the output is therefore independent of read-current pulse polarity. If the cores are not rotated 180 degrees from their original orientation about the X-axis, the disturb flux direction is not changed. However, the direction of the residual flux is changed, and a change in the transient flux and the output signal results. Since the transient flux and the residual flux are always in opposite directions, the polarity of the output signal is easily detected (Fig. 2).

For approximately the first ten read-current pulses, some flux is switched in an irreversible mode because of the de­magnetization effect in leg B. After the initial read pulses, the flux is com­pletely switched in a reversible mode. Design considerations of the read-current pulse parameters have eliminated major amplitude variations in the output sig­nals. The output pulse width, however, decreases as a result of the irreversible flux switched (Fig. 4). Domain wall motion occurs in leg B during the exist­ence of the read-current pulse; leg A, on the other hand, is not affected. This can be explained by examining the hysteresis properties of the core in Fig. 5. Orig­inally, leg B is at point 1 ; then, upon ap­plication and removal of the read pulse, some flux is irreversibly switched and leg B returns to a point with slightly less residual flux. After several read pulses are applied, the residual flux φη decreases to point 2. Then leg B on each successive read pulse follows the reversible path: point 1, point a, point 2.

/ 8

SWITCH DRIVERS

/ 16

READ DRIVERS

z7

15 SENSE

AMPLIFIERS

16 OUTPUT

LOAD SHARING MATRIX

2 0 MATRIX DRIVERS

4 READ

SWITCHES

/ / 4

SWITCH DRIVERS

y ^

, Fig. 6. System block diagram

J U L Y 1964 Wiley, Pierce—Read-Write Nondestructive Read-out Memory 379

WRITE CYCLE INITIATE

LOAD SHARING MATRIX OUTPUT

DIGIT DRIVE PULSE

SIGNAL ON SENSE LINE

READ CYCLE INITIATE

READ DRIVE PULSE

SENSE AMPLIFIER GATE

STROBE

OUTPUT REGISTER

h 1/ "S \

WRITE CYCLE

Γ

r

READ CYCLE

1 Λ Π il [\

Fig. 7. Timing dia­gram

1 2 3 4 5 TIME (MICROSECONDS)

6 6.67

line is electrostatically shielded from read drive lines by the copper housing, and the digit line is included in the tube in order to simplify the core stack con­struction.

A signal cancellation technique is em­ployed so that the effect of the digit drive does not disable the sense amplifier. Cancellation is employed on a frame basis and all words in a frame are cleared to the

same state. Half the frames are cleared to a " 1 , " a positive signal into the input of the sense amplifier, and the other half to a "0," a negative signal. When writing is performed, the bit is driven into the "set" state, that is, opposite the "clear" state.

In this system, words are selected by a coincident selection technique (Fig. 6) in­stead of individual word drivers. Each word is uniquely chosen by a combina­tion of one of the 32 switches and one of the 16 drivers. After selection, data can flow into or out of the accessed word, de­pending on the cycle performed. Each cycle operates the coincident switch and driver selection. Both the unipolar read switch and the bipolar write switch con­tain conventional transistor-core cir­cuitry. The driver for the read cycle is a current driver with controlled rise time; therefore, the read-out signal is uniform from word to word. The driver for the write cycle consists of a load shar­ing matrix which provides high current bipolar drive pulses.

The coincident selection technique used in the memory access requires diodes

COPPER TUBE

DIGIT (i) SENSE

380 Wileyt Pierce—Read-Write Nondestructive Read-out Memory

Fig. 8. Memory frame organization

J U L Y 1964

Fig. 9. LSM current pulse

to prevent multiple current paths. The read cycle needs a diode for each word, while the bipolar write cycle requires two diodes per word. Thus, the two distinct cycles require three diodes per word to restrict the current paths (Fig. 8).

T H E WRITE CYCLE

Since reading is nondestructive, the write operation must be preceded by a clear operation that saturates the memory core into a known state; the write cycle is thus divided into two separate opera­tions.

A positive clear pulse and a negative half-write pulse are driven along the word axis, while a digit is driven along the bit axis. The clear pulse drives each bit of selected word into the clear state; the coincidence of the half-write pulse and the digit pulse is necessary to drive a core into the set state. The digit driver associated with each bit in which the set state is to be

stored must be activated, and the bits in which the digit drivers are not activated remain in the clear state.

A load sharing matrix (LSM) is used to generate the asymmetrical bipolar clear and half-write current pulses. High peak-power bipolar outputs can be achieved with low power unipolar input drivers. Preceding designs2 have shown that, with a sharing matrix, 4w inputs can provide (4w—1) outputs. Each unipolar output is uniquely selected by half the available inputs, and for any output, the matrix configuration dictates which combination of 2w input lines should be selected to provide a positive output pulse. If the input lines are comple­mented and, through this, the previously unselected input lines are selected, a negative output pulse is obtained; hence, bipolar output pulses are realized by com­plementing the input lines. These lines are threaded through each output trans­former in a discrete manner so that signals on the lines cancel each other in all but the selected transformer, where all signals are in the same direction. The total output power of the LSM is the sum of the input power of the input drivers.

The LSM has 20 inputs, and 16 of the 19 available outputs are utilized. Each input line requires one unipolar current driver. Current drivers supply 300-ma

(milliampere) pulses during the clear operation and 140-ma pulses during the write operation; the resultant pulse from the load sharing matrix (Fig. 9) is 800 and 400 ma for the clear and write pulses, respectively.

The reasons for choosing an LSM for the memory are twofold: first, the LSM achieves a higher reliability than is possi­ble with individual drivers, and second, the write driver circuit complexity is re­duced from expensive high power bipolar drivers to conventional low power uni­polar drivers.

T H E READ CYCLE

Since reading is done in a nondestruc­tive mode, the read cycle is performed in one operation. A read pulse with an amplitude of 300 ma and a rise time of 0.1 /xsec is driven along the word axis, reading the contents of the selected word. A nominal output signal amplitude with these drive pulse conditions is 25 mv (millivolts). (The controlled rise time of the read pulse maintains amplitude uniformity in the read-out signals.)

The characteristic impedance of the sense line is decreased and its propaga­tion delay is increased by the copper tube; these parameters change because the copper tube increases the shunt capaci­tance of the line without changing the series inductance. The propagation de-

PREAMPLIFIER

INPUT i NO.

INPUT-N0.2

Fig. 10. Sense amplifier

JULY 1964 Wiley, Pierce—Read- Write Nondestructive Read-out Memory 381

P J I ~Ί 0

H Π f

J L

V 4« 1.0 USEC H

Fig. 1 1 . Read initiate pulse and sense amplifier output

lay of the sense line is limited by the peak­ing time of the read-out signals in the memory core. If the delay is greater than the peaking time of the read-out, the output signal will vary from word to word. A word located at the middle of the sense line yields a normal amplitude output, but a double-peaked output with one-half normal amplitude will result from a word located at either end of the sense line. The time between the peaks is equal to the total sense line propaga­tion delay. The time for the read-out signal to peak is 100 nsec (nanoseconds) ; the maximum delay is specified at 80 nsec so that the output signal has only one

IN 1936, a simplification of the magnet­ization curve that was intended to

facilitate the explanation of the pre-saturation phenomena led to the develop­ment of a d-c instrument transformer hav­ing genuine current-transformer char­acteristics. It was found that the as­sumption of a rectangular hysteresis loop for the combined effect of d-c and a-c mag­netization would fulfill the condition of strict equality of the primary and second­ary magnetomotive forces (mmf) of the transformer, at least periodically. This

A paper recommended by the IEEE Nonlinear Mag­netics Committee and approved by the IEEE Tech­nical Operations Committee for presentation at the IEEE International Conference on Nonlinear Mag­netics Washington, D. C , April 17-19, 1963. Man­uscript submitted December 17, 1962; made avail­able for printing December 5, 1963. W. KRÄMER is with the Darmstadt Institute of Technology, Darmstadt, Germany.

peak. In order not to exceed this maxi­mum delay, each sense line is divided into two sections.

The sense amplifier must detect and amplify a 25-mv read-out signal and yet be passive and unaffected by the 1.25-volt write signal. This amplifier (Fig. 10) consists of two preamplifiers, one for each half of the sense line, plus a diode gate, an a-c amplifier, and a detection circuit. The preamplifiers are linear differential amplifiers whose gain is controlled by the diode gate, which is closed quiescently, lowering the preamplifier gain below one. Write signals and digit noise coupled to the sense lines are attenuated by the pre­amplifier when the gate is closed. During the read cycle, however, the diode gate is opened and the preamplifier gain is 10. The read-out signal is thus amplified by the preamplifier and the a-c amplifier. The output is detected by coincidence of the read-out and a 100-nsec strobe pulse. Coincidence signifies a " 1 , " and lack of coincidence signifies a "0." The final output (Fig. 11) is noise-free and sets the output register 0.40 ^sec after the read initiate pulse.

applied to all types of current trans­ducer circuits.

It turned out, for instance, that the presaturated reactor with twin cores and opposed a-c series windings will generate a sinusoidal alternating flux, only by drawing a magnetizing current of rectan­gular waveshape that compensates the primary d-c mmf for the duration of each half period; this will result in an alter­nating desaturation of the cores. By rectifying the rectangular current half-cycle waves, an uninterrupted secondary direct current is obtained whose magni­tude, like that of the a-c transformer, is calculated from the primary current and the turns ratio.

The rectangular magnetization charac­teristic requires a perfect compensation of the mmf s for a current half-cycle wave.

Conclusion

This memory achieves high-speed per­formance in computer applications where the ratio of information retrieval to the insertion of new information is greater than 10. Nondestructive retrieval per­mits a very fast read cycle. With a read cycle of 0.67 Msec, a write cycle of 6 μ8ε^ and a ratio of 10, the average cycle time is 1.15 /isec. As the ratio becomes much greater than 10, the average memory cycle time approaches the read-cycle time.

The test data taken on multiaperture cores have shown that reading can be performed more than 1012 times without any degradation in read-out signal after the tenth read-out.

References 1. A N E W NONDESTRUCTIVE READ FOR MAG­NETIC CORES, R. Thorensen, W. R. Arsenault. Western Joint Computer Conference. Los Angeles, Calif., Institute of Radio Engineers, Mar. 1955, pp. 111-16. 2. A LOAD SHARING MATRIX SWITCH, G. Con-stantine, Sr. Journal of Research and Develop­ment, International Business Machines Corp. New York, N. Y., vol. 3, Apr. 1959, pp. 194-96.

This condition is independent of the magnitude of the alternating voltage and the voltage drop in the secondary d-c circuit; i.e., it is independent of the transformer load. It is also independent of the frequency of the auxiliary voltage. Any fluctuation of the primary direct cur­rent must also be superimposed on the rectangular current half-cycle wave of the alternating current in order to main­tain perfect compensation. Thus, the secondary direct current will also repre­sent correctly a fluctuation of the primary current; changes of the primary current are transferred practically without delay.

These considerations led to the con­clusion that an ideal d-c instrument trans­former could be constructed by using an ideal core material; from the standpoint of measurement technology, this would be the equivalent of the a-c instrument transformer.

The high-permeability nickel-iron (Ni-Fe) alloys already known at that time permitted a satisfactory approximation of the magnetization characteristic to the shape demanded theoretically at high magnetizing forces; even the first d-c instrument transformer for 30,000 amp (amperes), built by Allgemeine Elektrici-täts-Gesellschaft, Berlin, Germany (AEG), in 1936, attained a class accuracy

Development of the D-C Instrument

Transformer for the Precision

Measurement of Highest Direct Currents

W. KRAMER

382 Krämer—D-C Instrument Transformer for Precision Measurement of Currents JULY 1964