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Polarization Induced 2DEG in AlGaN/GaN HEMTs: On the origin, DC and transient characterization
by
Ramakrishna Vetury
Committee
Dr. James Ibbetson Prof. Evelyn Hu
Prof. Robert YorkProf. Umesh Mishra
Acknowledgements
Professors Umesh Mishra, Robert York, Evelyn Hu, Dr. James Ibbetson
Prof. Steve DenBaars, Prof. Jim Speck
Mishra and York Groups: Lee, Peter, James, Gia, Naiqain, Dr. Wu, Ching Hui, Primit, Prashant, Rob U, Rob C, Dan, DJ, Anand, Sten, Tim, Can, Likun, Huili, Ilan, Dario..Amit, Jane, Vicki, Bruce, Paolo, PC Jia, Erich, Troy, Pete, Padmini, Thai, Jim ..
Dr. Stacia Keller, Dr.Yulia SmorchkovaNaiqain Zhang, Darron Young, Chris Elsass, Ben Heying, Hugues Marchand, Paul Fini, Dave Kapolnek
Bob Hill and Jack Whaley and everybody in the clean roomUCSB Nitride Community
Cathy and Lee
Anil, Minu, Sri, Doli, Smitha, Karthik, Shri, OttoSridevi & Rohit Joshi
ONR AFOSR
Outline
1. Non-Idealities in GaN HEMTs,traps in GaN buffer, AlGaN dislocations
2. The free surface of AlGaNSurface potential, Polarization, Origin of 2DEG
3. Current CollapseVirtual gate, Transient characterization,Passivation
Obtaining power from the device. Biasing and load line for maximum power output
VBREAKDOWN
IMAX
IDS
VDSVKNEE
Bias Point
A
B
Q
What makes a good GaN HEMT?
- - - - - - - - - - - - - - - -- - -
SG
D
Substrate
GaN Buffer
AlGaN
ns
IMAX . (VBREAKDOWN – VKNEE)
8Max Power =
VBREAKDOWN
IMAX
IDS
VDSVKNEE
BIAS POINT
A
B
Q
What makes a good GaN HEMT?
- - - - - - - - - - - - - - - -- - -
SG
D
Substrate
GaN Buffer
AlGaN
ns
Maximize I Maximize ns, µ
Maximize ns Maximize PSP, PPEMaximize Al mole fraction without strain relaxation
Maximize fτ Minimize effective gate length, Minimize Lg and gate length extension
Maximize µ Minimize dislocations, smooth interface
ns . µIMAX α
Choose the high power RF device..
Non –Idealities in GaN HEMTs
2V/div
Predicted Output Power (W/mm/ VDS bias)
3.15 /24 3.50 /25 1.50 /20 1.30 /2070
0 m
A/m
m
Choose the high power RF device..
Measured Output Power (W/mm/ VDS bias)
1.06 /24 0.30 /20 0.76 /203.24 /25
What limits output power?
Non –Idealities in GaN HEMTs
2V/div
Predicted Output Power (W/mm/ VDS bias)
3.15 /24 3.50 /25 1.50 /20 1.30 /2070
0 m
A/m
m
Vds (V)
I d(5
mA
/div
)
DC
AC
Load line
Dispersion
Due to the trapping effect,VKNEE @ AC increased from 5 V to 12 V.
• Maximum Output Power decreases, as voltage swing and current swing reduce
• Drain efficiency decreases as knee voltage increases
DE = (Vmax-Vknee)/(Vknee+Vmax)
• Power added efficiency
PAE=(1-1/G)DE
Non –Idealities in GaN HEMTs
• The sequence of biases used to obtain a pulsed I-V curve from theTektronix curve tracer.
• The drain current is sampled during eachgate pulse.
• This biasing sequence is used to obtain the lighter pulsed (AC) I-V curves shown previously
Non –Idealities in GaN HEMTs
TIME
VGS
VDS
Vp
+20+18
+16
Von 23
45
6
123
456
IDS
VBREAKDOWN
IMAX
IDS
VDSVK1
(a)VKNEE
Bias Point
A
B
Q
Non –Idealities in GaN HEMTs
(b)
VK2
IMAX 2
VDS
IMAX 2 < IMAX1
VK2 > VK1
IDS
VBREAKDOWN
IMAX
IDS
VDSVK1
(a)VKNEE
Bias Point
A
B
Q
The consequence of trapping effects:
• the device I-V characteristic changes from (a) (b).
Non –Idealities in GaN HEMTs
Non –Idealities in GaN HEMTs Where can the traps be?
ϕS
1. S.I. Substrate (if SiC)
2. Substrate-GaN buffer interface
3. S.I. GaN buffer
4. AlGaN bulk
5. Free surface of AlGaN
AlxGa1-xN
GaN
Sapphire/ S.I.SiC
~ 200 Å
2-3 µµµµm
Possible trapping sites Deep levelFermi level
EC
2DEG
Source of the Buffer Traps
NOMINALLY UNDOPED GaN IS n-TYPE (~1x1016cm-3)
- - - - - - - - - - - - - - - -- - -
SG
D
GaN
Substrate
n Buffer
AlGaN
ns
BufferConduction
For a 1 µm Thick Buffer
nBuffer ~ 1016 cm-3 x 10-4cm = 1012cm-2
IBuffer
IChannel~ 10% (Unacceptable)
SOURCE OF TRAPS
GaN
Sapphire/SiC/Si…
HIGH RESISTIVITY BUFFER IS ACHIEVED THROUGH COMPENSATION
~ nS ~ 1013cm-2nChannel
Fermi Level (eV)
0.5
1
1.5
2
2.5
33.4
0
Electron ConcentrationConduction Band (cm-3)
1015 1016 1017 1018 1019
NAA Deep Acceptor Concentration1018
100
1015
1012
109
106
103
Non –Idealities in GaN HEMTs Making a S.I.Buffer - Compensation
NAA
ND
EV
ECND = 1017 cm-3
Non –Idealities in GaN HEMTs Making a S.I.Buffer - Compensation
NAA
ND
EV
EC
0.5
1
1.5
2
2.5
3
Fermi Level (eV)
0
3.4
0
0.2
0.4
0.6
0.8
1#of Empty Acceptors(fraction)
NAA
NAA
0
1015 1016 1017 1018 1019
NAA Deep Acceptor Concentration
ND = 1017 cm-3
Strategy
Minimize Background Donors
Background donorsVN, O
Compensating centersCarbon, Dislocation related deep levels
Non –Idealities in GaN HEMTs Making a S.I.Buffer
- - - - - - - - -- - -
SG
D
SubstrateGaN Buffer
AlGaN
nsMinimize background donors
Minimum necessary concentration of compensating centers
Fine tune growth conditions to
Optimize
From: water vapor, Ambient (loading, leaks)impurities in gases used, NH3, precursorsSapphire substrate
Non –Idealities in GaN HEMTs High quality AlGaN
- - - - - - - - - - - - - - - -- - -
SG
D
Substrate
GaN Buffer
AlGaN
ns
Maximize I Maximize ns, µ
Maximize ns Maximize PSP, PPEMaximize Al mole fraction without strain relaxation
Maximize fτ Minimize effective gate length, Minimize Lg and gate length extension
Maximize µ Minimize dislocations, smooth interface
Optimized AlGaN growth
• high Al %
• high structural quality
• minimum unintentional defectincorporation
Optimize
- - - - - - - - - - - - - - - -- - -
SG
D
Substrate
GaN Buffer
AlGaN
ns
Vds (V)
I d(5
mA
/div
)
DC
AC
Load line
Dispersion
Question :Are dislocations the dominant source of deep levels causing current collapse ?
Non –Idealities in GaN HEMTs Impact of Dislocations on Current Collapse
Optimized : GaN buffer, AlGaN layer
Non –Idealities in GaN HEMTs Impact of Dislocations on Current Collapse
LEO FETs Growth technique
(d)
HFET on regular GaN
HFET onLEO GaN
LEO is dislocation free
(b)
Dislocations propagate vertically in seed GaN
(e)
(c)
AlGaN
SiO2
(a)
(c)3 nm
• Dislocation mediated structural defects on Al0.3Ga0.7N on regular GaN
Non –Idealities in GaN HEMTs
2 µm
• Dislocation density reduced from 108-109 to < 106 in LEO GaN
• Dislocation mediated structural defects absent in Al0.3Ga0.7N on LEO GaN
Non –Idealities in GaN HEMTs
(c)3 nm2 µm
• HFETs on LEO and regular GaN showed similar DC I-V characteristics Typical max IDS ~ 250 mA/mm, max gm ~ 60 mS/mm.
• Pulsed measurement on HFETs on LEO GaN showed significantcurrent collapse
• Dislocations are not the primary source of current collapse
Non –Idealities in GaN HEMTs HFETs on LEO and regular GaN
DC
AC
Pulsed Measurement on LEO device
Non –Idealities in GaN HEMTs The story so far …
Is AlGaN surface important ?
- - - - - - - - -- - -
SG
D
SubstrateGaN Buffer
AlGaN
ns
AlxGa1-xN
GaN
Sapphire/ S.I.SiC
~ 200 Å
2-3 µµµµm
• Optimized GaN buffer
• Optimized AlGaN layer
• Dislocations are not the primarysource
• Substrate interface too far away
Trapping effects still present…
After..
Non –Idealities in GaN HEMTs The story so far …
• AlGaN surface is important !
time1996 1997 1998 1999 2000 2001
0
2
4
6
8
10
X
improved AlGaN
xAl > 0.3
thick S.I. GaN buffer
UCSB on Al 2O3
- - - - - - - - -- - -
SG
D
SubstrateGaN Buffer
AlGaN
ns
AlxGa1-xN
GaN
Sapphire/ S.I.SiC
~ 200 Å
2-3 µµµµmHitherto undiscussed
improvement to surface
PowerW/mm
• Measurement of surface potential - indicates existence of surface states
• Why should surface states exist?
• Polarization effects
• Surface states give rise to 2DEG
• Surface states also give current collapse - passivation
The free AlGaN surface
Experiment
Device Layer Structure Device Layout
Sapphire Substrate
undoped 2 µm
undoped 200 ÅAlxGa1-xN
i-GaN
LG LFG
L1 L2
AlxGa1-xN
GaN
S G FG D
The free AlGaN surface Measurement of surface potential
Floating gate voltage scan
DVFG
SG
VGD
VT
VFG
VGD
The free AlGaN surface Measurement of surface potential
Regime 1[ |VGD| < |VT| ]
EX|y=0
0
-80
-40
0 -80-40
VGD
Regime 1[ |VGD| < |VT| ]
Regime 2[ |VGD| > |VT| ]
+ ++
S FG DG
VT
Regime 2[ |VGD| > |VT| ]
S FG DG
EX|y=0
+ ++
++
Clamping of Peak Electric Field
0
200
400
600
800
1000
0
20
40
60
80
100
0.0 20.0 40.0 60.0 80.0
D1025v fg
VFG
IG
VDG
Peak Electric Field at gate edge is clampedIG limited
The free AlGaN surface Measurement of surface potential
VT
EX|y=0
Regime 2[ |VGD| > |VT| ]
S FG DG
+ ++
++
L1
VT dependence on L1 tells us the how the depletion region extends with gate-drain reverse bias
VT increases with L1
The free AlGaN surface Measurement of surface potential
-25
-20
-15
-10
-5
0
VGD (V)
V FG
(V)
a b
c
-80-60-40-200 -100
Floating gate voltage scan L1a< L1b< L1c
a) 0.5 µm b)1.5 µm c) 1.7 µm
VT
EX|y=0
Regime 2[ |VGD| > |VT| ]
S FG DG
+ ++
++
L1
The free AlGaN surface Measurement of surface potential
• Average E limited
• Large extension ofdepletion region
Measurements show that
-400
-300
-200
-100
0
0 1 2 3 4 5 6 7
V T (V
)
L1 (µm)
Lateral extent of depletion region
Simulated
Measured
S DG+ +++
++
++
S DG+ ++ +
+
+++
Negative charge on surface
extends depletion region
Negative charge on surface
The free AlGaN surface
What can the free AlGaN surface look like?
EV
EC
Density of States
Energy
EV
EC
DOS
E
EV
EC
DOS
E
EV
EC
DOS
E
Donor
AcceptorDonor
Donor
BUT …
• Strongly ionic semiconductors should not have surface states..(Kurtin et. al.)
• Ga-N and Al-N bonds have strong ionic character
(Ga, Al – strongly electro +ve, N - strongly electro –ve)
(000
1)
Wurtzite lattice group
Presence of polarization dipole and electric field in an unstrained crystal
The free AlGaN surface Influence of Polarization
Wurtzite group lacks inversion symmetry in c plane (0001 )
Spontaneous polarizationcoefficient is large
Presence of piezoelectric polarization dipole and electric field in a strained crystal
Large lattice mismatch between GaN, AlN, InN
Piezo-electric polarizationcoefficient is large
The free AlGaN surface Influence of Polarization
Crystal structure of GaN
Difference in spontaneous polarization coefficients
Built in Sheet Charge and Electric fields in
an AlGaN/GaN heterostructure
Lattice mismatch
Between GaN and AlGaN
Spontaneous Polarization
Induced Charge Sheet in AlGaN
Piezolectric Polarization
InducedCharge Sheets in
AlGaN
+ + + + + + + + +
- - - - - - - - - - - - -
GaN
AlGaNFor Ga-face crystal the two sheets add up
Ga-face crystal
The free AlGaN surface Influence of Polarization
+σPol
-σPol
GaN
AlxGa1-xN
S G D
- - - - - - - - - - - - - - - - - - - - -+ + + + + + + + + + + + + + +
- - - - - - - - - - - - - - - - - - - - -
-σchannel
The free AlGaN surface Influence of Polarization – Origin of Charge
Hall measurements on undoped AlGaN/GaN structures show that there exists a 2DEG at the AlGaN/GaN interface
EF
+σPol
-σPol
GaN
AlxGa1-xN
S G D
d
- - - - - - - - - - - - - - - - - - - - -+ + + + + + + + + + + + + + +
- - - - - - - - - - - - - - - - - - - - -
-σchannel
The free AlGaN surface Influence of Polarization – Origin of Charge
A metal (gate) can provide positive charge to satisfy charge neutrality.What happens when the surface is free? As in the access regions…
EF?+σMetal
•In the absence of any donors, 2DEG electrons must come from the VB
•Critical thickness depends on bandgap
•Polarization is not directly responsible for the 2DEG at AlGaN/GaN interface
2DEG formation - (1) Ideal Surface
d < dCR
Built-in field due to Unscreened dipole
Presence of polarization charge is not sufficient for 2DEG to form
d > dCR
2DEG
Reduced fieldE=(σPZ – qns)/ε
The free AlGaN surface
+ σPol
- σPol
+ σPol
- σPol
- σ2DEG
+ σHoles
• No 2DEG until the surface donors can empty into the GaN
• Critical thickness depends on donor level, fermi level in notch
• ns depends on the AlGaN thickness, surface donor level, polarization dipole
2DEG formation - (2) Surface Donors
Presence of polarization charge is not sufficient for 2DEG to form
d < dCR
Built-in field due to Unscreened dipole
The free AlGaN surface
+ σPol
- σPol
d > dCR
2DEG
Reduced fieldE=(σPZ – qns)/ε
Partially filled surface donors
+ σPol
- σPol
- σ2DEG
+ σSurface donor
d
ϕS∆Ec
EfodCR
Simulated 2DEG charge density
50
100
150
2000.5
1
1.5
5 ×1012
1 ×1013
1.5 × 1013
2 × 1013
50
100
150
200
5 ×1012
1 ×1013
1.5 × 1013
2 × 1013
Surface Barrier( eV)
AlGaN thickness(Angstroms)
Sheet charge(#/cm2)
q.ns = σPol.(1-dCR/d) - ε Efo/d + Ndd/2
q.ns = σPol.(1-dCR/d)
dCR = ε.(q.ϕS-∆Ec)/σPol
The free AlGaN surface
0
5
10
15
20
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Shee
t car
rier d
ensi
ty N
S (1
012 c
m -2
)
Alloy composition x
d = 31 nmT = 13 K0
5
10
15
0 10 20 30 40 50 60
Shee
t car
rier d
ensi
ty N
S (1
0 12
cm -2
)
AlGaN thickness d (nm)
x = 0.27T = 13 K
AlGaN/GaN Heterostructures by MBE
(a) vs AlGaN barrier width (b) vs Al content
theoretically calculatedNS assuming eΦB = 1.42 eV for all x
least square linear fit, dNS/dx = 5.45x1013 cm-2
theoretically calculatedNS assuming surface barrier
height qΦB = 1.42 eV
The free AlGaN surface
The free AlGaN surface
• Measurement of surface potential - indicates existence of surface states
• Why should surface states exist?
• Polarization effects
• Surface states give rise to 2DEG
• Surface states also give current collapse - passivation
Current Collapse Concept of Virtual Gate
Q. How can traps affect device characteristics?
• Directly trapping electrons in the channel i.e depleting the 2DEG density(collapse should not be affected by surface treatment)
OR
• Trapping charge elsewhere, creating a potential barrier to current flow(a virtual gate, spatially distinct from the metal gate)
OR
• Trapping charge underneath the metal gate, effectively changing the gate bias.
(pinch-off voltage changes, collapse should not depend on surface treatment)(∆∆∆∆VP = q. ∆∆∆∆ns / CAlGaN)
Effect of Surface Traps
Surface Donors+++++++++
+++++++++
- - - - - - - - -PolarizationDipole is
Charge Neutral 2 DEG
- - - - - - - - - - - - - - - - - - -
++++++++
SG
DElectrons can be injected from the gate into the very donor states that provide channel electrons.
- - - - - - - - -
EF
Current Collapse
Source
Drain
VG
VVG
Current Collapse Concept of Virtual Gate
Source
Drain
VGX
R
• VVG controls the drain current
• What is VVG , the potential on the virtual gate ?
• Time constants to charge/discharge the virtual gate
+ + + + + + + + + + + + + + +
- - - - - - - - - - - - - - - - - - - -AlGaN
GaN
+ + +
- - - -
Virtual Gate
Extended depletion region
e
IDS
VDS
A
B
Increasing trap occupancy,VVG more reverse biasedQ
• Trend of increasing reverse bias or increasing trap occupancy on the I-V plane of the device
• On the load line, VVG is most negative at B and least negative at A.
• Metal gate can decrease IDS , but not increase IDS
Source
Drain
VG
VVG
Current Collapse Potential of Virtual Gate
Current Collapse Time constants of Virtual Gate
Occupancy ofsurface traps
ORReverse bias on VVG
Channel does not fully open.
Drain Current
time
f3 > f2 > f1
time average (DC) drain current
Pinch Off
Fully Open Channel
f1 f2 f3
timeNo virtual gate
Negative virtual gate
TDETRAPTime constant of interest
IMAX
DC (low frequency) High frequencyDC (low frequency) High frequency
Dispersive device
11ff ff0 ff2
?Ideal deviceDispersive deviceIDS
VDS
Expected plot of maximum drain current as a function of frequency
: TDETRAP longff2
: TDETRAP short 11ff
Current Collapse Frequency dependence of Maximum drain current
IMAX
Experimental set up – Max drain current Current Collapse
Zin = 50 ohmZin = 50 ohm
SIGNAL SOURCE
DRAIN BIASGATE BIAS
MICROWAVE TRANSITIONANALYZER(sampling oscilloscope)
BIAS TEE BIAS TEE
RDC
DUT
AMPLIFIER
SIGNAL SOURCE
DRAIN BIASGATE BIAS
ANALYZER
BIAS TEE BIAS TEE
RDC
DUT
AMPLIFIER
Vpp (V)Vpp (V)Vpp (V)Vpp (V)
-8000
0
8000
0 100 200 300 400 500Vpp (V)
Measure waveform here
50 ohm load
IDS
VDS
VPP/ 50 = IPP = IMAX
140.0
145.0
150.0
155.0
160.0
165.0
170.0
175.0
180.0
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
Max
imum
Dra
in C
urre
nt (m
A) 1st iteration
2nd iteration
140.0
145.0
150.0
155.0
160.0
165.0
170.0
175.0
180.0
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
Max
imum
Dra
in C
urre
nt (m
A) 1st iteration
2nd iteration
Frequency (Hz)
Max
imum
Dra
in C
urre
nt (m
A) 1st iteration
2nd iteration
1st iteration
2nd iteration
Current Collapse Measure Max IDRAIN
IDS
VDS
VPP/ 50 = IPP = IMAX
Measure waveform here
50 ohm load
• Transient response is being measured
50Ω
VDD
VGS
Current Collapse Trapping Transient
• Bias and drive conditions cause formation of the virtual gate
• Transient response not a true frequency dependence
VDD
IDS
VDS
VGS
Formation of virtual gate
time
VDD
IDS
VDS
VGS
Formation of virtual gate
time
f1 f2 f3
• Drain current recovers when UV light is incident
50Ω
VDD
VGS
Effect of UV light
UV Light
VDD
VGS
IDS
Trapping Transient
time
OFF ON OFF
Current Collapse
+ σPOL
- σPOL
+ σSURFACE DONOR
- σ2DEG
EC
(1)
+ σPol
- σTRAPPED SURFACECHARGE
+ σSURFACE DONOR
- σPol
EC
(2)
Gate
Drain
e-
Net Positive Charge
Arrow indicates the transition from a non-existent virtual gate to negatively charged virtual gate.
Ec when virtual gate is non-existent
Ec, when surface states are charged
1 2
• The surface negative charge compensates the surface donor
• 2DEG channel is depleted
After virtual gate formed,
Current Collapse How does collapse occur ?
- σTRAPPED SURFACECHARGE
+ σPol+ σSURFACE DONOR
- σPol
EC
EC
Incident photonshν > EG
+
+ σPOL
- σPOL
+ σSURFACE DONOR
- σ2DEG
- σTRAPPED SURFACE CHARGE
+ σHOLES
• The effect of incident photons.
• Holes generated in the GaN channel are swept to the surface.
• The positive charge due to the holes neutralizes the virtual gate
Current Collapse What does UV light do?
0 2 4 6 8 10 12 14 16 18 20 220
10
20
30
40
50
60
70
Ids
(mA)
Vds (V)
VDD1, VDD2 …
Scan across the IV plane by choosing different VDD, the drain supply voltage, to observe the effect of drain bias on the extent and potential of the virtual gate.
Current Collapse Bias Dependence of Virtual Gate
VDD
IDS
VDD1
VGS
Formation of virtual gate
time
0 100 200 300 400 500 6000.0
0.2
0.4
0.6
0.8
1.0
Fit to 5V decay.0.69+0.31exp(-t/150)^0.47Fit to 10V decay0.58+0.42exp(-t/30)^0.45Fit to 18V decay0.50+0.50exp(-t/5)^0.40 (K)2nd Fit to 18V decay (J)0.48+0.52exp(-t/8)^0.43
Initial value
10kHz signalunpassivated NQZ HP wafern_100_1 - n#1100,1.5,0.5
Peak
to P
eak
curre
nt (n
orm
aliz
ed u
nits
)
time after bias applied (s)
5V 10V 18V fit to 5V decay fit to 10V decay (J) fit to 18V decay (K) 2nd fit to 18V decay
Current Collapse Trapping Transient
0 2 4 6 8 10 12 14 16 18 20 220
10
20
30
40
50
60
70
Ids
(mA)
Vds (V)
VDD1, VDD2 …
VDD
IDS
VDD1
VGS
time
I = I0 + I1. e-(t/τ)β
• Collapse depends on bias
• Trapping transient fits stretched exponential
Trapping TransientCurrent Collapse
0 100 200 300 400 500 6000.0
0.2
0.4
0.6
0.8
1.0
Fit to 5V decay.0.69+0.31exp(-t/150) 0.47Fit to 10V decay0.58+0.42exp(-t/30) 0.45Fit to 18V decay0.50+0.50exp(-t/5) 0.40 (K)2nd Fit to 18V decay (J)0.48+0.52exp(-t/8) 0.43
Initial value
10kHz signalunpassivated NQZ HP wafern_100_1 - n#1100,1.5,0.5
Peak
to P
eak
curre
nt (n
orm
aliz
ed u
nits
)
time after bias applied (s)
5V 10V 18V fit to 5V decay fit to 10V decay (J) fit to 18V decay (K) 2nd fit to 18V decay
I = I0 + I1. e-(t/τ)β
Trapping transient fits stretched exponential
e-
GATE
DRAIN
• Electric field that induces leakage reduces
• Active traps located continuously further away from gate
Virtual Gate
+ + + + + + + + + + + + + + +
- - - - - - - - - - - - - - - - - - - -AlGaN
GaN
+ + +
- - - -
e
Virtual gate formsEC
Current Collapse Surface Passivation
- - - - - - - - - - - - - - - -- - -
SG
D
Substrate
GaN Buffer
AlGaN
ns- - - - - - - - - - - - - - - -
- - -
SG
D
Substrate
GaN Buffer
AlGaN
ns
SiN
• Surface passivation to prevent formation of virtual gate
Current Collapse Effect of Passivation
0 2 4 6 8 10 12 14 16 18 20 220
10
20
30
40
50
60
70
Ids
(mA)
Vds (V)
VDD1, VDD2 …
VDD
IDS
VDD1
VGS
time
0 100 200 300 400 500 6000.0
0.2
0.4
0.6
0.8
1.0
1 - Passivated (10V) 2 - Passivated (14V) 3 - Passivated (18V) 4 - Unpassivated (5V) 5 - Unpassivated (10V) 6 - Unpassivated (18V)
Initial value
Peak
Dra
in C
urre
nt (n
orm
aliz
ed u
nits
)
Time (seconds)
123
45
6
Current Collapse Effect of Passivation on Microwave Power
0 100 200 300 400 500 6000.0
0.2
0.4
0.6
0.8
1.0
1 - Passivated (10V) 2 - Passivated (14V) 3 - Passivated (18V) 4 - Unpassivated (5V) 5 - Unpassivated (10V) 6 - Unpassivated (18V)
Initial value
Peak
Dra
in C
urre
nt (n
orm
aliz
ed u
nits
)
Time (seconds)
123
45
6
0
5
10
15
20
25
30
0 5 10 15 20Input Power (dBm)
Out
put P
ower
(dBm
) /
Gai
n(dB
)
0
10
20
30
40
50
PAE
(%)
Pout (dBm)Gain (dB)PAE (%)
6.59W/mm
• Extent of current collapse dramatically reduced on passivated devices
• Measured output power close to maximum available at that bias point
• Existence of a polarization dipole induces surface donor-like states
• Surface donors give rise to the 2DEG
• Surface donor states accept electrons making surface potential negative
• Accumulation of negative charge in gate drain region creates a virtual gate
• The spatial extent and potential of the virtual gate depends on bias and drive conditions
• Current collapse is due to inability to modulate the virtual gate
• Passivating the surface prevents formation of virtual gate, hence reducing current collapse
Conclusions