quartus ii la pg - 國立臺灣大學access.ee.ntu.edu.tw/course/advanced_vlsi_91/course... · at...

Advanced VLSI Due Wednesday, 01/08/2003

SOPC － LAB1

I. Introduction

The purpose of this lab is to familiarize you with all the items in the kit. This tutorial tells you how to develop FPGA system in Quartus II. You are ready to begin using the Nios Development Kit to create your own design. Once you finish your design, you should measure your signal by using LA (Logic Analyzer) and PG (Pattern Generator).

II. Lab contents

At lab1 you have to design a 4-bit (0 ~ 15) positive edge trigger count up counter. It can load input value when Load = 1 and clear output value when Reset = 1. When Enable = 1 it has output value. So we have 4-input data pins, 4-input control pins (Clock, Reset, Load, and Enable), and 4-output data pins. Use Quartus II to compile your design and download it to APEX20K (we take it as a FPGA board in this Lab). Verify your design by PG and LA.

4

Clock

4

4-bit count up counter

Enable

Load

Reset

Data_out Data_in

12/25/2002 ACCESS IC LAB P. 1


Clock Reset Enable Load Data_out

H/L/↓ × × × No Change

(Hold)

↑ 1 × × Clear

↑ 0 0 × No Change

(Hold)

↑ 0 × 1 Data_in

↑ 0 1 0 Count

(Increment)

III. Tutorial

1. Start the Quartus II Software

In this section, you start the Quartus II software and begin creating your project.

To start the Quratus II software, use the following methods:

Choose Start menu → programs → Altera →

Quaruts II <version>

2. Create a project

Before you begin, you must create a new Quartus II project.

To crate a new project, perform the following steps:

(1) Choose File → New Project Wizard. (2) Click Next. (3) Specify the working directory for your project. This walkthrough uses

the directory C:\my documents\avlsi\<your id no.>\lab1.

(4) Specify the name of the project and the top-level design entity. This lab



uses My_project. (5) Click Finish.

3. Create a New .bdf

In this step you create a new BDF called My_project.bdf. This file is the top-level design entity of the counter project.

To create a new BDF, follow these steps:

(1) Choose File → New. The Device Design Files tab of the New dialog box appears automatically.

(2) In the Device Design Files tab, select Block Diagram / Schmatic file. (3) Click OK. A new Block Editor window appears. (4) Choose File → Save As (5) The Save As dialog box automatically displays the project directory

C:\my documents\avlsi\<your id no.>\lab1. You will save the file into this directory.

(6) In the File name box, type counter as the name of the BDF, if necessary.

(7) Make sure Add file to current project is turned on. (8) Click Save. The file is saved and added to the project. Leave the .bdf



open for the remainder of the Design Entry section.

4. Add the Symbol to the BDF

In this section you create a new symbol for your Verilog code and add it to your BDF.

Follow these steps to add the symbol:

(1) Click the Block tool in the Block Editor Toolbar. (2) Click and drag on the block diagram counter.bdf. You can see the block

symbol on the diagram. (3) Right click on the Block symbol and choose Block Property. A Block

Property window shows. (4) In the Name box, Type counter as the name of the block. (5) Choose I/O and type your I/O pin Name and Type. When you input one

pin, click Add to display on Existing block I/Os section. (6) When input all pins, click OK. (7) Right click on the Block symbol and select AutoFit to adjust your block

symbol size.



5. Add Pins & Primitives

Before you do compilation, you have to enter input, output, and bidirectional pins.

Perform the following steps:

(1) Click the Symbol Tool button on the Block Editor toolbar. The Symbol dialog box appears.

(2) In the libraries list of the Symbol dialog box, click the “+” icon to expand the C:\quartus\library folder. Expand the primitives folder and then expand the pin folder.

(3) In the pin folder, select the input primitive. (4) Click OK. (5) Click an empty space five times to insert a total of 5 INPUT pin

symbols. (6) Repeat steps (3) through (4) to inset 1 OUTPUT pin symbol. (7) Double-click the pin symbol that you entered. The General tab of the

Pin Properties dialog box appears. (8) Type pin name in the Pin name(s) box. Repeat this until all the pins has

it pin name. (9) Move the input pin to touch the Block Symbol, and then move away.

You can see they make connection. Repeat this until all the pins have connected. Of course you can use the wire or bus in the Block Editor toolbar to draw the line.



6. Create a Verilog file

Now you can write your Verilog code in the block diagram.

To write your Verilog code, follow the steps:

(1) Right click on the Block symbol and select Create Design file from Selected Block. The Create Design File tab appears automatically.

(2) Choose Verilog HDL and input file counter.v in the File name tap. Click OK.

(3) You can see the counter.v file that has some information and it creates Module counter and Port Declaration automatically. Write your Verilog code into this file.

(4) Repeat steps (1) through (3) to create VHDL code if you are familiar with it.

(5) Choose File → Save.



7. Create compiler settings

You can create Compiler settings to control the compilation process. The compiler settings specify the compilation focus, the type of compilation to perform, the device to target, and other options.

This section includes the following steps:

(1) Choose Processing → Compile Mode (2) Choose Processing → Compiler Settings (3) View the Compiler General Settings. It displays only the default

compiler general settings created by the Quartus II software when the project was initially created.

(4) Specify the Chips & Devices. In the family list, select APEX 20KE then you can see many types listed in the Available devices. Choose “EP20K200EFC484-2X” for our FPGA design. Under Target device, select Specific device selected in ‘Available device’ list. You can go to step 8 to do Pin Assignment.

(5) Select Mode. In the Compilation level, choose Full compilation, including programming file generation and actual timing data. In compilation speed/Disk usage tradeoff, choose Smart compilation/mode disk space.

(6) Click Synthesis & Fitting. In the Timing-driven compilation, choose Optimize timing and Optimize I/O cell register placement for timing.

(7) Specify Verification. Choose Run timing analysis. (8) Choose Processing → Start compilation. You also click the compile

toolbar button. (9) When compilation completes, you can view the results in the counter

Compilation Report windows. If the Compiler displays any error messages, you should correct them in your design and recompile it until it is error-free.

(10) You can select Pin-Out File in the Results for “My_project” to check if the pin assignment is correct.



8. Specify the Pin Assignments

You have to assign your pins in order that we can use LA & PG to verify your design.

To verify the pin assignments, follow these steps.

(1) Choose Processing → Compiler Settings (2) Click the Chips & Devices tab. (3) Click Assign Pins. The Pin Assignments dialog box appears with the

new pin assignments listed in the Available Pins & Existing Assignments list.

(4) You can see the Connector JP11 in the Figure 1. We use these pins to input and output our values. You also can use other pins that showed in our slides. Choose K1 in the Available Pins & Existing Assignments list.

(5) Input Clock (your pin name in the Verilog or VHDL code, for example) in the Pin name. Click Add.

(6) Repeat this step until all the pin names are in the Available Pins & Existing Assignments list.

(7) Click OK.



Figure 1

9. Create simulate settings

You can create Simulate settings to control the simulation process. The simulate settings specify the simulation focus, the type of simulation to perform, time period, and other options. Before you begin, you have to create a new waveform file.

Follow these steps to start simulation:



(1) Choose File → New. The Device Design Files tab of the New dialog box appears automatically

(2) Click Other Files. (3) In the Other Files tab, select Vector Waveform File. (4) Click OK. Then the Waveform Editor Window shows. (5) Choose Time → End time. The New Time dialog box appears. You can

input the whole time that you want to see. Input 200, for example. Then click OK.

(6) Choose View → Auxiliary Windows → Node Finder. The Node Finder block shows. Select Pins: all in the Filter tab and you can see the counter in the Look tab.

(7) Click Start. You can see the I/O pin name display in the Nodes Found. Select the I/O ports you want, and drag them to the Name block of the Waveform.

(8) Close Node Finder block. You can see the pins you select display on the Name block and they have their initial value.

(9) Next we assign the values on each I/O pins. Right click on the name and choice value → count value. The Count Value block shows. Input your test pattern in the Counting block. Keeping doing this until you specify all the input pins values.

(10) Choose File → Save As. In the File name box, type My_project as the name of the waveform.

(11) Choose Processing → Simulation. (12) Choose Processing → Simulator Settings. View the simulator General

Settings. It displays only the default compiler general settings created by the Quartus II software when the project was initially created.

(13) Select Time/Vectors. In the simulation period, choose Run simulation



until all vector stimuli are used. (14) Click Mode. In the simulation mode, choose Timing. (15) Specify Options. Choose simulation coverage reporting. (16) Choose Process → Run simulation. Then you can see the waveforms

in the block and know if it works correctly.

10. Download our program

Once you have properly connected and set up the ByteBlasterMV cable to transmit configuration data over the JTAG port, you can configure the APEX device on the Nios development board with your design.

To configure the APEX device on the Nios Development board with the counter design, follow these steps:

(1) Choose Process → Open Programmer. The Programmer window opens a blank Chain Description File (.cdf).

(2) Choose File → Save AS. (3) In the Save As dialog box, type My_project.cdf in the File name box. (4) Click Save. (5) In the Mode list of the Programmer window, make sure JTAG is

selected. (6) Under Programming Hardware, click Setup. The Hardware Setup

dialog box appears. (7) In the Hardware Type list, select ByteBlasterMV. (8) In the Port list, select the port that is connect to the ByteBlasterMV

cable. Click OK. (9) Click Close to exit the Hardware Setup window. (10) Click Add File. The Select Programming File dialog box appears. (11) Specify the My_project.sof file in the File name box. (12) Click Open. The SOF is listed in the Programmer window. (13) In the Programmer window, turn on Program/Configure. See figure. (14) On the Nios development board, make sure switch SW8 is in the

CONNECT position, and that switches SW9 and SW10 are in the BYPASS position. Figure illustrates the correct configuration of the JTAG switches:



(15) Click Start. The Programmer begins to download the configuration data to the APEX device. The Progress filed displays the percentage of data that is downloaded. A message appears when the configuration is complete.

11. Connect Pattern Generator (PG) and Logic Analyzer (LA)

Now we connect PG and LA to our Board in order to verify our code.

Perform the following steps:

(1) Connect the probe of the PG and LA to the input and output pins, respectively, of APEX20K that we defined in step 8. Check carefully with your pin connections and ground also connect to board.

(2) Execute the PG. (3) Set work frequency in “environment parameter setting.” Be sure that



the frequency is not so fast that LA cannot sample it. We set it 20MHz. (4) Set all input pins in “signal menu” and edit their waveforms. (5) Execute the LA. (6) Set trigger level in “trigger level setting.” (7) Set all output pins in “signal menu.” (8) Set sampling frequency. Make sure that the sampling frequency is four

times or more the work frequency so that the LA can sample it. We set it 100MHz.

(9) Set trigger condition in “trigger parameter settings.” (10) Push “sampling data” in the LA. (11) Push “output waveform” in the PG. (12) Push “stop sampling data” in the LA. You can see the output waveform.

IV. Demands

1. Show your Verilog code (4-bit positive edge trigger counter).

2. Show your Pin-out file. (You can go your My_project directory and find the file.)

3. Show your simulation waveform diagram under the Quartus II simulation mode.

4. Show your result by PG and LA.

V. Bonus

Is there possible to make your design run at more high frequency? If we can, how do you make it? If not, why? Please discuss this more.


quartus ii la pg - 國立臺灣大學access.ee.ntu.edu.tw/course/advanced_vlsi_91/course... · at...

Documents