low-power cmos design - 國立臺灣大學access.ee.ntu.edu.tw/course/advanced_vlsi_91/course... ·...
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Graduate Institute of Electronics Engineering, NTU
Low-Power CMOS Design
For Advanced VLSI Design and VLSI Signal Processing Courses
12-04-2002台大電機系 吳安宇教授
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Data SourceData Source“Low-power Circuit Design Basics,” by Prof. Jan M. Rabaey, UC Berkerly, in tutorial of ISCAS, London, 1994.“Can we simultaneously achieve High Speed and Low Power in IC Design?” by Prof. Wentai Liu in 7th
VLSI/CAD Symposium, 1996.Chapter 17 of Textbook.
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Low Power Design Low Power Design ––An Emerging DisciplineAn Emerging Discipline
Historical figure of merit for VLSI design –performance (circuit speed) and chip area (circuit density/cost). ButPower dissipation is now an important metric in VLSI design.
No single major source for power savings across all design levels – Required a new way of THINKING!!!Companies lack the basic power-conscious culture and designers need to be educated in this respect.
Overall Goal – To reduce power dissipations but maintaining adequate throughput rate.
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Motivation Motivation -- MicroprocessorMicroprocessor
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Motivation Motivation -- MicroprocessorMicroprocessor
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Competitive Reasons Competitive Reasons –– Low PowerLow PowerBattery Powered Systems – Extended Battery Life and reduce weight and size.High-Performance Systems
CostPackage (chip carrier, heat sink, card slots, plenum, …)Power Systems (supplies, distribution, regulators, …)Fans (noise, power, reliability, area, …)Operating cost to customer – Energy Star issue.
ReliabilityFailure rate increase by 4X for Tj @ 110C vs 70CMission critical operation at 100C
Size and Weight – Product footprint (office and deskspace)
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The Power Crisis : PortabilityThe Power Crisis : Portability
Expected Battery Lifetime increaseOver next 5 years: 30-40%
PDA, Cellular Phone,Notebook Computer,etc.
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A Multimedia Terminal A Multimedia Terminal –– The The InfopadInfopad
Present day battery technology (year 1990) – 20 lbs for 10hrs
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IC Design SpaceIC Design Space
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Low Power DesignLow Power DesignSource of power disspation
P = Pswitching + Pshort-circuit + Pleakage + Pstatic
Definitions:Switching power P = CV2fαShort circuit power P = IscVLeakage power P = IleakageVStatic power P = IstaticVα : switching activity factor
Low power design would look at the trade-offs of the above issues
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Dynamic Power ConsumptionDynamic Power Consumption
Energy/transition = CL * Vdd2Power = Energy/transition * f = CL * Vdd
2 * f
Not a function of transistor sizes!Need to reduce CL, Vdd, and f ti reduce powerReduce the probability, P0 -> 1
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Dynamic Power Consumption Dynamic Power Consumption --ExtendedExtended
Power = Energy/transition * transition rate= CL * Vdd
2 * f0->1= CL * Vdd
2 * P0->1 * f= CEFF * Vdd
2 * f
Power Dissipation is Data Dependent Function of Switching Activity
CEFF = Effective Capacitance = CL * P0->1
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Ultra Low Power System DesignUltra Low Power System DesignPower minimization approaches:
Run at minimum allowable voltageMinimize effective switching capacitance
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ProcessProcessProgress in SOI and bulk silicon
(a) 0.5V operation of ICs using SOI technology(b) 0.9V operation of bulk silicon memory, logic, and processors
Increasing densities and clock frequencies have pushed the power up even with reduce power supply
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Choice of Logic StyleChoice of Logic Style
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Choice of Logic StyleChoice of Logic Style
Power-delay product improves as voltage decreasesThe “best” logic style minimizes power-delay for a given delay constraint
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Power Consumption is Data Power Consumption is Data DependentDependent
Example : Static 2 Input NOR Gate
Assume :P(A=1) = ½P(B=1) = ½
Then :P(Out=1) = ¼P(0→1)
= P(Out=0).P(Out=1)=3/4 * 1/4 = 3/16
CEFF = 3/16 * CL
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Transition Probability of 2Transition Probability of 2--input NOR input NOR GateGate
as a function of input probabilities
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Switching Activity (Switching Activity (αα) : Example) : Example
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GlitchingGlitching in Static CMOSin Static CMOS
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At the Datapath LevelAt the Datapath Level……ReusableIrregular
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Balancing OperationsBalancing Operations
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Carry RippleCarry Ripple
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Data RepresentationData Representation
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Low Power Design Consideration (contLow Power Design Consideration (cont’’))
(Binary v.s. Gray Encoding)
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Resource Sharing Can Increase Resource Sharing Can Increase ActivityActivity
(Separate Bus Structure)
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Resource Sharing Can Increase Resource Sharing Can Increase Activity (contActivity (cont’’d)d)
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Operating at the Lowest Possible Operating at the Lowest Possible VoltageVoltage
Desire to operate at lowest possible speeds (using low supply voltages)Use Architecture optimization to compensate for slower operation
Approach : Trade-off AREA for lower POWER
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Reducing VReducing Vdddd
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Lowering VLowering Vdd dd Increases DelayIncreases Delay
• Concept of Dynamic Voltage Scaling (DVS)
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Architecture TradeArchitecture Trade--offs : Reference offs : Reference Data PathData Path
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Parallel Data PathParallel Data Path
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Pipelined Data PathPipelined Data Path
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A Simple Data Path : SummaryA Simple Data Path : Summary
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Computational Complexity of DCT Computational Complexity of DCT AlgorithmsAlgorithms
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Power Down TechniquesPower Down Techniques• Concept of Dynamic
Frequency Scaling (DFS)
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EnergyEnergy--efficient Software Codingefficient Software CodingPotential for power reduction via software modification is relatively unexploited.Code size and algorithmic efficiency can significantly affect energy dissipationPipelining at software level- VLIW coding styleExamples -
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Power Hunger Power Hunger –– Clock Network Clock Network (Always Ticking)(Always Ticking)
H-Tree – design deficiencies based on Elmore delay modelPLL – every designer (digital or analog) should have the knowledge of PLL
Multiple frequencies in chips/systems – by PLLLow main frequency, ButJitter and Noise, Gain and Bandwidth, Pull-in and Lock Time, Stability …
Local time zoneSelf-TimedAsynchronous => Use Gated Clocks, Sleep Mode
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Power Analysis in the Design FlowPower Analysis in the Design Flow
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Human Wearable Computing Human Wearable Computing -- PowerPowerWearable computing – embedding computer into clothing or creating a form that can be used like clothingCurrent computing is limited by battery capacity, output current, and electrical outlet for recharging
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ConclusionsConclusionsHigh-speed design is a requirement for many applications
Low-power design is also a requirement for IC designers.
A new way of THINKING to simultaneously achieve both!!!
Low power impacts in the cost, size, weight, performance, and reliability.
Variable Vdd and Vt is a trend
CAD tools high level power estimation and management
Don’t just work on VLSI, pay attention to MEMS – lot of problems and potential is great.
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ApplicationsApplicationsPortable Multimedia TerminalWireless C&CSystem on Chip (From Dr. Yang of Windbond)
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Applications IApplications IWireless Computing/CommunicationWireless Computing/Communication
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Applications IIApplications IIA Portable Multimedia TerminalA Portable Multimedia Terminal
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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
pp. 45台灣大學 吳安宇 教授
Applications IIIApplications IIISystem Value of IC ProductSystem Value of IC Product
Concept of lays
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pp. 46台灣大學 吳安宇 教授
Applications IVApplications IVSystem on ChipSystem on Chip
Entire system functionLogic + MemoryMore than two types of devices
Allow more freedom in architectureConst/Performance trade-off
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pp. 47台灣大學 吳安宇 教授
Applications VApplications VNew Opportunity for Taiwan IC IndustryNew Opportunity for Taiwan IC Industry
PASTDigital ICµPIBM Compatible + MD-DOS
FUTURESystem On Chip
Reduce head-on competition on standard productsTechnology will be availableManufacturing Service availableSame starting point as other countriesCan have more R/D focus