Otrona

TECHNICAL MANUAL

© 1983 Otrona

Theory of Operations

Overview

This chapter describes the 8086 16-bit processor board. The 8086 16-bit board fits into the ~xpansion board connector on Attache's main procesE!.9r board, proV'i,d.ipSjlccess to the system bus. -

The following section describes the overall Attache 8:16 system flow.. Subsequent sections~de~cribe in detail the individual logic sections of the 8086 l()-bit board, which include: the 8086 CPU (Central processing Unit)" and associated control logic. 256K bytes of RAM (Random Access ~r1emory), interface circuitry to the Z-80A main processor board~,·'.'and optional circuitry. Optional circuitry includes the GPm ci:?ritlioller (General Purpose Interface BUS), the serial synchron~9u~: port, 'and th~ 8087 numeric coprocessor.

Hardware modifications upon Attache to construct Attache 8:16 include a secondary board connected to the 8086 16..;bit. board. a high-resolution graphics board fit onto the Z-80A main processor board, and alterations to the display circuitry on the main processor board. These modifications are described in the final sections of this. chapter.' ,

Schematics of the 8086 16-:-b;(t bPard.· secondarY'~ard. graphics~ modification. and display modification are located. in Appendix A. Specific chips are identified,in this chapter b.Y their schem~tic location number in paren'thesis. as we~l as bi their manufacturer's part number. Not!;!. thattbe manufactur~rs identified in this, manual are for the' primary'chip source ..

Logic Overvi~. -The logic s4l!,dtions oo:the)$086 16-bi t boa',l':c!a're the processor, the RAM (R~ndom Access, Memory), the ~-80A interface. and circuitry for~ionalfeatures. ::

The G?U;q~r(iu;ltry consi$ i>f an 8086, a ClocK,i'generator. a wait _stat~': gener.a:1:or, and a. processor command decoder. The 8086 proce$Sb.+:,~s • true Ji6-bit processor with 20 address lines. c.pable: of; addressing up -to;1 Megabyte of RAM~ . ' .

'; .. -'" i.~·,,;.', <:. -:."'~- "'-~.<~:; ,'. -TheaO'8Q,:"lAS-bit . board contains 256K bytes of. dynamic RAM~.a capacitive'metnod of storage .whic;h requfres periodic refreshes.

A socket ~s lQ'c~t.edin- par"~ll~{' with t!ie '80 86 pr86e~jsor. - This sock", OAJlcOnt.a.tn either an 8087 numeric coprocessor or a secondaryOOIr:4. . The secondary. board issues hardware interrupts that allow Attache 8:16 to emulate IBM-PC hardware.

".' .'

2-1

8086

Attache 8: 16 Technical Manual Theoq . of Operation

All interface between the Z-80A and the 8086 is handled through an 8255A interface chip. The Z-80A operates basically as an Input/Output handler, with the capability to interrupt the 8086. The 8086 cannot interrupt the Z-80& The Z-80A/8086 interface is described in detail in the following sectio~

In addition to the 8087, optional features of the 8086 16-bit board include a synchronous serial port, and a GPIB (General Purpose Interface Bus) controller. These options are described in following sections.

\ J \ '/ f l" .- - --1

GPIB see I I

8087 I I

I . ... _ ~ _ J ~~

,

" , 1, . 8255A .. Z-80A - 1\ .. ~ ~

~

~

" IF , r- - I.. - -.,

256K EPROM

I Secondary I RAM I Board .

r I L _____ J "

system Block Diagram

2-2

Attache 8:15 Technical Manual Theo~ of Operation

Z-SQA/SOS6 Int.:trfac . .:t

The Z-80A handles all low-level I/O in the system: character input and output buffering. disk reads and writes. and console (display ~.nd key_board) activity. The 8086 BIOS (Basic Input Output System) converts DOS requests into requests to the Z-80A. The BOB6 does very little I/O processing itself.

All data transfers are either data reads from the I/O devices on the Main Processor Board (via the Z-BOA) or data writes from the BOB6 to the Z-80A I/O devices.

- . Where possible. write commands (from 80B6 to Z-BOA) take advantage of the dual processor system. The 80 B6 does not wai t for completion status of a given command. allowing simultaneous Ilo processing. Read commands (from Z-BOA to BOB6) 'require the BOB6 to wait for completion. '

The two processors communicate through a single B-bit parallel port. Since all transfers (commands. status, and data) flow through- this port. a master/slave-communication protocol is required. The 8086 acts as the master, all actions are the resul t of B086 commands. The Z-80A receives commands. parameters and data, and re~urns data and status.

Interface with the Attache Z-BOA bus is handled by an IHtel B?55A Programlnable Periphnral Interface chip. The 82.55A hA.s 24 I/O pins, which are programmed as two groups of 12 pins. One group operates in MODE 2 (a bidirectional mode using eight lines for a bus and five lines, borrowing one from the other group. for handsha}d.ng). and the other group operates in MODE 0 (which is­programmed for output).

The Z-BOA can interrupt the BO B6. but the BO B6 cannot interrupt the Z-BOA. (The secondary board can interrupt the Z-80A. which plac~s the B085 into a wait state.) When the bOB~ r(:quires data from the Z-80A interface, it pulls signe-.! INTRm true. The Z-ROA. detects this flag, retrieves the requested information. and passes it to the BOB6 via the B255A. _

The ~:-80A is constantly operating as an I/O handler. handling all of the Z-80A board de~ices and awaiting INTREQ from the B086.

Port assignments are as follows:

100Port A - Read/Write 102 Port B ~ Read/Write 104 Por.-;:. C - Read/Write 106 Control Port - Write only

Port A is used for bidirectional interface with the Z-80A bus.

2-3

Attache 8 :16 Technical Manual T.beo~ of Operation

Port B Bits 0 - 3 are used by the interrupt controller logic to mask 6ut interrupts. Bit 4 enables WAIT logic. and Bit 5 is connected to J4 to enable or disable high-resolution graphics (1 = medium resolution. 0= high resolution).

Port e Bits 3-7 contain PORT A status information as follows:

Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0

Interrupt request to 8086 if ON Interrupt enable associated with IBF IBF (Input Buffer Full) if ON Interrupt erable associated with OBF/ OBF/ (Output Buffer Full) if low DSR/ (Data set Ready) from serial interface

Port e Bits 4 and 6 can be set or reset by writing to the control port as follows:·

109B Set IBF i.nterrupt enable 10SH Clear IBP. interrupt enable lODH Set OSF interrupt enable lOCH Clear OBF "interrupt enable

oela is written to the control port to initialize the 8255A with Port A in ~10DE 2 and Port B in r·10DE 0 (0 utput).

The 8255A can interrupt the 3086 at interrupt level 3.

0.

z .. aOA. Ports The Z-80A communicates wit.lJ. Port A of the 8255A as follows:

Z-80A Port Read Write

B8 B9

status Bits:

Bit 0

Bit 1

Control Bits:

Bit 0

2-4

Data Status

Data Control

1 = no data ready o = data ready for raad

1 = ready to accept data o = not ready to accept data

1 = Reset 8086 o = Set 8086 to run state

Attache 8 :16 Technical Manual Theory of Operation

The Z-80A/8086 interface which occurs during the system boot and during specific commands is desc:tibed in Chapter 3.

8086 CPU

The CPU circuitry consists of an 8086 processor (US), a clock generator (011), a wait state generator (027), and a processor command decoder (028). Additionally, chip location OlOls signal lines are in parallel with 'the 8086. '

The secondary board connects to the 8086 l6-bit board at sock,et 010. 010 may optionally be used to attach an 8087 numeric coprocessor instead of the secondary ~oar~ This option is called an Attache 8:l6A" and f.eatures an 8087 coprocessor, but does not feature IBM compatibility. The 8087 is described in a foll~ing section in this chapter.

The 8086· (05) is operated in maximum mode. The clock generator is an 8284A (Ull) which derives its signal from a 24MHz crystal (Xl) to provide an 8MHz, 1/3 duty cycle clock. Signal line /CLK is an inverted output from the 8284A, and DCLK is a twice­inverted delayed cloc~

The 8284A (011) also provides READY line synchronization. RAM cycles do not use wait states, except as provided by RAS/CAS circuitry during refreshes. For non-RAM cycles, wait states are provided according to, the setting of jumper L on the output of flip-flop U27. In ~ttache 8:16, this jumper is connected to J to provide two wait states. When this jumper is connected from L to K, U27 generates a single wait s,tate, L to J generates two wait states, and L t9 I generates three wait states. .

Note'that no bus controller chip is used. Instead, Address Latch Enable (ALE) is simulated by the flip-flop circuitry U62, U29, and U27. When ALE is high, addresses and status lines are allowed to settle. At the middle of Tl, address and status lines have settled and are valid. The rising edge of the cl:ock then sets ALE low, and address lines are latched by U16, U17 and U18, and the status lines, are latched by an LS137 decoder (U~.8).

The LS137 decoder (U28) also decodes the status lines and provides strobed control lines which resemble 8288 bus controller lines. Control lines are enabled by U28Pin 5, valid at the start of T2. For non-RAM cycles, U27 provides two wait states, as determined by the setting of jumper L.

Note that 028 is a socket which contains a header connecting to the secondary board. The LS137 decoder is actually U9 on the secondary board.

2-5

Attache 8:16 ~cal Manual Tbeoty of Operation

t1 u u it

Ctl

STATUS 1

lLEI ---, L

strohl· (UU.S) ________________ ~r__

HS

CIS

JlUI

RAM Cycle

Dynamic RAM

The 64K x 1 dynamic RAM (Random Access Memory) chips comprise a 256K byte memoty array on the 8086 16-bit board. Thirty-two chips (U34-41, U44-51, U54-61, U64-71) are organized into two 128K byte banks, addressed from 0 to 128K bytes and 128 to 256K bytes.

2-6

Attache 8:16 Technical Manual Theory of Operation

RAM address mul tiplexers (025 and U26) mul tiplex 16 latched address lines (Al - Al6) into a row address and a column address. Gates U53 and U30 ensure that a RAM cycle is initiated on the rising edge of the clock during Tl when A18 and A19 are low (address 0 to 256K), and when a memory cycle has been indicated on 8086 status lines SO. Sl. and S2. .

Memo~ cycle timing is controlled by flip-flops U43 and 062. RAS (Row Address Strobe) is active for two clock cycles. CAS (Column Address Strobe) is also active for two cycles. but follows RAS by one cycle via the feed-back delay caused by U53 and U43.

Signal line MUX toggles on the falling. edge of RAS and CAS becoming active, which selects column address rather than row address from the 025 and U26 outputs. .

Depending on the st·ate of Al7 (input to decoder 042). either . signal RASO (driving the first 128K) or signal RASl (driving the second 128Kl is 'generated by decoder U42 and gate U52. The 8086 can perform operations on a word (AO and /BHE both low). on the high-byte only (AO high /BHE low) or on the low-byte only (AO low. /BHE high). OR gates in chip U29 control CAS for high-byte. low-byte or word operations, as required.

Counter (Ul4) divides the 8MHz system clock by 128. to provide a refresh request eve~ 16 microseconds. A refresh is granted via flip-flop 023 Pin 9 when RAS and CAS are idle. which must occur within four clock cycles of a refresh request.

During refreshes. U25 and U26, the RAM address multiplexers. are disabled. and b~ffer (U24) is enabled. This gates the current refresh address ·from U15, an 8-bit counter which advances with every refresh request. onto the RAM address lines. RAS and CAS then perform a normal memo~ cycle sequence. except that signal line MUX remains high ~d CAS is blocked by NAND gate U72 so that CAS canno1: reach the RAM.

During refresh cycl·es, memory cycles are held. which places the 8086 into a wait sta.te. At the conclusion of the refre.sh cycle (when RAS and CAS are again inactive). flip-flop U23"5 output line REF is cleared. . This allows any pending memory cycle to proceed. and consequently releases the 8086 wait state.

2-7

ttl

STATUS

RIP \lEQ (Ull.S)

RlF (ut3.')

lAS

CIS

!tUl (\lDYIl

RIADI (US. n)

ALEI

Attache 8:16 TecbnicalManual Theo.:y of Operation

I it t1 tZ t3 tv I t. tv I tv t4

L

L-

----1

Refresh Cycle (with delayed memory cycle)

interrupt Structure The Z-80A can interrupt the 8086. but the 8086 cannot i'nterrupt the Z-80A. The secondary board interrupts the Z-80A and places the 8086 into a wait state during read/write operations to unique IBM-PC addresses. SINTR allows the Z-80A to interrupt the 8086 during timer tick interrupts (INT lCH).

There are four signal lines capable of ini tiating on ... board interrupts. depending on optional features which your 8086 l6-bi t board may contai-n. These interrupt lines are: the 8255A (PIO) ir

the 8087 numeric processor extension (NPX). the Z8530 (SCC). and the TMS-99l4A (GPIB). Note: When the secondary board is installed. PIO is driven by line SINTR (the interrupt signal from the Z-80A), and NPX is not applicable. as there is no numeric processor.

2-8

Attache 8:16 Technical Manual Theory of Operation

These interrupts can be masked by Port B Bits 0 - 3 of the 8255 as.follows: .

Bit 0 PIO Bit 1 ~PIB Bit 2 see Bit 3 NPX

An interrupt is allowed when the corresponding bit is set to one, and masked out if the bit is set to zero. Priori ty among any non-masked interr~pt is determined by software. Fifteen interrupt vector locations (FO - FE) are use~ Each combination of interrupting device vectors form a unique location as follows:

With SecondaryrBoard

Fl sec GPIB SINTR F3 GPIB SINTR F5 see SINTR F7 SJNTR F9 sec GPIB FB GPIB FD sec

With 8087

FO Fl F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE

NPX sec GPIB PIO see GPIB PIO NPX GPIB PIO GPm PIO NPX see PIO sec PIO NPX PIO PIO NPX see GPIB sec GPIB NPX GPIB 'GPIB NPX see sec NPX

Interrupt priority is then determined by which of the four routines each of these fifteen vectors indicate.

Interrupts are discussed in Chapter 3 of this manual.

TEST Circuit

The 8086 /TEST input, together with the WAIT instruction, can be usedf or synchroniz ing I/O to the NPX, sec, GPIB, or PIO. If Bit 4 of the 8255 POR.T B is set to one, the /TEST input is connected to signal line NPX BUSY, (Which NPX software expects). To use /TEST with other devices, bit 4 is set to zero, which essentially connects test to an interrupt request. By disabling 8086 interrupts and masking off all but the desired device, very fast transfers between the epu and the sec, GPIB, or PIO, can occur.

2-9

Attache 8 :16 Technical ManwU i'beoq of Operation

Optional Feature - Serial Port

The 8086 l6-bit board has provisions for an optional serial port, which uses a Z8530 SCC (Synchronous Communications Controller) chip. The following ports are used:

l44H A Control anq Status l46H A Data l40H B Control and Status l42H B Data

RTxCA is connected to Pin 15 (transmit clock).

TRxCA is connected to Pin 17 (receive clock).

Only the A channel of the SCC chip is connected.

PCLK is driven at 4HMz; The SCC's baud rate generator divides the 4MHz clock to provide a 9600 baud rate.

Optional Feature - GPIB

A TMS99l4A provides an optional GPIB (General Purpose Interface Bus) port. This GPIB port can be used to interface Attache 8:16 with the DA-lO Ha'J::d Disk Subsystem, a 10 Megabyte hard disk.

The following addresses are used as the TMS99l4A registers:

Address {hex} Read

180 182 184 186 188 l8A l8C l8E

2-10

Int Status 0 Int Status 1 Address Status Bus Status Address SWitch 1

Onnd Pass Thru Data In

write

Int mask 0 Int mask I

Auxiliary Command Address Register Serial Poll Parallel Poll Data Out

Attache 8: 16 Technical Manual Theo~ of Operation

Optional Feature - 8087

The 8087 Numeric Data Processor is a coprocessor that adds extensive high-speed numeric processing capabilities to the 8086. The 8087 performs arithmetic and logical operations on a variety of numeric data types. '

The 8087 cannot coexist with the secondary board. (the board which fits onto the 8086 l6-bit board and which makes the Attache 8:16 IBM comp;ltib1e). The 8087 is' an option available on the 8086 16-bit Processor Board instead of the IBM compatibility provided by the secondary board. A computer which contains this option is called an Attache 8:l6A. and must be specially ordered from Otrona.

The Secondary Soard - Overview ,.

The secondary bQard on the 8086 16~bit board is designed to allow hardware which is not IBM compatible to be IBM compatible. The secondary board intercepts any 8086 requests that can be unique to mM-PC hardware. and simulates this mM-PC hardware.

To accomplish this PC simulation. the Z-80A is interrupted during 8086 I/O reads and writes outside the address range OlOO-OlFFH. and during 8086 memory reads and writes inside the range BOOOO­BFFFFH. When tbe Z-80A is interrupted. the 8086 is set into a wait state (via signal SRDY). The Z-80A interrupt service routine processes the respective read and write. simulating the IBM hardware. and then rel,eases the 8086 from its wait state.

The process of interrupting the Z-80A during IBM-PC unique address calls is referred to as "trapping". The IBM-PC uses memory addresses BOOOO-BFFFFH for display memory and the 8086 16-bit board does not. so memory reads/writes in that range are trapped. The 8086 l6-bit board uses I/O addresses in the range OlOO-OlFFH. which the IBM-PC does not. so all I/O read/wri tes except those in the identified range are trapped.

Initialization

Both ports of theZ-80A PIO (U8) operate in MODE 3. i.e •• bidirectional bit-mode, and interrupts are enabled. (Port A is actually used as a 1-byte, 8-bi t, bidirectional internal bus, but the port is initialized in bit mode to simplify the interrupt schemes.) Port B has two outputs. Bits 3 arid 4. which are used to enable latch outputs onto the Port A bus. Bits 5 through 7 are inputs, used as the sources of interrupts. Bits 0 through 20f Port B are inputs which indicate to the Z-80A how to process the interrupt. ''. '

2-11

Attache 8: 16 Technical Manual Tbeory of Operation

Address ~

.. Decoder

Port B

Z80 Z-80A

P10 INT

8086 Address ..

Latch .. ~

-1 T

Address ~ Latch ~ Interrupt

8086_· Logic

0.....-

INT I-

Control

Data ~ Latch ~

I

Data a..- Latc,h ...

Secondary Board Block Diagram

Address Decoding

As the 8086 executes code, it places addresses on lines ADO through AD19 and strobes these addresses with ALE (Addre'ss Latch Enable, 09 Pin 4). The high- and low-order addresses are latched by U16 and U13 when ALE goes low.

The 8086 then puts data onto the ADO-ADIS lines, and continues operating unless the address is wi thin the ranges that must be trapped. If the address must be trapped, the 8086 is placed into a wait state. The 8086 data is held on the bus for a write operation, or the 8086 waits to read data for a read operation. Note that regardless of whether or not the operation is trapped, U13 and U16 will have latched the address before any wait state occurs.

2-12

Attache 8: 16 Technical Manual T.beo~ of Operation

Two sets of address decoding logic are provided on the secondary board, each to detect the occur rence of one of two trapping conditions (either an 8086 memory read/write memory operation within addresses BOOOOH-BFFFFH, or an 8086 I/O read/write outside addresses 0100-91FFHl.

'The first set of address decoding logic detects' memory addresses BOOOO-BFFFF {hex}. This logic consists of an LS20 (U6). two inverters (inU10 and US). and an LS374 (U12). If .the address output by the 8086 is in the range BOOOOH-BFFFFH, the output of the first LS20 gate is driven low. '

Signal /S2 at a high state indicates that the address is a memory address, as opposed to an I/O address. /S2 ANDed with the inverted output of the first LS20 drives the output of the second LS20 low if this address is a memory address in the range BOOOO­BFFFFB. This low signal is then latched by U12 when ALE goes low. The output of this LS374 .is the' Bit 7 input of PIO Port B.

The second set of address decoding logic detects any I/O addresses which are not in the range 0100, through OlFF {hex}. Th~s circuitry consists of two LSOO NAND gates (U10) and latch U12. The first NAND gate inverts AD9. thereby obtaining the proper level for the second NAND of 010.

If the I/O address is outside the range OlOO-OlFFH, the output of the second NAND goes high. This output is latched by the LS374 (U12) when ALE goes low. If the Pin 5 output of the latch is low, then the address is on the 8:16 board (i.e., within addresses OlOO-OlFFH).

The output of latcl1 U12 is fed back (via signal line /8~16I/0) to the 8086l6-bit. board to enable its address decoder when the address is on the 8086 l6-bi t board. I~ the output of the latch is high. then the address is not on :the 8086 l6-bit board and the 8086 address decoder is not enabled

Latch U121s outPl:lt is then NANDed with lines IOWR and. lORD by the LSOO (U4). IOW~ and lORD are the decoded and inverted outputs from the LS137 (U9). U4 consequently gene~ates a signal indicating an I/O read or write outside OlOO-OlFFH to Bfts 5 (I/O write) and 6 (I/O read) of PIO Port B.

Generating an Interrupt

The decoded signals /MEMACC (U12 output Pin 2. the decoded memory access signal within address range BOOOO - BFFFF). IIORD. and /IOWR are the three inputs to the Z-:-80A PIO which cause it to interrupt the Z-80A (Port B, Bits 7. 6. and 5 respectively). The PIO issues an interrupt if any of the three inputs go low. This interrupt to the Z-80A causes it to jump to an interrupt service routine.

2-13

Attache 8 :16 Technical Manual !heo~ of Operation

/MRD .. /IORD .. and /IOWR are decoded by U9 (the LS137) from 8086 inputs ISO (U9,Pin 3) .. /Sl (U9 Pin 2). and /S2 (U9 Pin 1). /MRD is output on U9 Pin 10. /IORD on pin II. and /IOWR on Pin 13.

PIa inputs IIOWR. lIaRD. and the IMEMACC sign~l are ANDed together by tw·o LS08s (U3). so that anyone of them going low causes the D input of Ul (half of an LS74 flip-flop) to go low. This input is then latched by the clock input (the output of the 8086 l6-bit board wait state generator U27 Pin 6 inverted by an LSOO {U4}). This starts a synchronizing chain of LS74 flip-flops. which finally gene.rates SRDY low .. setting the 8086 into a wai t state.

Decoding the Interrupt

with the 8086 in a wait state.. the Z-80A interrupt service routine may now read Port B of the PIO to determine which Bit (5-7) caused the interrupt. It also reads Bits 0-2 of PIO Port B. which indicates how the interrupt should be handled. Bit 0 (/MWR) indicates whether the interrupt caused by a memory address in the range BOOOO-BFFFFH was a read or write operation. while Bits 1 and 2 (ADO and BHE. latched by U12) indicate whether the data transfer was one or two bytes .. according to the table below:

ADO BBE Bytes Transferred ----- -----------------0 0 Upper-byte on ADB-AD15

Lower-byte on ADO-AD7

0 1 Upper-byte only on ADB-AD15

1 0 Lower-byte only on ADO-AD7

1 1 No data is transferred

An LS138 (07) appears as an I/O port to the Z-80A. It decodes the addresses of the PIO. and provides to the Z-80A a means to control the secondary board. The I/O map is as follows:

2-14

00-03H 04-07H 08-0BH 001 ODH OEB OFH 10-13H l4-l7H l8-lBH lC-lFH

CLEAR INTERRUPl' TO 8086 CLK Z-80A DATA INTO L(lol BYTE LATCH CLK 8086 DATA IN'ro U13 and U16 PIO PORT A DATA PIO PORT A COMMAND PIO PORT B DATA PIO PORT B COMMAND/ CLK Z-80A DATA INTO HIGH BYTE LATCH INTERRUPr THE 8086' UNUSED SET 8086 TO RUN STATE

Attache 8: 16 Technical Manual Tbeor:y of Operation

The Z-80A reads the address that caused the interrupt (latched in U13 and U16) by using Bits 3 and 4 of the PIO to enable the output of these latches, and then reading Port A of the PIO for the data. one byte at a time. It then causes the 8086 data to be latched into these same latches by doing a dummy I/O write to address 08 - OBH. The Z-80A can now use Bits 3 and 4 of the PIO Port B to enable the outputs of the latches, and then read the data into Port A of the PIO. one byte at a time •.

If the cause of the interrupt was an I/O or memory read. the Z-80A must write data into 014 and U15 for the 8086. This is a one- or two-~te transfer, determined ~ the state of ADO and BHE as read from the PIa Port B (listed in the preceding table.) This is accomplished ~ putting the data out on Port A of the PIO and latching it with a dummy write operation to I/O address 04-07H (for low-order bytes) or 10-13H (for high-order bytes). This data latching also sets Ul (the lower half of an LS74). which enables the output of these data .latches onto the 8086 data bus.

Releasing the Interrupt

After the appropriate service has been performed. the Z-80A releases the 8086 from its wait state ~ doing a dummy write to an I/O address in the range lC-lFH. This dummy write clears Ul (upper-half of an LS7 4) which clears SRDY.

The Z80 then executes a return from interrupt instruction. The 8086 now finishes the cycle it had started by reading the data that is on its bus from U14 and U15. if the operation was an 8086 read. or simply moving to the next instruction if it was a write.

The output of the LS08 that clocks the lower half of the LS74 (Ul) goes low on either an /IORD or a /MRD. This readies the clock input for the positive-going transition chat clocks the flip-flop. When the 8086 continues with its read operation. it brings /IORD or /MRD high. (the signal that caused the clock to go low). This low-to-high transition clocks the grounded D input

. to the output. causing /0 to go high. This. in turn. disables the output of U14 and U15. which completes the cycle and frees the bus. The next 8086 instruction is handled in the same manner.

To allow the Z80 to interrupt the 8086. the Y5 and YO out'puts of the LS138 (07) are tied to the set and Reset inputs of half of an LS74 (Ull) (and the 8086 must set 8255 Bit PBO high). This flip­flop allows the Z80 to set the interrupt request to the 8086 by writing to addresses 14 - 17H and to clear the request ~ writing to 00 - 03H.

Additional logic on the secondary board is the LS08 (U3) on the Ml input to the PIO. Since the PIO interprets /Ml without an /IORD or/RD as a reset. the LS08 combines /RES with /Ml to reset the PIO when necessary.

2-15

Attache 8 :16 Technical Manual 'lbeoq of Operation

25-Line Circuitry

The 25-line modification is a small circuit board with headers that fit into sockets U422 and U423. U422 is a 74LS157 which mul tiplexes the display's line number. The board contains this relocated mul:t:iplexer (U422) and a 6349 PROM which replaces an S283 counter (U423).

The S283 adder is used to remap the line and column address bits and output the unique character addresses' to the character and attribute RAM chips.

The 25-line modification replaces adder U423 with a 6349 PROM, encoded to outp~t to the character RAM the proper address for the line and column position of each character to be displayed.

A 25-line, 80 colmnn display· contains 2000 unique locations for characters (25 x 80 = 2000). The binary representation of 2000 is 211, which means that 11 address bits are required to address all 2000 locations. However, representing the column positions (80) in binary requirefi. 27 (seven address lines) and the line number (25) requires 25 (five address lines). This .resul ts in 12 address lines, even though the upper address combinations of the columns and lines are not used (27 = 120, 25 = 32». The PROM is used to remap the 12 lines into 11 for optimized usage of RAM.

The PROM (U423) remaps the address bits by combining the upper three column address bits with all five line number address bits and reassigning the otherwise unused address combinations. Therefore, the lower four column address bits are allowed to input directly to= the attribute and character RAM chips, while the PROM provides unique 7-bit outputs to any required address combination on its eight input lines.

High-Resolution Graphics Board

The high-resolution graphics board doubles the memory of the graphic RAM and provides the circuitry nec~ssary to select between low-resolution and high-resolution graphics.

Hardware Modification

Several chips ar,e removed f rom the Z-80A Main Processor Board, and are replaced with a graphics high-resolution board which plugs directly into the emptied chip sockets •.

2-16

Attache 8:16 Technical Manual Theo~ of Operation

The modification removes the following chips: U703. an LS166 eight-bit shift register which serially outputs data to the display; U426. the LS13S address decoder which selects one of the graphic RAM chips (or the CRT controller. Attribute RAM or Character RAM); the five graphic RAM chips (MK4S02's U704 -U70S); and U416. a 2732 EPROM character generator.

The graphics high-resolution board contains three graphic RAM chips (HM6264's U6. 07. and US). two S-bit LS166 shift registers (U3 and U4). an LS138 decoder (U2). AND gates (LS08 US). an LS153 mul tiplexer (Ul). and a 2764 EPROM (U4l6). The board connects to the Z-80A Main Processor Board" via connectors Jl through J7. Connector Jl fits into the U426 socket. J2 into the U703 socket. and J3 into the U70S socket, and J4 through J7 are hard-wired to the appropriate signal lines on the Z-SOA processor boar~

Address Decoder

Graphic RAM Display

Circuitry

High-GOOT -

I or GOAT Low- ,..--Resolution

A12 Shift ~

Register Multiplexer

Z-80A

." -

High-Resolution Graphics Block Diagram

2-17

Attache 8:16 Technical Manual 'J.'heory of Operation

Graphics Board Theory of Operations

The high-resolution graphics board replaces five 2K b¥te x a-bit graphic RAM ch.j.ps with three 8K byte x a-bit chips. Since the graphics memory is doubled, the graphics board requires an ad.di tional address line, Al2.

Address line ~2 is input to graphic memory through multiplexer Ul. This allo~s graphic memory to be selected by either the processor or the CRT (Cathode Ray Tube) controller. The CRT accesses graphics memory to display the current data via Ul input line RO, and the processor accesses graphics to update data via line AlS. .

Decoder 02 provides the chip selects to address RAM chip U6, U7, or 08. Additionally, U2 can select the at.tribute RAM (U432) or the character RAM (0433).

MUltiplexer Ol's enable line, Pin 14, selects between two 8-bit shIft registers, U3 and U4. 03's input lines are coupled such that dots are addressed in pairs, 'as opposed to individually. 04's input lines select individual dots. When Ul'S Pin 14 enable is high, 03 is selected for medium-resolution. When Pin 14 is low, 04 is selected and high-resolution graphics is selecte~

The shift regis~ers (U3 and U4) are clocked by GDOT, which is input to the board through J2 Pin 7. Each GOOT clock pulse is the time that it takes to write one dot (pixel) to the display. The Pin 15 input to 03 "nd U4 select parallel load or serial output. When Pin 15 is low, the selected register loads data in parallel.

When Pin is is high, the selected register shifts serial graphic data out of' Pin 13. to J2 Pin 13, which forms the display signal line GDAT, a direct output to the display interface circuitry.

Additional Circuitry

In addition to the circuitry provided by the high-re~olution graphics board, E.PROM 0416 on the main processor board is replaced.

The new character generator EPROM (0416) contains the IBM character set, in addi tion to the complete ASCII character set and al ternate character sets (Greek, mathematical symbols, business form and graph drawing ~bols, German, Spanish, French, Italian, SWedish; and other alphabet symbols.)

2-18

+! V

... - ta

- ~".T ~ ..... L33

... v ~

--t

S7DY

'P; FIC 5..---..

EFI UII ~ .. 4 LS08 C5N 82BAA

t:::)-!!!!!T ,.....! RDYI

Fa-' 22 _ MUl( 3

ENI ROY 211AIT 8 RDY2 CLK "'If HI

:::::RAMCYCL£ I 7 EN2 RST ItO IRI!!!!IET 21 - 311AIT -~ ASN asc ~ ~/RES it ...,.. RlilES ~~~

17 16

rl 2~

t: It:. "!!

RI R2 !!IiO !!Ito

:

~BUSY ':" ':"

RESET

eLK

CoL 22 HI , 2i

INTR ADI 3!!! &Iua

NMI ADt_ 36 &!lU

TEST ADI 37 UU,

38_ In •• MN/Ml( ADI ROaTi ADI

39 An ...

ROaTO ADI 2 Afto ..

ADI a Aftd

ADI. iA An., !!I An .. AD 11 B AD10 &!lOft

AD ~ &l1li

8 lIIIl AD 9 Aft7

U5 AD7 10 &NI 8086-2AD6

AD Lt .LIllI

AD 12 An ...

AD 13 AmI

AD LA An,

ADI It!!! Aft 0

ADO Iu; Ann

LOCI< ,29 IUIO<

BH .. J_

RD 321A1l ~a J .. ,.

52 ~7 I!!IO 51 26 l!!Ift ROY SO

CLI< OSI 4 D!!IO

RESET OSO 12!!! a!!lft

13!!! Aftoa AD1_ 136 &!lUI ADI 137 AII47 8USY AD17 138 &110" RQGT1ADI 139 All til ROaTO ADI i2 AIIU ADI 13 Ano ..

ADI &lIt:l 4 ADI

I!II AIIOO ADU

18 ADtO All Oft

AD 17 Alia

AD 8 &1111

UIO AD7 9 A117

a087 ADS to AlII'-

,11 &1111 AD!!I AD 112 &11.

AD3 i13 AIl3

li4 All" AD2 Ii!!! .lilt ADI 118 Allft ADO

aHE ..::IA / .... ~

INT ::a2 NPX'IIIT :aa /!!I" S2 27 J!!It SI ~8 /!!Ift ROY SO

CLK OSI 4 a!!lt

RESET OSO 2!!1 aso

....... ;:..... ....... .e --. ;:..... .-::.... ::.... ::.... ;...

,;...... .......

,;...... ....... ;..... -;..... ~ -,.,...... ,.,...... ....... .......

,.,...... I'""'\,

,.,......

--.'

41-051209 Rev. B

PROCESSOR

16 BIT CPU

CPU

OTAONA ADV SYS

1 OF 8 A1

... ~ ..... ~---. -- ---.--"---'.--.. ------.---'------~--------,

"'-If 9 20. 8 ,.1"'-11. L U27

:= := ....,

L.J' ---:= -

I

-L.J'

:= -:::-,=: 1-IL...J'

I i

...... -L.J'

::::: -=:' =: L.J'

L..I

rS04 I - LSI7!S 1!5 3WAIT ~I -l...uDa~~O ""' .. 4~~ 40 40

2WAIT - 30 '10 -'] tS84 ..1.2 0 30~ IWAIT

.....L 20 20~

U4-9 (2nd Bd) -~ K

20 .S

lOCi CJ--L 4 10 A

10

rD ~ 1

IALE

~H t~R.2e 12 A_~ --LS32 S04 -U2B

+S-'-LS137

~' !I

~1 V7

~ 2 V6 .If NT .. .......... • L V!S IIORD '..;::; : .1

V :'lI! .I .... A ....--V /IDWR ~ /!l1I :J V2 :13 -.I!1'. :I

U :1. 4~ .I!1l1! I :.11 ,-1- ~ .1'S1I8 ... VII

+~ V

i--1- 4

-:I ~ ... ' .l!DI-_1!. ...2. r P O~ ~A12 _21 Ult '~E ILSlo/"' U62 ..1L.... .E

13 ...... nr.1 J( ~ I, i..S74 f:P- +!5V ...... 19 112732 n-WLD 10 /64 ...... r R 0 , .... '" 22 9

11 .. 11 23 I~ 1 8 ~

..... . 1 7 07 17 ADI!!

UI8 r---L 18 LS313 19 aua ...1.Q.1iJi9"'\.a At.

17 80 80 16 IAIB ~ AtO 70 70 L.~

..u~o 60~

...u~1 ' ~ -L 0 !SO~ ':.. .1_ .L 40 40 S IBIIMf ':...

4 3D 3~~ .. , ~ ",. 20 20 ... 11 3 10 10[2. BAtll ~

-eN OF.: -ul 1k

UIS LS373 [19 11,,13 t"""\ .. nl" ..l8. 80 80

,nt, 17 116 &Au. ~ 70 70 An,1 14 ° 60

I t!'l .... 1 ~

AolQl 13 I t2 II"UII. ...... ° 50 ADS ..8. 19 aA S .."......

"oS 40 40

[s IIA S ...... 7 30 30 AD" 4 15 aAg .."...... 20 20 ,n .. 3 1:0 ' .... " ......

10EN..O.J O

ull~ UIY

AD.3 ..l8. LS373

119...a...3. .."...... 80 SO An III 17 [tS .... ~ ...... ° 7~ An.IS 14 [t!'l II .. IS ......

-.13. ° 60 112 BA I .,;:; AD I, et !SO An2 8 19 ... 2 ...... I .. 011 7

40 4~ Is 11 .. 11 .=:, 30 30

AD4 4 20 20 1!5 ~ ~

3 12 11,,12 ......... An12 lo"N aJO -Ullk

•• J.

" .. 7 2 6 06 IS AD •• ~ 1!5 ADI3 ....

!S O!S ...... 4 114 ADt:l ... 4 04 I'... An •• .A" !5 ... 3 03 IH ADlO ...... S

02 1

... 2 I till ADII " .... 1 01 .... 8

eCECEoD 19 ADII

I~C

-i:BA12 U4 .Ji..E 21

AU 2732 ~E .+SV IIAl' 19 AUI 164 n . ..AULD IIAIO _22 1.9 • ....... 2~ "SV 1.8 "1.011 _1 1.7 07 117 A07 .. .. 7 2 1.6 06 " .. II 3 1.5 05 BA!! 4 4 04 II .... !5 ... 3 03 ...... S 1.2 02 ...... 7 1 01 ... B

AeCEC'.EoD

lSr«

. 41-051209

CONTROL 16 BIT CPU

CONTROL

[16 ADII [15 lO!!

114 AD. 113 AD3

[tt ADa [Itl AD'

19 ADO

Rev B

,OGlC OTR aNA

AOV SYS 2 OF, 8

A2

U2S 10.6 13

LS257

~ 14 48

4Y 11~ MA0 6 RA25 -41. y ~ ~ -

_ liAS 10 8 19 MA2 a R27

-C> - .... 10 11 3Y 31. 'V~

::::: .... 7 8 8 3 R2 4

J""">. .::: !A14 !5 2Y 7 MA6 21. v ::::: 11 .. 8 ~ 18 MAl 2 R} I -IIAI3 2 1Y 4 - v ....., -- 11. GBI 1\

15 i U26

- 10&::\ _13 LS257

4 R3 3 ::::: IIAI6 _14 48

4Y Ii::! MA5 J""">. 41. 'v -...

.... 2 '10 6 ~R;' 5 ::-' IIAI5 11 38

3Y 9 MA3 -C> A 'V ...

·,d 6 ~8 2Y 7 MA7 7 ..... RK a ..r-.. .......

IIAIl !5 A v - .,,4 ~ I RX ~2 ::::: !A12 2

18 1Y 4 M .. 4 -Vv- ....., iAG'B/A

- R~

15 1 ... " -I'

UI5 B '.' 13- LS393 0

~ U24

C

~ LS244 13 MAS 2.....,.,.1 R2 B BA BY D

~ !; 171. 7Y I~ MAIO 3 ..... ' 4R2 -

R A "-t I 2R3 -::::

A 6Y 7 MAA

~ eA 5Y I", MA7 7 BR3 ;:::.

1 Ii::! MAO 60A 5 R2 -

6 41. 4Y

114 R: ~7 R2 ~ 31. 3Y MA2

UI5 ~ 4 118 MA!I 4 3 R3 ..r-.. 1 LS393 0

~ 21. 2Y

liB MA3 6 5 R3 -; 4 r 1AH : ~r.1 Y .....,

..r- ,,13 i 11-, R

21

~-i U29 3 c .. s 2 LS32

U72 ~ a~~. I LSOO 4 U29

.... " 5 LS32 J I:~: :! ~U30 II ~ ~11~

SOB ~ ~

..... Q 9~: R72 n...sL_tt-~!-i1U52 ,..------------:------;

SA II B~ LSOO soe ,"''''' 3~' l!~ ____ _r==dl~==~~~~k=~=====bd;~RBA:S~;~~2~jJ~~~~~~ I RAS

-kO ICLK I~ s3Jle

11-il-_++-+-..J1~::> p 9 RI"F -U23 G ...

18_ ICASH

'''A''L

IRASS

IR .. S"

Lu.~ LS;4 G...s IREF J""">.

+!lV 113

.MHZ _

~KI 41-051209 I Rev. B

MEMORY CONTROL OTRONA

16 BIT CPU ADV SYS

RAM 3 OF 8 A3

---= = ..::: -

.. .&7 9 7 U45

...... 13 8 4164

.... to IS

..... 11 A4

..... t2 3

...... s 2

..... 7' 1 DI~

... ,,!II ~

lC~swl"~~9 11513 4

.. .&7 9 A7 U44

...... 1~ A6 4164

.... II 10 IS

..... it

..... 12 4

...... 6 3 ....IIII~1....!A2

....., 1 DI~

.... ft!5 ~ IE~SWEF~~ 11S13 4

... ., 9 7 U!S

.... t~ A6 4164

..... to AI5

..... 11 A4

..... t:! A3 ....... S 2

.... ., 1 Dlli--

.... ,,!'i AO DO~ IF.ASW~iA!

lIST 3 4

.. .07 9 7 US!! ~II 13 6 4164 .... II 10 15 ..... 11 A4 .... " 12 A3 .... 2 6 2

--"Ai _7 1 DI~ .... ft !'i 1'4

r.~~w .. ~~91-i-=-11513 4

.. .07 9 U64

.... II 13 ~ 4164

_MAlI .10 ..... 11 ! MA3 12 3 .... , s .... 7 .... ft !II

.. .07 9 U47

...... i~ 7 4164

...... 10 :

.. ,.... t t

.... " 12

.... , R

.. , 7

.... ft !II

4

3 2 1 Dlf2-

r.2sw~~91.a.. 11513 4

.. .07 9 U46

.... II 13 A7 4164

..... to A6 .

..... 11 AIS

..... t~ A4

...... S A3 A2

.... 7 Al Dlli--

... n 5 '~2sw~a9\.1.L. 115T 3 4

.. .07 9 U37

..... t"l A7 4164

.... to A6

....... it AIS

.. ..,. 12 A4

.... " S A3

.... ., A2 I",

.... "15 Al Dlr.;-...!Ij!~~1~2SWE:F~~~

1ST3 4

.... , 9

.... " 13 MAli ..10 ..... 11 ...... 12

U'S7 7 4164 6 IS 4 3

.... " 6

.. At .7

.... n !'i

2 1 Dlf2-

E2sw~~9~ 1151 ~ 4

.. .07 9 U66

...... 13 ~ 4164

...... ..1.0 15

.... 11 4

.. ..,. 12 A3

..... S A2

.. 7 Al Dlli--

... n 15 It 4 1~2SWEF~r--11513 4

.... , 9 7

.... " 13 A6

...... 10 AIS

~ ... ..1.1 A4 .. ..,. 12 A3 ... " S

.... 7

... n !I

U!57 4164

.. .07 9 U34 __ ~_9 A7 US4 .. .07 9 . U36 .. .07 9 A7 US6

.. All 13 A7 4164 ..... t~ A6 4164 .... II 13 A7 4164 .... 13 A6 4164

~10: ~..1.0~ ~10: ~10~ .... 11 A4 .... 11 A4 ..... II A4 ..... 11 A4 .... 3 12 A3 .. A3 12 A3 ..... t:l A3 .. ..,.12 A3 ... , S A2 MA:! 6 A2 ... , s A2 ..... S A2

.... 7 1 Dlli--' ~A 7 A1 Dllz-- .... 7 Al DI~ ... 7 A' OI~ _ .. aA! .......... ft!5I1......1AO 001 t 4 .... ft!5 0 oollL ... n 5 AO DOl t 4 .... ft .5 ~ It 4

Ie: SWE:F A'!~O ADS ~ASWE:F A'! AD2 .03 I~ASWE:FA!r--:;; • .lOll 1~2SWE:F~9~1I 15 3 4 lf3 4 1513 4 1513 4 AD

f-. ,

12

+5V

to .

P Q~ U62

_ feLK II LS74 .,a MU~ C>--~~~~~ Qo---~}

13

41- 051209 Rev. B MEMORY AND LOGIC

16 BIT CPU

RAM LOW

OTRONA ADV SYS

4 OF 8 A4

.... ., q 7 U49 .... ., g

7 U69 "&7 g 7 U!51 .. &7 g UTI .=.. .. & .. 1:;1 4164 ..... 11 13 4164 ,,&11 13 4164 ,,&11 13 7 4164 A6 6 6 6 - .. &!'! 10 A!5

...... '1O !5 j!A!l10

!5 ""'!I_10 !5 .. " .. 11 .... , 11 .... , t t .J!M.i1 = ...... ,,~

A4 .... ~ 12

4 ..... ~ 12

4 ..... ~ 12

4 A3 3 3 3 - ..... " s 2 .... " S 2 ~_6 . 2 ~~ 2 ..... 7

1 or ~ ." 7 1 or ~ ..... t 7

1 or ~ ..... ~7 1 or I~ - ..... 0 !!

IC~SWEF~~ .... n !!

W::~SWEFa? _MAo_5 .

C~SWEF~? .JWl~

~., ... ~<OO

151~ 4 15T3 4 15T3" 4 1513 4

..... 7 g A7 U48 " ... 7 9 U68 "A7 9 A7 u-so "AL9 U70

.. All 13 4164 ...... 13 7 4164 ...... 1:;1 4164 J!All...1.3. A7 4164

.. A!I 10 A6

.... !'! 1.0 6

..... !'! 10 A6

.. A!I 10 A6

A5 5 A5 A5 "A. 11 A4

....... 1.1 A4

....... t 1 A4

..... , 11 A4

MA3 12 A3 - ..... ~ 12 3 "A~ 12 A3 MA~ 12 A3

.... " s A2 "A" 6 2 "A" 6 2 ~_6 A2

.... 7 1 OI t: "At 7 1 OI t: "A 7 1 Dr ~

MllJ_ Al or ~ .. AO !! .... 0 !'i .... n !'i .JWl~ ~~SWEFa? IC~SWEFa? ~~SWEF~? I~~SWEF~~ 15 3~ 4 "t3

" 4 1!513 4 1:13 4

.... 7 g U39 "A7 g U!59 "&7 g U41 .. A7 9 U 81

"All 13 7 4164 "All 13 7 4164

"All 13 A7 4164 "All 13

A7 4164 6 6 A6 A6

.... !'! 10 5 .... " 10 5 " .. !'! "0 AS .... !I 10

A5 " .... 11 A4 ..I!6L11. A4 "A. 11 A4 "A. 11 A4 "A~ 1~ A3 ....l!AL1it A3 "A'" 1~ A3 ..... ~ 12

A3 "A" 6 2 -I!A.L§.;.. A2 "A2 6 A2 "A2 6 A2 .... 7

1 or ~ .... t 7

Al or 1~4 _MAl _'1. A1 or ~ ..Hll~ Al or ~ "AO !! ..... 0 !! .. AO !5 MAO !5

~~sw~Fa9 ~SWEE~9 ~~SW.EE~ I~~SWEF~O 15 ~ 4 1513' 4 1!51 3~ 4 1:13 4

"A7 g U38 ..... 7 9 U58 "A7 9 U 40 -"A7 9 7 U60 "All 13 7 41ES4

"All 13 7 4164 "All 13 A7 4164 "All 13 A 4164

6 6 A6 A6 "A!I 10 5 "A!! 10 A5 "A!! 10 A!5 MA!! _10 AS " .... 11 4 " .... 11 A4 " ..... 11 A4 " .... i1 A4 ..... ~ 1~

3 "A~ 12 3 .. &~ 1~

3 "A:!! 12 A3 "A" S A2

.. A2 S 2

,,&2 S A2 ",A" 6 A2

"At 7 1 or ~. "'A 7 1 or ~ "AI 7 Al or 1~4 ". 7 Ai or ~ .... 0 !'i "AO !'i ", ... 0 !! "AO !S

Ic~SW~Fa? ~ rc2SWEF~0 1~2sWEF~0 1~2sWEF~? 15 3 4 15T 31 4 1sT 3 4 1!S13 4

!"MAA "'Dt!! _ - !eASHA ~.~ ....... !AAStA .01:!!~ - IRASOA

.AIl.1.2....r> ....... ADIL:::::

.A.D..l.Q...r-, -- ... 09 :::::

.AllIl. ........ .......

41-051209 1 Rev. e RAM HIGH DATA

OTRONA 16 BIT CPU ADV SYS

RAM HIGH' 15 OF E AS

'-' .--; .... ......:.. -_.& .,": ""4:IESE1PC7f.o11o.¥-O--------... aA" 8 Al PC6f.o1u ..... -----___ +_.

- IlAt 9 AO PCSif.ol,1.--.2-------..., - nMn ~ 0 PC4P! 11.&..3 _______ __++. - nllwa ,::Iii: R PC3 7 pc:!!

~FS PC2~ PC 11-""'- ., PCO I14 ,DSR

-QJ2 3 .12 J2 2 -12 --<.12 1 ;§'250 .. 5 .1248

.1246 "247

- .1245 .1243 U6 PB7~ --

B2ss~::i~12~3-------_4~~ PB4122 PB.

PB31:a PIl:!!

PB2120 Pil"

PB1119 Pill

: "'].2

(.1249

27 28 7

paolle PBO 1~7 I! r

.... D714

1111 ..

II!! ..

n ....

II n ....

II

PA713B PA6139

PA5i~.~A==============:jttta~---~-W~---~ PA~ PA3~11~-------_4~~ II""

I

.J2 27

J2 23

.J2 22

J2 21

J2 20

..J2 24

34 1 O-Ailll.-+-..&!!"bo

n ... ~.J2 26 PAa!~lat:============:::jtt~-----~~-~-~ PA1~ nn .. ~.J2 as PAO~14~-------__+~~-----~a-~+_-_<

u .. J5 14 loS367 12 A" 6Y~

All to A 5Y l9

4A 4V

U42 101L loS 139 ; 19

r-"'C G ~~~ IGPI8_

_BA 7 1~ 8 V1L!1 ~ .. cc_

=8A 16 14 A VO~ -

;,

.12 7'-'>--..i.·YI!. .... - __ -.:.. ___ -.;..,

.12: ,.... l u22 w..... .". I 2 loS'138 I~.,

.I 2 9'- 14 ., .. t--=-... ~ 1 Y7 P':-

.12 :~ All .. !5 U2~ s ~IU21 \.....fi 4 28 Y6~

.12 ~ • ., .. rS04 r-~JloSagr ~~2A ~~~

ax B 3A 3V 7 .... 4 A avis

"" 2 I~ 1AGH 21V

111!

D llNTA I

U12-5 12nd Bd'

.12 4::'" ~Tn""t:I.. J ~ Y3~ Ya~~~-------~

23' 1M.. 2 Yl~ .I "'.... "I 1 A VO~ .123) ::: I .l2~4) I .12 a ~i~2 ~4=-,_" ----If-'

... PAO 12 P GIL US3

---1.l. > loS: 4 G...B IRES

l J3 ---_ .....

41-051209

ATTACHE

16 BIT CPU

INTERFACE

AD3 AD:! AD' 10110

--:=::.

-

A6

U20 RI +5-- lA';': 3 3 4 .. prBr"T .-.

v~~ V 504

...... ~MHZ 18 TM59914 129 IRES tQ..

8 5RQ 12'" - a

E5ETATN 127 CCGFEOI ...... IGPIB 3 12S

IIDA~Dt"FU2~'2 '-? CE CAV

I:>~ :::::. WE NRFC

124

A3 r5048 BINIIOAL

123 52 IFC 122 SA 7 51 AEN ...... BAS 6 RSJ C.::JNT ..3':--

~ '2 INT TE AD?

0'0101 38 - ADII 16 01 010 37 ...... ADS 15 02 0103 36

AD~ 14 35 .:: AD3 13

03 010 34 - 0.4 010 33 AD2 12 05 0106 :::::. ADS II 06 0107 32

10 31 ADO 7 oloe -

l

+5

f. Rl

SCCINT 2

2

"7

U2

Q-'- IPSA 'i" 12

C7

1330 L4

." -5RC ... AT'; " · ~ EOI :-

". ;: OAV

.;: '" NAFO .- ~ NeAC . ", IFC

.. '.9 REN " · . CU32

E 7!SUit

A +5 B C' Gnd. I LL U:33

11 IT E 75 USO E

12 e ea lg '.3 7 I!I '" • 4 6 I!I ". Ie

~ e: ,I . ;: .. 1"

4 e' 3 e 4

19 i3 2 a- il ~9

S~ :::

:

II

C!

,.-. .: I33~

L4

141-051209 . GPIB/SERIAL

16 8IT CPU

:::;0

1

I

I

I I I

I

3 10

3 11 ~. .... , ....

....

....

....

'<' '.

....

3 5

3 6

3 7

:3 8

3 9

3 17

3 :8 ~. ~

'<'

4-'<'

....

3 19

3 20

~ 21

;5 22

3 '<'

;, ;, ....

;, ;, ....

:3 2

3 3

3 4

'3 13

3 14

3 15

'3 16 1', ....

f8'" 3 24

7 3 12

~: 2

3

25

23

f: 1

7

.... 4

~I 5

8

20

~I 6

R~v a I/O

OTRONA ADV SYS

7 OF A7

~5V L6~12 LS .... 12

I I I I

,-

41-051209 IRev B

BY-PASS CAPS

'16 BIT CPU OTRONA AOV SYS

BY-PASS 8 OF E AS

I I I·

I I

i I I I I ! I, I

I I 1 I

• I

I I '. "', .

1 I. ........

1 1

1+ __ -I I

I I '_--:--'-_______ -:-1--.:.1 __ • ______ •••••

J 1 I

1" I .. ~ti '5

'l I I liS

Ii I ': i ' I L- _ I

!~~I 1

I uS

,,,,"0 I .3

I 11010 ....L 1 I I

1,11..;,.1

SIJ(r1\ 0- .

,~,~-I I ~:~ ,~~: GoZ4 & I J 2 11P1~1~ t..l$

IJ? , LllZe I

C !-'i ?=----.,-,-<<:I.' IlrlM

;1: .. : ;T~ ---____ 1, SIli>'I

---- UZ1-E,

I~ BIT <;(COijDAf.'1' ellAID \IV C.

ADVANCED SYSTEMS CORP. A9