org remarks

1Org remarks• Parts of the book which can be read:

– 4th edition:• Chapter 1: pages 3-31• Chapter 2: pages 35-91• Chapter 3: examples 3.4 and 3.5; pages 115-139• Chapter 4: pages 149-170• Chapter 5: pages 207-222

– 3d edition: • Chapter 1• Chapter 2: pages 29-65; sections 2.7-2.9• Chapter 4: 141-166• Chapter 5: 201-233• Chapter 6: 241-258

Digital Techniques Fall 2007 André Deutz, Leiden University

2Onto Our Simple One-cycle Instruction Processor

• CLUs: Continuation of ALU discussion

• CLUs: discussion of algorithms and hardware for multiplication (and discuss the idea of Booth’s algorithm)

• Sequential Circuits: Ways of clocking flip-flops

• Von Neumann Computer Model

• Implementation of the fetch-part of the eternal von Neumann cycle


3

An old acquaintance: processor-project assignment 1 (1.3)


0

1

2

3+

2

a b c_in k_1 k_0

c_out

r(esult)

1-b

it A

LU

as

spec

ifie

d in

1.3

4An old acquaintance: processor-project assignment 1 (1.3): 1-bit

ALU


0123+

2ab c_ink_1 k_0

c_out

r(esult)

Let us find another implementation Of the 1-bit ALU by constructing The Truth table for r(esult) and c_outSubsequently read off the canonical Sum of minterms for r and c_out, simplify this sum With the Quine-McCluskey Algorithm.Convert the minimized sums into LDs.

5


1-b

it A

LU

sp

ecif

ied

in 1

.3T

T f

or r

an

d c

_ou

t

6


Canonical sum for r(esult) and c_out

We continue with r:

7


Simplification of the expression for r by Quine-McCluskey

8



9



10



Selection Table No 1 for Quine-McCluskey

m2 m6 m7 m9m10 m11m13m14 m17 m19 m21 m24 m25 m28 m29 m31

00010

00110

00111

01001

01010

01011

01101

01110

10001

10011

10101

11000

11001

11100

11101

11111

1 0011_ v v2 010_1 v v3 0101_ v v4 100_1 v v5 111_1 v v6 0_ _10 v v v v7 _1_01 v v v v8 1_ _01 v v v v9 11_0_ v v v v

11


Selection Table No 1 for Quine-McCluskey

m2 m6 m7 m9 m10 m11 m13 m14 m17 m19 m21 m24 m25 m28 m29 m31

00010

00110

00111

01001

01010

01011

01101

01110

10001

10011 10101

11000

11001

11100

11101

11111

1 0011_ v VO

2 010_1 v v

3 0101_ v v

4 100_1 v VO

5 111_1 v VO

6 0_ _10 VO v v VO

7 _1_01 v VO v v

8 1_ _01 v VO v v

9 11_0_ VO v VO v

Simplification of the expressionfor r by Quine-McCluskey

12


Selection Table No 1 for Quine-McCluskeym2 m6 m7 m9 m10 m11 m13 m14 m17 m19 m21 m24 m25 m28 m29 m3100010

00110

00111

01001

01010

01011

01101

01110

10001

10011

10101

11000

11001

11100

11101

11111

1 0011_ v VO2 010_1 v v3 0101_ v v4 100_1 v VO5 111_1 v VO6 0_ _10 VO v v VO7 _1_01 v VO v v8 1_ _01 v VO v v9 11_0_ VO v VO v


The red one are the essential prime implicants

13


Selection Table No 2 for Quine-McCluskey (for this example the last one)

m1101011

010_1 v

0101_ v


14


prime implicants:a b c_in k_1 k_0

0 0 1 1 --- a'b'c_in k_1by selection tables we conclude: essential prime

0 1 0 --- 1 a'bc_in' k_00 1 0 1 --- a'bc_in' k_1

1 0 0 --- 1 ab'c_in' k_0by selection tables we conclude: essential prime

1 1 1 --- 1 abc_in k_0by selection tables we conclude: essential prime

0 --- --- 1 0 a' k_1 k_0'by selection tables we conclude: essential prime

--- 1 --- 0 1 b k_1' k_0by selection tables we conclude: essential prime

1 --- --- 0 1 a k_1' k_0by selection tables we conclude: essential prime

1 1 --- 0 --- ab k_1'by selection tables we conclude: essential prime


15


Construction of LD for r:

16

A more realistic ALU


17


A more realistic ALU: the MSB slice

18


A more realistic ALU

carryOut

19


Bits have no inherent meaning: operations determine whether they are really ASCII characters, integers, floating point numbers …

The previous slide (the ALU) makes this point quite tangible! The choice of operation will determine whether the bitstrings a_3a_2a_1a_0 , b_3b_2b_1b_0 and the output bitstring result_3result_2result_1result_0 are viewed as two’s complement (numbers -8 through +7, for a 4-bit ALU) or as binary (numbers 0 through +15).

Answer to the question of Lecture #1:

20


Multiplication: towards Booth’s Algorithm

21


64 bits

64

64 bits

Shift left

Multiplication: first attempt

64

32 bits

22


Multiplication: second attempt Hardware:

23


Multiplication: second attempt

24


Multiplication: third attempt

25


Multiplication: third attempt

26


•What about signed multiplication?•easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps)•Booth’s Algorithm is more elegant way to multiply signed numbers using same hardware as before

Multiplication: Booth’s algorithm

27


Motivation for Booth’s algorithm

28Booth’s Algorithm Insight

Current Bit Bit to the Right Explanation Example

1 0 Beginning of a run of 1s 0001111000

1 1 Middle of a run of 1s 0001111000

0 1 End of a run of 1s 0001111000

0 0 Middle of a run of 0s 0001111000

Originally for Speed since shift faster than add for his machine

0 1 1 1 1 0beginning of runend of run

middle of run

29

Booth’s Algorithm

1. Depending on the current and previous bits, do one of the following:00: a. Middle of a string of 0s, so no arithmetic operations.01: b. End of a string of 1s, so add the multiplicand to the left half of the product.10: c. Beginning of a string of 1s, so subtract the multiplicand from the left half of the product.11: d. Middle of a string of 1s, so no arithmetic operation.

2. As in the previous algorithm, shift the Product register right (arith) 1 bit.

Multiplicand Product (2 x 3)0010 0000 0011 0

Multiplicand Product (2 x -3)0010 0000 1101 0

30


31

Sequential circuits

• Ways of triggering flip-flops– Whenever the clock is asserted (level sensitive)– Whenever the clock changes state (edge-

sensitive)– Capture data on one edge of the clock and

transfer it to the output of the following edge(i.e, master-slave flip-flop)


32


33

The von Neumann Model of a computer


34


A typical “desktop” system:

35


Where is the processor?

36


A look at the motherboard:

37


Basic functional blocks of a simple computer


38Basic functional blocks of a simple computer

• The CPU, or processor, consists of a datapath and control• The datapath performs arithmetic and logical operations

on data stored temporarily in internal registers• The control unit determines exactly what operations are

performed. It also controls acccess to memory and I/O devices


39Salient feature of the von Neumann Architecture

• Storage/memory structure holds both a list of instructions (= program) and data

• The list of instructions and the data are changeable, making the computer into a universal machine (as opposed to calculators).


40

Digital Techniques Fall 2007 André Deutz, Leiden University4-40

Instruction Processing (von Neumann Cycle -- eternal)

Execute instructionExecute instruction

Fetch instruction from memoryFetch instruction from memory

(Increment program counter )(Increment program counter )

How do you stop this?

41

Digital Techniques Fall 2007 André Deutz, Leiden University4-41

Instruction Processing in more detail

Decode instructionDecode instruction

Evaluate addressEvaluate address

Fetch operands from memoryFetch operands from memory

Execute operationExecute operation

Store resultStore result

Fetch instruction from memoryFetch instruction from memory

(Increment program counter)(Increment program counter)

42


43

Von Neumann model

• Discussion of model

• Eternal von Neumann cycle

• Show-and-tell: Digital Works implementation of fetch part of the eternal von Neumann cycle


44

Some Details for building our computer


45


Single cycle data paths: AssumptionsProcessor uses synchronous logicdesign (a “clock”).

f T

1 MHz 1 μs

10 MHz 100 ns

100 MHz 10 ns

1 GHz 1 ns

All state elements act like positive edge-triggered flip flops.

D Q

clkReset ?

46

Addr Data

InstrMem

D

PC

Q+0x1

A portion of the datapath used forFetching instructions and incrementing

The program counter (PC)

47


How data flows after posedge

32rd1

RegFile

32rd2

WE32

wd

5 rs15 rs25 ws

32ALU

32

32

opLogic

Addr Data

InstrMem

D

PC

Q+0x1

48

Digital Techniques Fall 2007 André Deutz, Leiden UniversityDigital Techniques Fall 2007 André Deutz, Leiden University

registerfile

4-bit register

4-bit register

4-bit register

4-bit register

Chooses firstregister

Chooses secondregister

Chooses registerto be written

Dat

a to

be

wri

tten

Write Enable

Dat

a to

rea

d fr

omSe

cond

cho

sen

regi

ster

Dat

a to

rea

d fr

omFi

rst

chos

en

regi

ster

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