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September 25, 2003

On-Chip Interconnects in Sub-100nm Circuits

Sang-Pil SimSunil Yu

Shoba KrishnanDusan M. Petranovic

Cary Y. YangBack

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September 25, 2003

Motivation

Effective Loop Inductance

High Frequency Effects

Frequency-Dependent RLC Model

Non-Orthogonal Wires

Conclusion

OutlineOutline

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September 25, 2003

Wire versus Gate DelayWire versus Gate Delay

0.5 0.4 0.3 0.2 0.1 0.08 0.06

0

5

10

15

ITRS 2002

interconnect Delay

gate Delay

D

ela

y [

ps

]

Generation [m]

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September 25, 2003

Increases wire delay and worsens signal integrity when

As technology advances, more wires will show inductive behavior Accurate RLC model is imperative for optimal design of today’s ULSI systems

On-Chip Inductance (I)On-Chip Inductance (I)

Gate delay (tr) < RC Wire delay (RCl2) < 2* flight time (2 l)LC

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Finding return path is not straightforward Partial inductance methodology alleviate the problem with a hypothetical return path

On-Chip Inductance (II)On-Chip Inductance (II)

j

ijij IL

Self Inductance

Mutual InductanceI

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September 25, 2003

Partial inductance methodology is not appropriate for large circuits or full chip For multi-GHz freq., return current through capacitive coupling should be considered Non-orthogonal wires are being utilized

Effective loop inductance model for general high-frequency non-orthogonal wires becomes necessary

MotivationMotivation

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September 25, 2003

Power grid: designated ground line Random lines: capacitive coupling path

High-Freq. Digital High-Freq. Digital InterconnectInterconnect Signal line Power grid

S

P

Parallel random signal lines

Crossing random signal lines

P

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September 25, 2003

LF : Low resistance path MF : Low inductance path HF : Low inductance by capacitive coupling

RReffeff and L and Leffeff versus Frequency versus Frequency

0

10

20

30

40

0.1 1 10 100

Frequency [GHz]

Res

ista

nce

[o

hm

/mm

]

0.0

0.2

0.4

0.6

0.8

Ind

uct

ance

[n

H/m

m]

R L L & CReturn path is determined by

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September 25, 2003

Given by partial inductance and resistance Frequency-dependent

I

Return Path

Magnetic Coupling

Lij

Lii

Rk

Leff

Reff

2

2

1

2

1ILIIL eff

jjiij

i

22 IRIR effk

kk

Loop Inductance and Loop Inductance and ResistanceResistance

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September 25, 2003

Reff & Leff show sufficient linearity for hierarchical model construction

0.0

3.0

6.0

9.0

12.0

15.0

0 200 400 600 800 1000

0.0

0.2

0.4

0.6

0.8

1.0

Leff at 100GHz

Leff at 100MHz

Reff at 100MHz

Reff at 100GHz R [

/mm

]

L [

nH

/mm

]

Length [m]

Power grid Leng

th (

L)

S=3m & P=40m

Foundation - LinearityFoundation - Linearity

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September 25, 2003

Slight under-estimation of L at LF is caused by super-linearity

0.0

2.0

4.0

6.0

8.0

10.0

12.0

1.E+08 1.E+09 1.E+10 1.E+11

0.0

0.2

0.4

0.6

0.8

1.0

1.2

R [

/mm

]

L [

nH

/mm

]

Leff

Reff

S=5um, L=340um S=20um, L=365um

S=10um, L=300um

Frequency [Hz]

P=40m

Line – model, Symbol – FastHenry

P=40m

(10m, 300m)

(20m, 365m)

(5m, 340m)

Comparison with Field-SolverComparison with Field-Solver

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Slight under-estimation of LLF does not change overall impedance characteristics of wire

Analytic & hierarchical model construction is validated for power grid configuration

0.0

10.0

20.0

30.0

40.0

50.0

1.E+08 1.E+09 1.E+10 1.E+11

Real

Imaginary

Frequency [Hz]

Imp

edan

ce [

/mm

] Line – Model Symbol - FastHenry

Effect of Super-Linearity in LEffect of Super-Linearity in LLFLF

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Full-wave simulation (0.1 to 100GHz) RLCG extraction from the resulting S-parameters Random lines are left floating

High-Frequency EffectHigh-Frequency Effect Signal line Ground line Random line

Port 1

Port 2

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September 25, 2003

0

5

10

15

20

25

0.1 1 10 100

Frequency [GHz]

Res

ista

nce

[

/mm

]

0

0.2

0.4

0.6

0.8

Ind

uct

ance

[n

H/m

m]

Full Wave

Full Wave(random lines)

S G GGG

2 3 2 3 2 10 101010

2

Effect of Random Signal LinesEffect of Random Signal Lines

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Q-TEM mode approximation using SWFs at HF Separate SWFs for parallel and crossing lines Inductance extraction from capacitance

Correlation between L and CCorrelation between L and C

0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.03

0.04

0.050.060.070.080.090.10

0.20

0.30(LC)-0.5 = SWF-1v

Parallel lines (SWF=1.35)

Crossing lines (SWF=1.56)

Ca

pa

cit

an

ce

[p

F/m

m]

Inductance [nH/mm]

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September 25, 2003

L1 R1 C

L2

R2

R3 L3

321 RRR

3

2

32

22

2

321

11 L

RR

RL

RRR

RL

21RR

2

2

21

11 L

RR

RL

1R 1L

Freq.

Low

Medium

High

Reff Leff Extraction

from power grid,using energy equivalence

from C, empirically

Leff(f) Reff(f) CLeff(f) Reff(f) CLeff() Reff() C

Freq-Dependent RLC ModelFreq-Dependent RLC Model

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September 25, 2003

S G GGG

2 3 2 3 2 10 101010

2

Comparison with Field SolverComparison with Field Solver

0

10

20

30

40

0.1 1 10 100

Frequency [GHz]

Re

sis

tan

ce

[o

hm

/mm

]

0.0

0.2

0.4

0.6

0.8

Ind

uc

tan

ce

[n

H/m

m]

Full wave

Proposed model Krauter’s model

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September 25, 2003

Can be modeled by an equivalent orthogonal power grid

Same SWF as orthogonal is observed

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.E+07 1.E+09 1.E+11

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.E+07 1.E+09 1.E+11

Ind

uct

ance

[n

H/m

m]

Frequency [Hz] Frequency [Hz]

Ind

uct

anc

e [n

H/m

m]

S

P

S

P

S increases S = 3, 5, 10, 15, 20, 25m,

and P=50m

Diagonal WiresDiagonal Wires

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ConclusionConclusion

Analytic and hierarchical construction of loop inductance is verified for power grid configuration Random signal line effect is quantitatively investigated, leading to an empirical model The wide-band characteristics of on-chip wire are incorporated into RLC circuit valid up to 100GHz Non-orthogonal architecture can be included into the proposed model

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September 25, 2003

PartnersPartners Cadence Design Systems

- Dr. N. Arora Intel

- Dr. C. Dai KAIST

- Prof. K. Lee

PP ublicationsublicationsSang-Pil Sim, et al., “An effective loop inductance model for general non-orthogonal interconnect with

random capacitive coupling,” Technical Digest of IEDM, pp. 315-318, Dec. 2002. Sang-Pil Sim, et al., “High-frequency on-chip inductance model,” IEEE Electron Device Letters, vol.

33, pp.740-742, Dec. 2002.Sang-Pil Sim, et al., “A Unified RLC Model for High-Speed On-Chip interconnects,” IEEE Trans. on

Electron Devices, vol. 50, p.1501, Jun. 2003.