the case for hybrid photonic plasmonic interconnects ...the case for hybrid photonic plasmonic...

The Case for Hybrid Photonic PlasmonicInterconnects (HyPPIs): Low-LatencyEnergy-and-Area-EfficientOn-Chip InterconnectsVolume 7, Number 6, December 2015

Shuai SunAbdel-Hameed A. BadawyV. NarayanaTarek El-GhazawiVolker J. Sorger

DOI: 10.1109/JPHOT.2015.24963571943-0655 Ó 2015 IEEE

The Case for Hybrid Photonic PlasmonicInterconnects (HyPPIs): Low-Latency

Energy-and-Area-EfficientOn-Chip Interconnects

Shuai Sun,1 Abdel-Hameed A. Badawy,1,2 V. Narayana,1 Tarek El-Ghazawi,1

and Volker J. Sorger1

1Department of Electrical and Computer Engineering, The George Washington University,Washington, DC 20052 USA

2Department of Electrical Engineering, Arkansas Tech University, Russellville,AR 72081 USA

DOI: 10.1109/JPHOT.2015.24963571943-0655 Ó 2015 IEEE. Translations and content mining are permitted for academic research only.

Personal use is also permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

Manuscript received September 17, 2015; revised October 19, 2015; accepted October 20, 2015.Date of publication October 30, 2015; date of current version November 16, 2015. This work wassupported by the Air Force Office of Scientific Research (AFOSR) under Award FA9550-15-1-0447.Corresponding author: S. Sun (e-mail: [email protected])

Abstract: Moore's law for traditional electric integrated circuits is facing increasinglymore challenges in both physics and economics. Among those challenges is the fact thatthe bandwidth per compute on the chip is dropping, whereas the energy needed for datamovement keeps rising. We benchmark various interconnect technologies, including elec-trical, photonic, and plasmonic options. We contrast them with hybrid photonic–plasmonicinterconnect(s) [HyPPI(s)], where we consider plasmonics for active manipulation devicesand photonics for passive propagation integrated circuit elements and further propose an-other novel hybrid link that utilizes an on-chip laser for intrinsic modulation, thus bypassingelectrooptic modulation. Our analysis shows that such hybridization will overcome theshortcomings of both pure photonic and plasmonic links. Furthermore, it shows superiorityin a variety of performance parameters such as point-to-point latency, energy efficiency,throughput, energy delay product, crosstalk coupling length, and bit flow density, which is anew metric that we defined to reveal the tradeoff between the footprint and performance.Our proposed HyPPIs show significantly superior performance compared with other links.

Index Terms: Optical interconnect, plasmonics, hybridization, hybrid photonic–plasmonicinterconnect (HyPPI), on-chip structure, bit flow density, intrinsic modulation, extrinsicmodulation.

1. IntroductionThe requirement of electronic device down-scaling has led to severe limitations for on-chip com-munication interconnects [1]–[3]. Likewise, the available bandwidth per compute operation (e.g.,Mbps/FLOPS) continues to drop and will likely reach its end at 5 nm technology node accordingto the 2013 International Technology Roadmap for Semiconductors (ITRS) [4]. The increasingdemand for data movement, requires novel interconnect technologies over classical electroniclinks, particularly in terms of latency, energy efficiency, and integration. These effects are due tothe heat generation in current integrated circuits, which can easily melt the chip. Furthermore,

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IEEE Photonics Journal

the physical properties of semiconductor material will no longer stay the same once we reach 5 nmfeature size.

Photonic interconnects are considered a viable on-chip option since the mid-2000s ITRSroadmap for ICs due to their ability to provide higher bandwidth compared to electrical intercon-nects. This originates from the parallelism of bosons, which is exploited in Wavelength DivisionMultiplexing (WDM).

In particular, the low optical attenuation of photonics enables on-chip communications withsmall power losses. Active optoelectronic devices based on pure photonic elements, however,often rely on optical non-linear physical effects requiring some form of light-matter-interaction(LMI), which is inherently weak, which often leads to significant power consumption. For in-stance, Batten et al., [5], [6] estimated that about 40% of the total consumption is accounted fortuning the electro-optic modulator, a value that is expected to increase further at lower link utili-zation rates. Moreover, the sensitive ring-modulator based on high quality factor (Q factor) mi-crorings is photon lifetime limited and bandwidth limited and requires heating to be tuned, whichresults in challenging dense integration.

The physical reason for the large required footprints and high energy efficiency of active pho-tonic devices stems from the large difference of the dipole momentum between the electronicwave function and a telecommunication photon. This leads to weak LMI, which can fundamen-tally be enhanced by either increasing the optical density of states, or increasing the field den-sity overlapping with the active material. The latter is deployed, for instance, in the field ofplasmonics and metal optics.

A plasmonic interconnect utilizing surface plasmon polaritons (SPPs) allows for diffraction-limited optical modes and high field densities. This enables addressing the footprint challenge ofphotonics by providing enhanced LMIs that allow the desired functionality (e.g., modulation, sig-nal switching, etc.) to be realized within a small and potentially wavelength-scale device footprint.Nonetheless, plasmonic interconnects are only suitable for short-distance communication pur-poses since its maximum propagation length is limited to tens of micrometers due to the ohmicloss of the plasmonic coherent electron oscillations at telecommunication frequencies.

In this paper, we propose a Hybrid Photonic Plasmonic Interconnects (hereinafter referredto as “HyPPI ”) strategy to combine photonics with plasmonic interconnect technology andshow that this combination leads to superior link performance. Furthermore, we provide acomprehensive performance comparison between electrical, plasmonic, photonic and our twoproposed HyPPI technologies and compare latency, energy efficiency and throughput perfor-mance of our proposed links to pure photonic, plasmonic, and traditional electrical links. Wealso investigate on-chip crosstalk and bit flow density as on-chip metrics. In particular, we re-place the diffraction-limited photonic modulation devices with plasmonic counterparts, butkeep the low-loss silicon-on-insulator platform as the passive backbone. In addition, we arguethat the light source should be part of the link's performance consideration and consider iton-chip. This will eliminate the need for an electro-optic modulator (EOM) if it is powerful enoughto drive the entire link with high operating frequency. We call this direct light source modulation“intrinsic” (versus “extrinsic” for the EOM use), which allows source power management. Our re-sults show that hybridization of classical photonic and nanophotonic elements is energy efficient(∼20 fJ/bit), low latency (< 10 ps for millimeter-range propagation distances), has reasonablylong-range transmission (∼3 dB loss per length > 104 �m) interconnect, and has a bit flow densityup to 0:5 Gbps=�m2.

2. Link Level PerformanceWith network-on-chip (NoC) application in mind, the network's performance inherently relies onthe characteristics of its building blocks, namely the interconnect links. In this section, we inves-tigate the performances of the HyPPI, plasmonic, and photonic technologies at the link, i.e.,point-to-point (P2P), level with respect to latency, energy efficiency, link throughput, and energy-delay trade-off. We also compare with electrical interconnects.

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2.1. Point-to-Point LatencyFor an electrical interconnect, the P2P latency is defined as the time a single bit of data

packet requires to travel from the sender to the receiver. For a photonic or a HyPPI (plasmonic)interconnect, latency includes the time of propagation that a photon (SPP) requires to propagatefrom the light source across the link to the photoreceiver, which includes the amplification cir-cuit. Thus, for every optical link type investigated here, the latency can be estimated by sum-ming up each device's individual latency plus the light propagation time.

Given the technologically mature option to use electrical interconnects, the entire link includingwires and other components can be combined into a series of RC (R ¼ Resistance,C ¼ Capacitance) lumped elements given by the selected technology node (i.e., 14 nm technologynode is considered here based on ITRS) as in (1) and (2), shown below. The on-resistance of theminimum size n-FET Ron, parasitic driver capacitance Cpar ;dr ; load capacitance CL, optimum num-ber and size of the repeaters kopt and hopt and the per unit length resistance/capacitance rint=cint inthe equations all are borrowed from Rakheja and Kumar [7].

tp2p�el ¼0:69RonðCpar ;dr þ CLÞ þ 0:69ðRoncint þ rintCfanÞLþ 0:38rintL2 (1)

Eel ¼ 12ðCintLþ Cokopthopt ÞV 2

DD : (2)

However, for photonic and HyPPI interconnects, the light source is considered to be on-chipand is kept ON at all times during operation for extrinsic modulation. Hence, we can safely ne-glect the source delay; except for the HyPPI intrinsic modulation because we manipulate thesignal directly at the laser not the modulator. Moreover, the latency caused by the source shouldalso be considered for the plasmonic option due to its short propagation length; the entire linkstructure needs to be repeated using the previous signal output to drive the light source in thenext segment in an iterative way. The plasmonic lasers for plasmonic and HyPPI interconnectsare borrowed from Lau et al. and Ren-Min et al. [11], [78].

For all four optical link options (photonic, plasmonic, HyPPI-intrinsic and HyPPI-extrinsic) thewaveguide delay was estimated based on its material composition, waveguide's structural shapeand propagating light wavelength. Here, we estimate the fundamental mode effective indexneff ¼ 3 for classic photonic SOI waveguide with moderate loss of 0.5 dB/cm and an Ag-SiO2

SPP waveguide with neff ¼ 1:457 and 440 dB/cm attenuation losses [8], [9]. All the numbers aregiven for 1550 nm wavelength. Using (3) and (4), shown below, we can calculate the waveguidepropagation speed (waveguide latency) and maximum propagation length. For consistency andcomparability, similar waveguide cross-sectional shapes were used for the waveguides investi-gated. Note, the propagation length L1=e for an SOI waveguide could easily reach few centimeters(∼9 cm), which is far beyond the chip-scale. However, for the SPP waveguide, this length is re-duced up to 100 microns. Therefore, in the following discussion we assume that photonic andHyPPI interconnects use an SOI waveguide for light transmission and do not need repeaterswith the exception of plasmonic links, which repeats every 100 �m.

Propagation speed v ¼ cneff

(3)

Propagation length L1=e ¼ total lossunit loss

¼ 10 � lg 1e

�� unit loss

: (4)

We studied a wide range of active devices (lasers [10], [11], modulators [21]–[47], and detec-tors [48]–[72]) with different structures, materials, and technical approaches. The selection foreach device is not limited to the device maximum operating speed or estimated energy con-sumption, but also includes the on-chip footprint, insertion loss, responsivity, cooperation withother devices, and other on-chip characteristics, such as temperature dependence and wave-length spectrum, etc.

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For the photonic interconnect, we use a femtojoule level athermal silicon microdisk modulatorfrom Timurdogan et al. [18] and a zero-bias waveguide photodetector from Vivien et al. [58]. Forthe plasmonic interconnect, we borrowed the modulator and detector from Dionne et al. [26] andMousavi et al. [64] respectively. For these devices, the latencies are simply regarded as thereciprocal of their operating frequency (60 GHz and 700 GHz, respectively, based on theirRC delay).

For the proposed extrinsic and intrinsic HyPPI interconnects, our aim is to reduce the link la-tency by using ultra-fast plasmonic active devices, while maintaining chip-size long-range prop-agation via low-loss photonic waveguides similar to those found in silicon-on-insulator (SOI)platforms. In the extrinsic modulation link, instead of using conventional photonic ring-basedmodulator or the novel microdisk modulator [18], we use an ITO electro-optical modulator usingSOI hybrid integration similar to the plasmonic link not only to achieve fast operation and lowenergy consumption, but also to have an advantage in structural matching since the base struc-ture of the ITO modulator is an SOI waveguide [46]. We should point out that when the link lossis reasonably low, new source technologies can be considered, which offer power savings andunprecedented-fast intrinsic modulation, as found in the emerging nano-cavity plasmon lasersand light-emitting diode (LED) devices [10], [11], [78].

The electrical supporting components (i.e., device drivers) specifications are based on the22 nm technology node [73]. Since the timeframe of all the optical devices used is in therange of 2009–2014, we chose the technology node level of the year 2012 for predictingelectrical components performances. Since the latency of the driver is determined by its RCdelay which is proportional to the device capacitance it drives, driver(s) latencies could becalculated using the prediction of Chen et al. (9.5 ps for a 24 fF size modulator) [73].

To obtain scaled down optoelectronic devices, the reduced LMI is compensated by field en-hancements and high optical density of states. These wavelength size sources only providetens to hundreds of micro watts of optical power, and utilize modified rate equations allowing forminuscule power consumption, small footprint, and fast data operation. The latter enables by-passing the external electro-optic modulator altogether. The laser is modulated via an electricaldriver (intrinsic modulation). The latencies of the various devices utilized are summarized inTable 1.

Comparing the P2P latency of the various five different interconnects versus link length showsthat the plasmonics can indeed outperform pure photonic links due to its higher LMI in the limitof propagation lengths (see Fig. 1(a)). However, the delay for plasmonic links grows when re-peaters are required ð�100 �mÞ, thus limiting the use of these links to local communicationranges only. The high performance of Silicon photonics can be seen by the relatively shortcrossover length ð�20 �mÞ with electrical interconnects. To that end, pure plasmonics are a ques-tionable interconnect technology unless other synergies with existing infrastructure such as CMOSwould allow us to reduce other technological relevant parameters such as cost. HyPPI can providemuch lower P2P latency for both local range due to high LMI and sub-wavelength-scale footprint

TABLE 1

Latency (ps) of each considered device for different interconnects with link length L in micrometers

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devices and chip-size communications, due to the long-range propagation of silicon photonicsð�SOI�waveguide � 0:5 db=cmÞ.

2.2. Energy EfficiencyThe link energy efficiency is directly related to the performance of the network and important

for both internal and external considerations [4]; internally, it relates to integration density, tem-perature budgets, and tuning overhead, whereas externally, it relates to overall power consump-tion and battery life.

While the power consumption of the source in optical links has been included in roadmaps, ithas usually been omitted in the literature since it is typically regarded as an off-chip componentdue to the high power consumption, and subsequent heat dissipation [4], [7], [73]. In this paper,we calculate the required laser power by summarizing the link device losses, photonic-plasmoniccoupler loss and the power loss of the entire propagation path to ensure output electrical signalgenerated by detectors based on responsivity ðRÞ still meet the minimum current requirementsfor the next stage after such losses (see (5), shown below).

In Table 2, we use the same devices when calculating the link latencies and the losses forSOI and we borrow from Li et al. and Berini et al. [8], [9] the values for SPP waveguides. Theoutput minimum current level Imin is assumed to be 50 �A, which is a moderate value for driving

Fig. 1. Comparison of (a) point-to-point latency and (b) energy efficiency versus link length for vari-ous interconnect types. All the interconnect options have a “cut-off” size greater than 1 �m on theleft side of the curve affected by device size limitations except for electrical interconnect. The elec-trical link is able to provide extremely low delay and energy efficiency over micron-scale distancesdue to its length dependent RC characteristics but loses its advantages at long link lengths. The la-tency for the photonic and HyPPI links are dominated by both the various active devices and thewaveguide propagation timescales in short link lengths and by the waveguide only for long propa-gation distances, and the flat energy efficiency profile is basically due to the use of low loss SOIwaveguide. The plasmonic link latency and energy efficiency limitation both grow due to repetitionevery 100 �m.

TABLE 2

Energy efficiency (fJ/bit) of each considered device for different interconnects with link length L inmicrometers; the minimum output current level Imin here is 50 �A

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electrical circuits or blocks but still highly depended on the energy requirement of the nextstage. The bandwidth (operating speed) for photonic link (25 GHz) and plasmonic (60 GHz) arelimited by their modulation speed and HyPPI-Intrinsic links (200 GHz) are limited by the switch-ing speed of the light source. Although the light source of the HyPPI-Extrinsic link could be re-garded as ON all the time and will not affect the overall operating speed, its speed is also beenconstrained to 200 GHz for fair comparison. Although some of the performance results arebased on optimized theoretical calculation and prediction, exploratory devices have shown todemonstrate over 100 GHz speed and the speed is still increasing [74].

Similar to the latency assumption, the energy consumption for the drivers are also consideredand predicted following the same methodology in the previous section. The driver energy con-sumption is highly based on the applied voltage and the capacitance of device it drives. There-fore, the driver energy equation for a single charge (operation) can be approximated to beð1=2ÞCV2. Under the same technology node, the voltage levels are usually the same. The driverenergy efficiency for HyPPI-extrinsic option shows smaller than the photonic and plasmonic in-terconnects. This is because the modulator we use has a much smaller device capacitance(size). However, that does not mean the driver of HyPPI consume less energy per second(power) because it also operates at a higher frequency. The energy efficiency, lasing efficiencyand power loss in dB of each of the considered interconnects are listed in Tables 2 and 3 brokendown based on the same devices used in the latency analysis.

Laser Power per bit ¼ Imin

BW � Responsivity� Efficiency� 10

jlossj10 : (5)

For comparison, the electrical link is plotted based on its length dependent RC structure men-tioned in Section 2.1 [7]. Comparing the energy efficiency with the other four different optical in-terconnects reveals a significant reduction in power consumption for the links, which usepassive SOI waveguide for signal transmission at longer communication distance. However,due to the insertion loss, propagation loss and low optical-electrical conversion efficiency de-mands that certain amount of energy overhead must be paid which also makes the electrical op-tion more suitable at shorter communication ranges with respect to energy side (see Fig. 1(b)).On the other hand, for a long communication range, the photonic and HyPPI interconnectsshow much better scaling because of the low attenuation loss of the passive SOI waveguide.

The plasmonic link can provide better performance by sacrificing transmission distance,whereas HyPPI links are able to outperform the photonic and plasmonic links in both metrics.The intrinsic modulation type of HyPPI saves more energy by not using the modulator, but itsspeed is subject to source modulation speeds. Moreover, the energy efficiency that the modelpredicts is an upper-bound energy consumption for each link because all the numbers borrowedfrom other papers as shown in Table 2 are based on the maximum bandwidth of each device.

TABLE 3

Power loss break down and detector responsivities. Link length L in micrometers

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However, in real applications, the data rate will be dependent on the data rate of the slowestcomponent of the link as it will be the bottleneck. Also, we note that a device operating at alower data rate will consume less energy.

2.3. ThroughputThroughput of a link, which is commonly defined as a measure of how many units of informa-

tion (bits) a “medium” (network) can deliver in a given time period, is another critical metric forevaluating the performance of a link. We can express it as a function of the operating frequencyof each device, the propagation length for the signal to be transported from P2P latency and thedata packet size (D); see (6), shown below and in Fig. 2.

In reality, D depends on the different traffic patterns and protocols under a particular computa-tional application. Capacity, as in (7) [bit/s], shown below, refers to the data-carrying ability of anetwork, indicates that the maximum amount of data that can pass from one point to anotherper unit time as in (7) (Bandwidth (BW, [Hz])). Fig. 2 shows schematic diagrams for throughputand capacity. Moreover, since the Nyquist equation can only predict the highest capacity forideal links without noise, we only take half of its results to match with real communication situa-tions. Note, the definition of the term BW is not unique; for instance, Rakheja [7] proposed to de-fine it as the reciprocal of the P2P latency of the entire link. Under this assumption, every bit issent only after the previous bit has arrived at the end of the link, which results in a rather low ca-pacity, and therefore can be regarded as a lower bound. In contrast, we regard bandwidth ofeach device in the link as operating as close as possible to its designed frequency, and there-fore, our capacity definition establishes an upper bound.

It is worth mentioning that decreasing the data packet size or increasing the link length willboth negatively affect the throughput (see Fig. 3(a) and (b)). This can be understood from analyz-ing (6); decreasing D for a fixed link length (i.e., P2P latency) will decrease the denominator at aslower rate than the numerator; however, increasing the link length for a given D also decreasesthe throughput of the link. Comparing the throughput for the five link types clearly shows an

Fig. 2. Schematic depicting the concept of throughput (which is equal to the data packet size ðDÞ di-vided by the total time to transmit the data through the link and the latter is the sum of the datasending and the data propagation time) and capacity (the maximum message sending rate, whichis defined by the Nyquist equation). Moreover, the bandwidth ðBW Þ in (2) refers to the differencebetween the upper and lower designed frequencies and is physically bounded by the slowest oper-ating frequency of the devices that the signal passes through. M in the brackets represents thenumber of the coding levels and is assumed to be 2 here for the simple case of on-off keying.

Fig. 3. Comparison of link throughput with (a) a fixed link length (1 mm) and (b) a fixed packet size(64 bits). No WDM was assumed here and all interconnects are using 1550 nm wavelength.

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absolute advantage for HyPPI in providing a high throughput with good response to increasingthe data size and high resistivity to increasing the link length. The throughput here is only for sin-gle wavelength carrier, and WDM technology will be discussed in future research.

Throughput ¼D=D

Capacityþ tp2p

� �(6)

Capacity ¼ 2� BW � log2ðMÞ: (7)

2.4. Overall Link PerformanceAlthough the individual link performance we have analyzed thus far can give us an accurate

comparison in each aspect, no interconnect option has an absolute advantage in all of the as-pects. Therefore, we still need to investigate a more complex figure of merit that includes theenergy efficiency; P2P latency and throughput of each interconnect type. Such composite met-rics are useful towards defining link merits via exploring tradeoffs among relevant criteria.

In this paper, we use the metric proposed by Martin, Nystroem, and Penzes termed ET n, inwhich E stands for the energy consumption in the unit of Joules and T for the delay (latency) of thesystem or network [16]. By multiplying the energy efficiency (E 0, [J/bit]) by throughput (Th, [bit/s]),we get the operational power (P in [W]). Power times P2P latency (T , [s]) results in the total energyconsumption (E , [J]) of the link. Note, n in ETn metric denotes a weight that represents the de-gree of correlation between two criteria. For n ¼ 1 (see (8), shown below), a decrease in latencyis considered as valuable as a reduction in energy consumption at the same proportion, and n ¼ 2is a metric independent of the power supply voltage (see (9), shown below) [75]. For n ¼ 2, whencomparing the tradeoffs, more energy consumption for small latency improvement in interconnectsthat a) have a composite performance which is more sensitive to latency, and b) have a relativesurplus in its power budget. Note that n ¼ 0 is just the energy efficiency metric we already men-tioned in the previous section. Therefore, the ETn metric can be used to optimize the weighted en-ergy consumption and system latency simultaneously, and is consistent with priorities of HighPerformance Computing (HPC) [76].

Energy Delay Product ¼E 0 � Th � T � T ¼ P � T � T ¼ ET (8)

Energy Delay Squared Product ¼E 0 � Th � T � T 2 ¼ P � T � T 2 ¼ ET 2: (9)

Interestingly, our results show that the electrical link is superior for link lengths below 5 �m.This is obvious, when considering that the resistance and capacitance is dependent on the linklength, and therefore causes smaller latency and energy consumption for short lengths (seeFig. 4(a) and (b)). In contrast for such short lengths, any optical solution has only RC delayfrom the active components and drivers as a small part, can have fundamental inefficienciesdue to a quantum efficiency less than 100%. Moreover, due to the different on-chip device

Fig. 4. Composite performance metrics. (a) Energy Delay Product (EDP) and (b) Energy DelaySquared Product (EDSP) for each interconnect. Both EDP and EDSP are the reverse metrics forthe overall link performance and have minimum link length for each technical option. The length ofHyPPI links is limited by the size of the active devices and propagation waveguide. However, elec-trical links have a rather mature technology and can be built even under 1 �m.

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footprint for each technology option, the curves to the left side (shorter link length) begin atdifferent points. Fig. 4(a) and (b) show absolute advantages for HyPPIs above �10 �m linklength and this again proves that a HyPPI backbone network with local electric interconnectsbranches is the best alternative.

Additionally, link of about 100 �m in length can be regarded as a general break-even point forelectrical, plasmonic and photonic links. This can be qualitatively understood as the boundarybetween local to medium range ðG 100 �mÞ and long range ð> 100 �mÞ communications andmay lead to a design rule for future NoC that are composites of multiple link technologies.

3. On-Chip Performance

3.1. Chip Level CrosstalkWhile the P2P latency, energy efficiency, link throughput and the ET n metrics are important

to understand a link's intrinsic features, crosstalk is a characteristic related more directly to NoCarchitectures.

Here, we define acceptable distance for crosstalk to be the link length where the energy leak-age is 25% from one waveguide to its adjacent neighbor and quantify the crosstalk couplinglength of two waveguides. Thus, the total leakage from two adjacent waveguides will cause amaximum 50% energy interference, which is the upper limit of a binary coding system couldsustain (below “0.5” as off/zero state and above “0.5” as on/one state). We determine the cross-talk by simulating the eigenmode of the two waveguide structures and solving for the differencebetween their symmetric and asymmetric modes.

Fig. 5(a) and (b) show that the SOI waveguide mode is cut-off at a dimension of tSOI ¼ 220 nm,which can be estimated by the Abbe Limit (t ¼ �=2n, where � is the free space wavelength, andn is the effective mode index, which is close to the material index of Silicon at 1550 nm).

In contrast, the plasmonic mode is able to provide sub-diffraction limited (non-cutoff) modesand is hence more suitable for highly integrated chip size (< 1 cm) and local-range communica-tion ðG 100 �mÞ. For an SOI waveguide, the maximum coupling length increases rapidly withwaveguide dimension and the inter-waveguide spacing (gap) and can easily reach the 1 cmchip size with a gap much smaller than its dimension. This leaves us with two choices; either alonger propagation distance at the cost of a larger waveguide footprint (area) or a denser wave-guide arrangement with only local range communication.

Note, the small diameter plasmonic waveguide (e.g., 50 nm radius; see Fig. 5(a)) has essen-tially the same crosstalk length as to the larger scale plasmonic waveguide (e.g., 300 nm and500 nm) but is still not practical for on-chip use due to its low optical mode propagation speedamplified by repeaters (i.e., high latency). We deploy an eigenmode solver to obtain the

Fig. 5. (a) Twenty five percent crosstalk coupling length comparison. The wavelength � ¼ 1550 nmis used as light source signal, and the waveguide diameters for each curve are directly labeled onthe figure. Shaded area is beyond 1 cm chip size. (b) Propagation speed of two kinds of waveguidewith 1550 nm wavelength light source.

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propagation speed based on the effective mode index for both the SOI photonic and metal em-bedded dielectric plasmonic waveguide (see Fig. 5(b)).

The propagation speed of plasmonic waveguides reduces significantly when the dimension ofthe waveguide drops below 100 nm. In addition, based on conclusions from Fig. 1(a), the majorcomponent of the P2P latency after increasing the link length is the propagation time throughthe waveguide. For instance, for a 50 nm radius plasmonic waveguide, the signal only hasabout half of its maximum speed of light, which will cause an unacceptable delay for the entirelink. The latter is another reason why pure plasmonic interconnects might not be a practical op-tion alone despite footprint savings on-chip.

On the contrary, the SOI waveguide has an opposite speed pattern with higher speeds forsmaller waveguide dimension (i.e., lower effective index). Although the crosstalk length has littledifference between two waveguides of about 300 nm or smaller, the higher propagation speedfavors the photonic waveguide resulting in a better link latency and higher throughput.

Furthermore for larger waveguide dimensions, the speed of the photonic waveguide de-creases rapidly while the speed of plasmonic waveguide stays almost constant. However, thisin return increases the crosstalk length of the photonic waveguide exponentially and can easilyreach 1 cm chip size with much less spacing. In other words, even though the propagation timethrough each single link increases, the gap between two parallel waveguides can be reduced.This would increase the packing density and also would result in higher total throughput den-sity. Note, we only considered the simplest crosstalk model from two adjacent waveguides(25% energy leakage from each waveguide) here for network level performance prediction,which can be regarded as the minimum crosstalk length on-chip since in an integrated wave-guide array, the crosstalk will not only comes from the nearest waveguide, but also the second-,third-nearest waveguide(s) etc., which has already been proved by Song et al. [77]. In thefuture, we plan to include not only multi-waveguides crosstalk but device-to-waveguide anddevice-to-device crosstalk as well a real optical network structure.

3.2. Bit Flow DensityCrosstalk limits the maximum communication length. On the other hand, the propagation

length determines the actual length a signal travels before a repeater is needed. Together thesequantifiers define over that distance an interconnect link can deliver a signal before it is unde-tectable by the receiver and without interfering with other waveguides.

In detail, the dimension (size) of the transmission waveguide and the spacing (gap) betweentwo adjacent waveguides has the most influence on the propagation length and the waveguide-to-waveguide coupling levels respectively. Therefore, it is reasonable to conclude that byincreasing the waveguide dimensions and the gap between waveguides, the signal can be deliv-ered a longer distance, however increasing the waveguide dimension and the gap between adja-cent waveguides would limits the on-chip footprint (area) and packing density. Thus, we believethere should be an optimal size-to-gap ratio given certain communication requirements. Wequantify this footprint-performance trade-off by defining “Bit Flow Density.”

We define Bit Flow Density (BFD) as the number of bits transmitted through a certain chipwidth (cross-section) to reach a specific required communication length, which is highly relatedto the size of each device and spacing. The three major elements in chip area calculations weassume are 1) the size of the light sources (laser, LED), 2) modulators (microdisk modulator,PlasMOStor modulator and ITO modulator), and 3) the waveguide area including waveguide-to-waveguide spacing. Note, the area of detectors are not considered here since the output currentlevel at the end of each link is highly dependent on the requirements of the next circuit blockand additional amplifiers may be needed as well.

Each of the four different on-chip packing layouts is arranged within a 1� 1 mm2 chip area.The laser size ð10 �m� 20 �mÞ for photonic links is taken from the DSENT database [5], andthe 20� 40 � 140 nm3 core dimension 200 GHz nLED proposed by Lau et al. covered by pas-sivation and silver layers with total on-chip size 80� 140 � 200 nm3. The microdisk modulator

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(�5 �m diameter) is simplified to an annulus structure on this 2-D layout, and the space be-tween the ring and the waveguide on one side is much closer (150 nm) than the three othersides for coupling purposes [24]. The larger spacing is used to avoid coupling and its value isdetermined by eigenmode simulations. The ITO based electro-optical modulator is used in bothplasmonic and HyPPI links with a 2 �m device length [10]. The width of the ITO modulator canbe regarded as being built “on” the waveguide device and costs no additional flat area due to itscompact structure. The detectors used for photonic links and plasmonic/HyPPI links have theon-chip size 10� 10 �m2 and 2� 2 �m2 respectively.

Fig. 6 shows the resulting Bit Flow Density heat map for our four interconnect links. As ex-pected, plasmonic interconnects achieve their highest value in the center of its plot, which indi-cates that plasmonic links are able to provide high data transmission rates over a certain chipscale with smaller waveguide diameter and gap compared to its photonic counterpart (Fig. 6(a)).However, when the waveguide diameter scale below 50 nm, the crosstalk length and the propa-gation length respectively will become even smaller than the side length of the PlasMOStormodulator and therefore causes a longer bit flow density.

On the other hand, all the high bit flow density regions are shown on the right hand side(waveguide width > 300 nm) of their plots for both photonic and HyPPI links due to the lowcrosstalk length (needs more repeaters to propagate enough distance) of SOI waveguides be-low 300 nm waveguide width. There is only one exception; the lower left corner of the HyPPI in-trinsic modulation link is significantly higher than any other regions below a width of 300 nm.This is because the modulators are absent for this interconnect, and therefore smaller wave-guide widths and gaps lead to much denser link arrangements.

(b)

Fig. 6. Bit flow density for four different kinds of interconnects as a contour plot with heat map colorscheme, in which more red (blue) indicates higher (lower) bit flow density. (a) Plasmonic intercon-nects (with PlasMOStor modulator), (b) photonic interconnects (with ring modulator), (c) HyPPI extrin-sic modulation interconnects (with ITO modulator), and (d) HyPPI intrinsic modulation interconnects(with nano-cavity plasmon laser). Plasmonic waveguide has a metal embedded structure with Ag cylin-der inside the dielectric. Others are using normal SOI waveguide with silicon strips over silicon oxidebase and have diffractive limit below 200 nm waveguide width.

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By comparing all four contour plots, we can conclude that HyPPI (especially intrinsic modu-lation links) can provide much higher bit flow density rather than both traditional photonic inter-connects and plasmonic interconnects. In this regard, intrinsically modulated links combine thebest of both worlds; small energy consumption from plasmonic devices and long propagation/crosstalk lengths from photonic waveguides. Such synergies are an example of a reductionin integration and design complexity, which is regarded as a key element to continue scalingon learning curves towards cost reduction and leads to what is previously termed coherentinnovation [19].

We note that the BFD and total link energy for chip level photonic links are forecasted to beover 40,000 Gbps/cm2, and 10–100 fJ/bit, respectively by the year 2025 [20]. Our results showthat to simultaneously achieve the two roadmap goals, HyPPI links are one possible and viableinnovative technique.

4. ConclusionHyPPI hybridizes photonic with plasmonic interconnects to provide a point-to-point link thatshows significant improvements in performance relative to that of pure photonic or pure plas-monic links in P2P latency (< 100 ps/cm), energy (∼20 fJ/bit), and combined metrics such asEnergy Delay Product and Energy Delay Squared Product. Plasmonic links are limited by theirhigh optical losses whereas; photonic links are bound by high power consumption due to over-heads in modulation. Moreover, the sufficient crosstalk length (over 1 cm chip-size) of HyPPIenables dense integration schemes leading to high bit flow density (0:1 � 0:5 Gbps=�m2, 1∼3orders of magnitude greater than other interconnects at different link length) and higher area ef-ficiency. Such high performance results from technology hybridization appears to be the onlytechnologies at this point in time that can supply both energy and bit-flow-density requirementsmatching roadmaps for any communication range requirements. These encouraging results willpave the way for designing scalable, low latency, low interference and energy efficient NoCs forfuture scalable chip multiprocessors.

AcknowledgmentThe authors would like to acknowledge the effort of the anonymous reviewers since their timelyand constructive reviews improved the paper significantly. They would like to thank the journaleditorial board for their timeliness.

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