chip-scale photonic interconnects for reconfigurable …
TRANSCRIPT
Chip-scale Photonic Interconnects forReconfigurable Computing
By: Dennis Prather
Department of Electrical and Computer EngineeringNewark, DE 19716 USA
Outline
• Motivation
• Interconnect Challenges– Routing Delay
– Routing Area
• Chip-Scale Photonic Routing Elements– Reconfigurable Planar Routing Network
– Three-dimensional Optical Bus
– Optical Analog-to-Digital Converter
– Optical Modulator
• Fabrication of Large Area 3D Routing Network
Motivation
Realization of a reconfigurable chip-scale photonic interconnect would enable
All optical switching on a chip, Multistage tunable wavelength converters and multiplexers, All optical push-pull converters, Optical FPGA Compact beam steering, Very fine pointing, tracking, and stabilization control; Ultra-lightweight reconfigurable antennas
The Integration of chip-scale electronics + digital/analog + photonics, all- optical FPGA made with programmable optical cells was identified as the future direction for optical signal processing and communications in the 2007 DARPA/MTO Microsystems technology symposium.
Air Force Research Laboratory (AFRL) identified13 critical technologies needed for realization of integrated Microsystems, including System-on-a- Chip (SoC).
Current Interconnect Challenges
Clo
ck S
peed
(MH
z)
Diminishing Returns
Processor speeds are NOLONGER increasing
exponentially
Otherwise, we would have a 10GHz processor TODAY!
But in fact, Intel cancelled theirdevelopment of a 4 GHz processor
Obstacles to Microprocessor GrowthObstacles to Microprocessor GrowthIncreased Power, Increased Heat, Increased Current LeakageIncreased Power, Increased Heat, Increased Current Leakage
ProcessorPlateau
Moore’s Law is Coming to an End!
Intel CPU Introductions (Year)
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Interconnect Trend Chart
Electronic FPGA (EFPGA) Optical FPGA (OFPGA)
FPGA Trend Chart (extracted from 2007 ITRS Product Technology Trends)
Cell Size is Decreasing
Functions per chip is increasing
Eventually standard FPGA technology will plateau
Increasing Performance
PC Cluster Supercomputer
Traditional approach to increasing computational power …
… but this approach has disadvantages!• Expensive• Limited Scalability• Tremendous Heat Generation
• High Power Requirements• Requires Significant Area• Increased Maintenance
Chip-Scale Interconnect Can Help
2 Main Interconnect Components Configurable Logic Elements (CLEs) Programmable Routing Fabric
CLEs implement logic operations Routing Fabric transfers data between CLEs (and also off-chip resources)
Descriptions
Routing Problems Tremendous delays (50-95%) Requires significant area (60-90%) Greatly increases design turnaround time
The routing problems are devastating … and are only getting worse!
Problem 1: Routing Delay
A Constant Obstacle to Interconnect Performance Routing delay has always been a roadblock … until the advent of our approach! Although researched for many years, only incremental fixes have been developed
Signals spending increasingly more time being transported rather than generated Redundant logic to offset fabrication errors adds capacitance and hence delays
Shrinking Feature Sizes Exacerbate This Problem
Typically accounts for 50-95% of the total system delay Eliminating routing delay, our Celerity™ FDTD Accelerator goes from 130 MHz to 650 MHz (500% improvement)
Statistics Are Shocking
Delay is getting worse and incremental improvements are not enough …a radical new interconnect architecture is necessary
Problem 2: Routing Area
How Much Chip Area is Used For Routing? Exact usage is a closely guarded secret Researchers estimate upwards of 90%
Also Hurt By Fabrication Improvements Area usage increases dramatically Why? Tracks must be laid down at a greater rate than CLEs to maintain connectivity
CLE
s
Routing Fabric
Only 10% of chip area used for logic
The modern metallic routingfabric is growing out of control
Parallelism between CLEsis artificially limited by thisever-growing infrastructure
We must reduce the sizeof the fabric in order tocontinue realizing performance improvements.
What Is Possible?
If the routing delays could be mitigated … Celerity™ FDTD Accelerator goes from 130 MHz to 650 MHz (500% improvement) Current accelerator rivals 100-node PC clusters; a 500% clock rate improvement would surpass even supercomputer speeds!
If the routing area could be lessened … Approximately 10x increase in CLE blocks (the computational heart of the chip) Approximately 10x increase in parallelization More chip-are for increase performance Larger problems can be solved
If CAD-tool runtimes could be decreased … 1 day design cycles are reduced to hours Real time error correction Time to market decreased!
Reduce the size of transistors and interconnects Down sizing those parts has become much more difficult and expensive This forced designers to make trade-offs between performance, energy and cost
Shift to cross bar structure (Courtesy: HP Labs) Removing the traditional interconnects will drastically shrink the size of the chip Performance will increase, while chips are still made of traditional transistors Cost will decline (no need to invest $Bs in new semiconductor manufacturing Equip.
Crossbar (Courtesy: HP Labs) Can improve memory chips Will compensate for manufacturing defects Will help circuits do calculations at higher rates Is the key element in the interconnect fabric Will eliminate static plumbing in traditional chips with an intelligent comm. system
Alternatives (Courtesy: HP Labs)
Goal : Replace HP’s crossbar switch with an opticallyinterconnected reconfigurable switching fabric
A reconfigurable crossbar structure Certain blocks not used can be switched off thereby reducing power Manufactures can salvage flawed circuitry Significant reduction in chip cost
Future Chips made with 45 nm transistors and grid of 4 nm nanowires would be 4% as large as standard chips Clock speed will be slower but the amount of energy consumed will be lower Cost will decline (no need to invest $B in new semiconductor manufacturing Equip.
Potential Application: Optically InterconnectedFPGA!!
Solutions ?
Reconfigurable Optical Interconnect(Planar Routing)
Optical Bus (Three-Dimensional Routing)
Research Goal : Utilize unique confinement and dispersive properties of photonic crystal structuresfor the design and implementation of key elements necessary for the realization of the planar andthree-dimensional routing fabric.
Chip-scale Routing Solutions
Interconnect Key Elements
Crossbar Switch Routing Network Modulator
Electrode
SCPhC
Electrode
Optical fiber array
Vertical J-Coupler
Design Includes• Planar and 3D routing structures (Fixed routing)• Crossbar switch (Active/reconfigurable routing)• Modulator (Signal encoding)• 3D/2D optical I/O
Reconfigurable Optical Interconnect(Planar Routing)
a=400nm; d=240nm; dm=320nmneff=2.9; wwg=690nm
Dispersion diagram
Spectrum Analysis Tunability Analysis
Electrodes
Port 1
Port 2
Port 3
Port 4
1505 1510 1515 15200
0.2
0.4
0.6
0.8
1
wavelength (nm)
Tran
smisi
son
n = 2.9 (port 3)n = 2.9 (port 4)n = 2.896 (port 3)n = 2.896 (port 4)
λ=1513.6nm
Wave vector (2π/a) 0.3 0.35 0.4 0.45 0.50.254
0.256
0.258
0.26
0.262
0.264
Norm
alize
d Fr
eque
ncy(
c/a)
Δn=0Δn=-0.004
Odd mode
Even mode
-0.006 -0.004 -0.002 0 0.0020
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Refractive index variation
Port 3Port 4
λ=1513.6nm
n=2.9
n=2.896
Δn = 0.004λ=1515nm
Reconfigurable Planar Optical Switch
Input
Pass Port
Coupled Portλ = 1500nm
Switching Element
1500 1510 1520 1530 1540 1550 1560
0.0
400.0n
800.0n
1.2!
Outp
ut
Pow
er (
W)
Wavelength (nm)
Pass Port Coupled Port
1 nm resolution
Experimental
Numerical Through PortCoupled Port
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Thermo-optically• An index change of ~0.003 can be observed as the
temperature is increased by ΔT=20°C.
Tunability
• Ideally, we would like to design a device which canbe tuned with small changes in refractive index.
• A key design parameter to attain such highsensitivity device, is the ratio of the large air holediameter to the small air hole diameter surroundingthe slow light PhC waveguide (see inset)
• Optimizing such parameter to account forfabrication tolerances will not only provide us witha highly sensitive devices but will also enhance theoverall device throughput efficiency
Device Tunability can be attained in two ways:
Electro-optically• An index change of ~0.004 can be observed for a
voltage change of 0.8V using a PIN-PhC structure.
Experimental Characterization
1 × 3 Bidirectional Switch Node
A
C
B
D
a1 a2
b2 b1
c2
c1
d2
d1
Switching TableA B C D
A Χ a2,b2 a1,c1 Φ
B a2,b2 Χ Φ b1,d2
C a1,c1 Φ Χ c2,d2
D Φ b1,d2 c2,d2 Χ
PhC directional couplers can bearranged to build a networkfabric with a node footprint of150µm x 150µm.
a1, a2, b1, b2, c1, c2, d1, d2 are PIN diodes
Switching elements Self-collimation PhC
Self-Collimation Based Switch
00.10.20.30.40.50.60.70.80.9
1
1.00 1.10 1.20 1.30 1.40 1.50Switching refractive index
rela
tive
pow
er
Port 2Port 1Total
optical source
Beamsplitter
Port1
-Self collimation Photonic Crystal
Switch RegionPort 2
mirror
mirror
Device Concept
Device Design
Δn = 0
Δn = 0.1
Δn = 0.2
Simulations Device Performance
Interconnection Switching Fabric
•R. Martin, A. S., Sharkawy, E. J. Kelmelis, D. W. Prather “Integrated optical chemical sensor using a dispersion guided photonic crystal structure, SPIE Optics and Photonics 2006•R. Martin, A. S., Sharkawy, E. J. Kelmelis, D. W. Prather “A reconfigurable self-collimation-based photonic crystal switch in silicon” SPIE Photonics West 2007 (Invited Paper)
SPIE newsroomarticle 1933
Port IIIInput
Port
I
Splitter 1
Port
II
Splitter 2
Ws=69nmWs=78nm
Port IIIInput
Port
I
Splitter 1
Port
II
Splitter 2
Ws=69nmWs=78nm
~50% Reflected
~50% Transmitted
~66% Reflected
~34% Transmitted
~100% Reflected
~0% Transmitted
Input,
Pin
PI=50%Pin PII=33%Pin PIII=17%Pin
Port I Port IIIPort II
Simulation
Fabricated PrototypeCharacterization
1 0 0
1 1 0
1 1 1
1 0 0
1 1 0
Two-Bit Optical Analog-to-Digital Converter(Passive)
Design HighlightsDesign Highlights•• Design utilizes unique dispersive properties of self collimated Design utilizes unique dispersive properties of self collimated PhCsPhCs•• Design is less sensitive to fabrication tolerances and hence no need for high -end Design is less sensitive to fabrication tolerances and hence no need for high -end cleanroomscleanrooms•• Ideal for low resolution (> 4bits) ADC applications Ideal for low resolution (> 4bits) ADC applications
Two- bit Optical A/D design
X (mm)
Y (m
icro
n)
Steady State of Hz
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.2
0.4
0.6
0.8
1.0
1.2
70%
30%
25nm 50%
50%
35nm 600nm
100%
0%
SPIE newsroomarticle 15805
00
0
111
Port IPort IIPort III
01 11
1
0
0
000
1 2 3 4 5 62 3 4 5 600
20
40
60
80
100
111
00 01 10 11 10 01 00
0
0
11
0
11
0
1
00
PI
PII
PIII
Pin
Perc
enta
ge P
ower
Time
00
0
111
01 11
1
0
0
000
1 2 3 4 5 62 3 4 5 600111
00 01 10 11 10 01 00
0
0
11
0
11
0
1
00
I
II
III
in
Binary Code
Optical Quantization
Pin = 1m
WP
in = 500µWP
in = 200µW
Cascaded Active PhC A/D Units
Advantages:• Each coupled PhC module can be considered as an independent unit which can be tuned separately!• Ultra-compact design (footprint is ~ 5µm*5µm for each unit)• High sensitivity (Δn ~0.004)
Current flow
Fabricated device (2 bit optical ADC)
Unit 1(LSB)
Unit 2 Unit 3MSB
Experimental Characterization
Sensitivityof 1.78nm
Two-Bit Optical Analog-to-Digital Converter(Active)
I/V Characteristics of PIP
Fabricated PrototypeCharacterization
-30 -20 -10 10 20 30 40
-3
-2
-1
0
1
2
3
4Measured I/V
curve
V (V)
I (mA)
-40 -30 -20 -10 10 20 30 40
-3
-2
-1
0
1
2
3
4Measured I/V
curve
V (V)
I (mA)
-40
Electrode
SCPhC
Electrode
Time step (1 time step =0.5 Sec)0 2
.10 15 20 25 30 35 40 45 50
0.2
0.40.60.811.21.4
1.61.8
Opt
ical O
utpu
t po
wer (
nW) Applied
40V
Transmission Response at λ=1428nm
V = 0 volt
V = 30 volt
V = 40 volt
P
P
IIncident Beam
SCPhC
Output
Device Design
Optical Modulator Design and Development
PIN Diode Fabrication and ElectricalCharacterization
Fabricated PINDiode
•Threshold voltage is ~.5V and series resistanceduring on state is ~10kΩ.•Comparing with PIP diode, at 4mA, applied bias is45V or 5V higher than PIP.•This high impedance is contrary to 2D simulationsand will need to be addressed in future designs.
Diode I-V characteristics
0.00E+00
2.00E-05
4.00E-05
6.00E-05
8.00E-05
1.00E-04
1.20E-04
1.40E-04
-1 -0.5 0 0.5 1 1.5 2
Voltage (V)
Cu
rren
t (A
)
P+ Electrode N+ Electrode
Vbias
PhC
30µm
PIN Diode Optical Characterization
0.00E+00
2.00E-10
4.00E-10
6.00E-10
8.00E-10
1.00E-09
1.20E-09
1.40E-09
1.60E-09
1.80E-09
1 6 11 16 21 26 31 36 41 46 51 56 61 66
Time step (1 time step = .1s)
Ou
tpu
t p
ow
er
(W)
Transmitted output power at λ = 1570 nm
Output
Vbias = 0V
Vbias = 45V
45V biasapplied
• Modulation depth is ~ 80% with an applied bias of 45V.
• Improved fall time over PIP junction.
• Rise and fall times limited by bandwidth (5 Hz) of detector.
Top view of PhC
Optical Bus (Three-dimensional Routing)
Dispersion Engineering• To engineer the dispersive properties of photonic crystals, dispersion surfaces must be extracted.
• A dispersion surface represent the solution of Maxwell’s equations within the entire Brillouin zone
• Ability to engineer dispersion properties of photonic crystals, provide;• New paradigm for synthetic optical properties• New paradigm for configurability (alterable media)• No bandgap is necessary hence more material choice (low and high index)• Less constraint for tight fabrication tolerances necessary with bandgap based applications
G M K G0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Wave vector (2 π /a)
Normalized Frequency(c/a)
EM Photonics Inc
ΓΓ
Dispersion diagram Dispersion surfaces
Types Of DispersionHomogenous Slab Dispersion surface
-0.6 -0.4 -0.2 0 0.2 0.4 0.6-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.10102
Equi-frequency contour (EFC)
Patterned PhC Slab (Square) Dispersion surface
-0.6 -0.4 -0.2 0 0.2 0.4 0.6-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.47297
-0.6 -0.4 -0.2 0 0.2 0.4 0.6-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.13908
-0.6 -0.4 -0.2 0 0.2 0.4 0.6-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.53567
(EFCs)
Patterned PhC Slab (Hexagonal)Dispersion surface
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.28968
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.35051
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.10259
(EFCs)
Low index dispersion-based devices
• No bandgap is needed
• Low-index materials holdthe potential
• EFCs can be engineered toexhibit strong anisotropy
( )0k!
kv
kv
kv
kv
gvv
gvv
gvv
gvv
( )0k!
kv
gvv
gvv
gvv
gvv
gvv
gvv
gvv
kv
kv
kv
gvv
2 4 6 8123456789
x (micron)
y (m
icron
)
2 3 4 5 6 7 8 91
2
3
4
5
6
x (micron)
y (m
icron
)
• From the relation: the direction of propagation of EM waves is in the direction of the gradient to the dispersion contour.
( ),g k k! "=#
-0.3 -0.2 -0.1 0 0.1 0.2 0.3-0.3
-0.2
-0.1
0
0.1
0.2
0.3
Normalized frequency: 0.31
-0.3 -0.2 -0.1 0 0.1 0.2 0.3-0.3
-0.2
-0.1
0
0.1
0.2
0.3
-0.3 -0.2 -0.1 0 0.1 0.2 0.3-0.3
-0.2
-0.1
0
0.1
0.2
0.3
vg
Photonic Crystal Dispersion Waveguides
gvv
-0.6 -0.4 -0.2 0 0.2 0.4 0.6-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kx
ky
Equi-Frequency =0.10102
gvv
( )0k!
ikv
gvv
gvv
gvv
gvv
gvv
gvv
ikv
ikv
ikv
-0.6 -0.4 -0.2 0 0.2 0.4 0.6-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
kz (2π/a)
kx (2π
/a)
ky=0
0.250.25
0.25
0.25
0.25
0.250.25
0.25
0.25
0.25 0.27 0.27
0.27
0.270.27
0.27
0.29 0.29
0.29
0.29
0.31
0.31
0.25
0.250.25
0.25
0.250.25
0.25
0.25
0.25
0.25
0.25
0.25
0.27 0.27
0.27
0.27
0.270.27
0.27
0.29
0.29
0.290.29
0.29 0.31
0.31
0.31
0.27
0.27
0.27
0.27
0.290.29
0.29
0.29
0.29
0.29
0.29
0.29
0.31
0.31
0.31
0.31
0.31
0.31
0.31
0.31
EFCs, f = 0.3c/aBands #3, 4, and 5
Bands #3 and 4Electric Field Intensity
G X M R G
0.05
0.1
0.15
0.2
0.25
0.3
0.35
K
Freq
uenc
y (c
/a)
ΓXM
R
r/a=0.45; εr=12.25; a is lattice constant
Dispersion Properties of 3D PhC Structures
r/a= 0.55 , a/λ=0.34, 16 a3 structure
x(a)
y(a)
Hz (Intensity)
0 2 4 6 8 10 12 14 16
2
4
6
8
10
12
14
16
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Two dimensional view Three dimensional viewConceptual rendering of airspheres in silicon, bend is
achieved via the 45º air mirror
3D Self-collimatinglattice 45
0 air mirror
Self-Collimation in 3D PhC
(a) Process sequence schematic for a modified TM-DRIE process that would yield buried 3DPhCs and (b) Conceptual rendering showing square lattice etch mask leading to fabrication of3D simple cubic PhCs
3D PhC fabrication: Novel Approach using SiliconMicromachining
Designed structure, simulated (8 layers)
zoom-in view of simulated structure
SEM image of fabricated device
SEM image of 3D photonic crystal at theinterface of 3rd and 4th layer
Comparison of Simulated and Fabricated 3DStructures
SEM images of overlapping voids etched insilicon.Single layer with excellent uniformity
(1 unit cell) 1 Layer
4 Layers
3 Layers
5 Layers
Fabrication of Buried 3D Structures forSelf-Collimating PhCs
1st 2nd 3rd
1st Apply new resist layer
2nd Exposure
3rd Post exposure bake (PEB)
Begin with spin-coating resist on a substrate
After repeating the processing loop
Multi-layer resist spin-coating systemwith fully controlled environment
Improved mask-making strategy for large area(2mmX2mm) PhCs and less stitching error Vertically confined exposure to ensure
pattern deposition in the top layer
5ì m
Engineered defects in PhCs Free standing PhCs membrane
Device for 1.5um wavelength Arbitrary 3D structure
8-layer woodpile structure
2mmX2mm
PhCs
Fabrication process
Fabrication of Large Area 3D PhCs in Polymer
2D plots on the plane that light leaves PhCs
-300 -250 -200 -150 -100 -50 0 50 100
0
0.05
0.1
0.15
0.2
0.253 deg.5 deg.7 deg.9 deg.11 deg.13 deg.
Woodpile polymer PhC51µm
x (µm)
Line scans along x direction with different incidentangles
trans
mis
sion
Performance
-235µm -140µm -112µm -86µm -71µm -61µm
Incident angle (deg.)
Bea
m o
ffse
t (µ
m)
240
3 5 7 9 11 130
20
40
60
80
100
124
0
Tran
smis
sion
(%)
θinc=3o θinc=5o θinc=7o θinc=9o θinc=11o θinc=13o
Beam Steering in 3D Polymer based PhCs
θουτ=50oθουτ=54.3oθουτ=59.33oθουτ=65.5oθουτ=69.98oθουτ=77o
Current & Future Chips are more Powerful Contain embedded memories and multipliers Demonstrated ability to rival (and assist) supercomputers
Routing Is The Limiting Factor Delay, area, and CAD considerations limit performance Need a radically new architecture to keep up
Conclusion
Optically Interconnected Chips Photonic Crystal interconnects are VERY promising Virtually eliminate the current obstacles to future chip growth Potentially enable an optically interconnected FPGA