NH – 67, Karur – Trichy Highways, Puliyur C.F, 639 114 Karur District

DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING

COURSE NOTES

SUBJECT: DIGITAL ELECTRONICS SUBJECT CODE: EC2203

CLASS: II YEAR ECE

UNIT-II

COMBINATIONAL CIRCUITS

Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor –

Parallel binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead

adder – Serial Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider -

Multiplexer/ Demultiplexer – decoder - encoder – parity checker – parity generators –

code converters - Magnitude Comparator.

INTRODUCTION

In digital circuit theory, combinational logic (also called combinatorial logic)

is a type of logic circuit whose output is a pure function of the present input

only.

This is in contrast to sequential logic, in which the output depends not only on

the present input but also on the history of the input.

In other words, sequential logic has memory while combinational logic does

not.

APPLICATIONS

Combinational logic is used in computer circuits to do Boolean algebra on

input signals and on stored data.

Practical computer circuits normally contain a mixture of combinational and

sequential logic.

For example, the part of an arithmetic logic unit, or ALU, that does

mathematical calculations is constructed in accord with combinational logic,

although the ALU is controlled by a sequencer that is constructed in accord

with sequential logic.

For n input variables, there are 2

n possible input combinations. For each input

there is only one output.

A combinational circuit is described by m Boolean functions, one for each

output variable. Each output function is expressed in terms of n input

variables.

ANALYSIS PROCEDURE

Procedure starts with getting Boolean expression and truth table from the logic

circuit or by computer simulation program. Check first whether the given circuit is

combinational or not.

To get Boolean expression from circuit,

i) Label all gates outputs which are the direct function of input variables with

arbitrary symbols and determine Boolean function for each gate output

ii) Label all gates outputs which are the functions of input variables and

previously labeled gates and determine Boolean function for these gates

iii) Repeat step ii until the output of the circuits are obtained.

iv) By repeated Substitution of previously defined symbols, outputs in terms

of input variables is obtained

Example:

Logic diagram for analysis example

T1, T2 and F2 are defined first.

T1 = A+B+C

T2 = ABC

F2= AB+AC+BC

T3 by next step.

T3 = F2’T1

= (AB+AC+BC)’ A+B+C

F1 is the finalized expression for one output

F1 = T3+T2

= A’BC’+A’B’C+AB’C’+ABC

Truth table for the above example

Truth table is constructed directly from the Boolean expression. From the circuit, start

constructing from the calculation for each logic gate until the output of the circuit is

reached.

DESIGN PROCEDURE

Design starts from the specification of the problem and culminates in a logic

circuit diagram or set of Boolean functions from which the circuit is obtained.

Steps:

i) Determine the number of inputs and outputs from the specification of the

problem.

ii) Derive the truth table.

iii) Obtain simplified Boolean functions for each output as function of inputs

iv) Draw the logic diagram and verify the correctness of the design

Verbal specification of the problem should be interpreted correctly in truth table.

Output binary functions in truth table are simplified by algebraic manipulation, map

method or by computer simulation depending upon the application.

Example: BCD to Excess-3 code.

Here the BCD is considered under 4-bit case. Excess-3 also have the same number of

bits. Conversion table is shown below.

Truth table for BCD to Excess-3 code conversion

K-Map simplification for the outputs (w,x,y,z) is done as shown under to arrive at the

simplified Boolean function.

The two level logic diagram for the derived Boolean expression is drawn directly. But

the function may be simplified further as

Logic diagram for BCD to Excess-3 conversion

ARITHMETIC CIRCUITS

Various arithmetic operations are encountered in computing tasks. Most basic

operation is addition of two binary digits. Starting with the addition of 2 LSb and

adding the next higher order bit with the generated carry and proceeds through the

number.

2.3.1 Half adder

It is a Combinational circuit doing the addition of two bits only. Output is Sum

and Carry.

Figure 2.3 Half adder

The output Boolean expressions are,

So = Ao’Bo +AoBo’

Co = AoBo

The logic diagram for the above expression can be expressed as follows:

logic circuit of Half adder Simplified circuit

Now this is only a half adder, although we are generating a carry, we cannot add in

the carry from the previous addition.

FULL ADDER

For all other bits (except the lsb) a half adder will not suffice because there

may be a carry input from a previous stage. ie) It is a Combinational circuit doing the

addition of three bits only. (Two information bit+one previous carry).

Figure 2.6 Full adder and Truth table

Full adder can be built by using two half adders as shown below.

Two bits are added and the sum is

given as one of the input to the

next half adder along with the

previous carry. Carry in cascaded

blocks are added separately to

produce the final carry.

Remember the Boolean operation

For half adder:

S’K = AK BK

Figure 2.7 Full adder in terms of

half adder

C’K = AKBK

For full adder:

SK = AK BK CK-1

CK = AKBK + CK-1(AK BK)

Proof:

Figure 2.8 Simplified Full adder

THE PARALLEL (BINARY) ADDER

Also called ripple carry adder used to add two n-bit numbers. it consists of n full

adders where the carry output of each stage is the carry in of the next stage.

Simplified Full adder

Initial carry, C-1 , is zero. But to get Co, propagation delay, 2 gate delay, inside Full

adder is encountered. Totally 8x2 gate delays are there to get C3 finally. This is

avoided by using Carry look ahead generator which is generating Carries

simultaneously.

Full adder Circuit

From the above full adder circuit,

Where Gi is Carry generate as it produces the output carry regardless of the input

carry and Pi is Carry propagate as it is associated with the carry propagation from

input to the output.

We can have the following Boolean expression from the figure 2.10.

Above Boolean functions is implemented by the logic diagram shown in 2.11.

Logic diagram of a Carry look ahead generator

A 4-bit Binary adder is built with the Carry look ahead generator as shown in figure

2.12

4-bit full adders with look ahead carry

In Connection with the above diagram, all the output carries are generated

simultaneously by having Gi, Pi and Co as the inputs.

DECIMAL ADDER

Decimal numbers are presented in coded form in all case of digital devices for

manipulation. Accepting numbers in coded form and presenting the result in same

form.

In these cases 9 inputs (8 data+1 Previous carry) and 5 outputs(4 data+1 output carry)

are needed.

BCD ADDER

One example of the decimal adder is BCD adder. It is useful because many

digital devices process + display numbers in tens in BCD each number is defined by a

binary code of 4 bits.

We will now look at into the effort of using a binary adder to add 2 single digit BCD

numbers.

The maximum possible BCD number is 9. So for adding two BCD number,

9+9+1(for Carry) = 19 is the maximum value the BCD adder should represent at its

output.

Following table represents the BCD, binary values for the corresponding decimal

number till 19. We can use this table to detect the binary combinations which are

greater than the BCD number 1001. ie) 9.

From the table, (Look at the Binary Sum column)

For the first group of numbers, partitioned till 9, BCD and binary are

equal.

In the next 6 combinations, Z8 is 1 always also with 1s in either Z4 or

Z2 places. This condition is stated as Z8Z4+ Z8Z2

In the last 4 combinations, K is 1.

As a consequence we can deduce the condition of getting carry once the result of the

summation of a binary adder exceeds the number 9.

C = K+ Z8Z4+ Z8Z2

Block diagram of a BCD adder

So When C =1, 0110 is added to the result to convert the binary number to BCD

number. The entire process is implemented as a block diagram in figure 2.13

BINARY MULTIPLIER

Binary multiplier performs the operation similar to the decimal multiplication

using partial products method.

Consider two 2-bit number B1 B0 and A1 A0

B1 B0

A1 A0

A0B1 A0B0

A1B1 A1B0

C3 C2 C1 C0

Block diagram of 2-bit multiplier

For J multiplier bits and K multiplicand bits, we need

(J*K) AND gates

(J-1) K-bit adders to produce (J+K) bits as result.

MAGNITUDE COMPARATOR

It compares two numbers and gives relative magnitudes.

3-variables used to specify the result for three conditions (>, =, <)

Thus for an n-bit comparator 22n

entries are needed in the truth table. So

design is cumbersome unless we use algorithmic procedure.

Consider for 4-bit comparison of A A3 A2 A1 A0

and B B3 B2 B1 B0

A=B If all the bits are equal. Ex-NOR gate is used to check this status as

Xi = Ai Bi + A’i B’I for i = 0,1,2,3

Finally the condition is, (A=B)= X3X2X1X0

A>B if MSB of A= 1 and that of B = 0. This can be stated as,

(A>B) = A3B3’ + X3A2B2’ + X3X2A1B1’ + X3X2X1A0B0’

B>A if MSB of A= 1 and that of B = 0. This can be stated as,

(A>B) = A3’B3 + X3A2’B2 + X3X2A1’B1 + X3X2X1A0’B0

The stated condition is implemented simply by the logic diagram as shown in figure

below.

A0 A1 B0 B1 C0 C1 C2 C3

4-bit magnitude comparator

The same circuit can be used to compare the magnitudes of two BCD digits.

CODE CONVERSION

Code conversion is necessary to achieve the compatibility between two

different systems following different coding schemes. The code that has to be

converted is applied as the inputs and the output gives the transferred code. BCD to

Excess-3 conversion was given already.

EXCESS-3 TO BCD CODE CONVERSION

The truth table for excess-3 to BCD is constructed and from the table the equation for

conversion of BCD to excess-3 is obtained. It is then implemented with the help of

logic gates.

TRUTH TABLE

EXCESS-3 BCD

A B C D W X Y Z

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

By applying K-map method the simplified circuit is shown below

345

6

7411

7411

7411

330k

7432

X

LED

12

1312

7432

12

D

Y

LED

A

7486

4

56

7411

56

7411

9

108

330k

LED

C

330k

LED

12

1312

W

34

1

23

B

7432

74

04

1

23

1

23

345

6

Z

330k

Excess-3 to BCD converter

BINARY TO GRAY CODE CONVERTER

The first bit of the gray code will be the same as the first bit of the binary code.

Second bit of gray code is obtained by the XOR operation of first two bits in the

binary code .Similarly third bit is obtained by the XOR combination of second and

third bit in binary and so on.

TRUTH TABLE

DECIMAL BINARY CODE

D C B A

GRAY CODE

G3 G2 G1 G0

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 0 1 0

4 0 1 0 0 0 1 1 0

5 0 1 0 1 0 1 1 1

6 0 1 1 0 0 1 0 1

7 0 1 1 1 0 1 0 0

8 1 0 0 0 1 1 0 0

9 1 0 0 1 1 1 0 1

10 1 0 1 0 1 1 1 1

11 1 0 1 1 1 1 1 0

12 1 1 0 0 1 0 1 0

13 1 1 0 1 1 0 1 1

14 1 1 1 0 1 0 0 1

15 1 1 1 1 1 0 0 0

4

56

G3

G1

LED

C B

G0

LED

330k

9

108

IC 7486

330k

1

23

A

330k

G2

330k

LED

LED

D

Binary to Gray converter

GRAY TO BINARY CODE CONVERTER

TRUTH TABLE

GRAY CODE BINARY CODE

G3 G2 G1 G0 D C B A

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

G3 G4

B

1

23

IC 7486

IC 7486

LED

LED

9

108

330k

330k

LED

330k

G2

CLED

A

4

56

G1

D

330k

IC 7486

Gray to Binary converter

PARITY CHECKING AND GENERATION

It is the simple error detecting code by appending or prepending one (parity)

bit in each data word at the transmitter.

The bit added will make the total number of 1s in the word (including parity

bit) as even or odd.

The receiver detects the error by counting the number of 1s in each word.

IC 74180 is used to check/generate even/odd parity of the 9-bit data.

PIN configuration

The data (X0 – X7) along with the Even or odd input (9-bits in total) is

checked by the IC.

It will act as the parity generator if PE = 1, PO = 0 (shown in first two entry in

truth table).

These inputs also taken into account while counting for the 1s. ∑ even output

will glow to generate a 1 to make the total number of 1s even. The last two

entries show the IC operation as parity checker. It checks the number of 1s in

those 9-bits and gives output accordingly.

Both the ∑ outputs are produced simultaneously. Output is derived from any

of these two pins depending up on the parity we follow.

TRUTH TABLE

INPUT OUTPUT

No.of.high

Data input (X0-

X7)

PE PO ∑ EVEN ∑ ODD

EVEN 1 0 1 0

ODD 1 0 0 1

EVEN 0 1 0 1

ODD 0 1 1 0

IC 74180 is cascaded to increase the word length capability from 9-bit to 16-bit. It is

shown below. MODE = 1 for checking parity and for MODE = 0, for generating

parity.

7404

1 2

>EVENO/P

ODDO/P

>

330k

>

E EVEN

>

LED

>

EVEN

330k

>

>

IC 74180

MODE

>

X11 E ODD

> LED

IC 74180

ODD

>

X6

X0

X14

>

X15

X1

X12

>

X8

X2

X7 >

X3

> X4

X13

ODD

EVEN

>>

X9

X5

X10 >

>

bit parity checker/Generator

DECODERS

Often, digital information represented in some binary form must be converted into

some alternative digital form. This is achieved by a multiple-input, multiple output

network referred to as a decoder. The most commonly used decoder is the n-to-2n-line

decoder:

The structure of a such decoder is straightforward. Consider the truth table of a 3-to-

8-line decoder:

This corresponds to the logic diagram shown below:

A particular application for this decoder is binary to-octal conversion. The input

variables represent a binary number, and the outputs represent the eight digits in the

octal number system.

DECODERS WITH AN ENABLE INPUT

Some decoders include one or more enable inputs to control the circuit operation. The

logic diagram and truth table of a 2-to-4-line decoder are shown below:

A decoder with enable input can function as a demultiplexer. The above decoder can

function as a 4-to-1-line demultiplexer when E is taken as a data input line and A and

B are taken as the selection inputs.

Decoders with enable inputs can be connected together to form a larger decoder

circuit. A 4-to-16-line decoder realized using two 3-to-8-line decoders is shown

below:

When w = 0, the top decoder is enabled and the other is disabled. The bottom decoder

outputs are all 0’s, and the top eight outputs generate minterms 0000 to 0111.

When w = 1, the enabled conditions are reversed; the bottom decoder generates

minterms 1000 to 1111, while the outputs of the top decoder are all 0’s.

COMBINATIONAL LOGIC IMPLEMENTATION

An n-to-2n-line decoder is a minterm generator. Recall that any Boolean function is

describable by a sum-of-minterms. Thus, by using OR-gates in conjunction with an n-

to-2n-line decoder realizations of Boolean functions are possible. However, these

realizations do not correspond to minimal sum-of-products.

Consider the pair of expressions:

F1(X2,X1,X0) = )5,4,2,1(

F2(X2,X1,X0) = )7,5,1(

Using a single 3-to-8-line decoder and two ORgates, the following realization is

obtained:

When more than ½ the total number of minterms must be OR-ed, it is usually more

economical to use NOR-gates rather than OR-gates to do the summing. Consider the

pair of expressions:

F1(X2,X1,X0) = )6,5,4,3,1,0(

F2(X2,X1,X0) = )6,4,3,2,1(

These may be realized with a 3-to-8-line decoder and two OR-gates having a total of

11 terminals between them. However, a more efficient realization is to re-write the

expressions as:

F1’’(X2,X1,X0) = F1’(X2,X1,X0) = )7,2(

F2’’(X2,X1,X0) = F2’(X2,X1,X0) = )7,5,0(

This corresponds to the realization shown below:

A total of five gate-input terminals are needed.

ENCODER

Perform the inverse operation of decoders. An encoder has 2n (or fewer) input lines

and n output lines. The output lines generate the binary code corresponding to the

input value. An example of an encoder is the octal-to-binary encoder whose truth

table is as follows:

The equations for the three outputs are:

Z = D1 + D3 + D5 + D7

y = D2 + D3 + D6 + D7

x = D4 + D5 + D6 + D7

The encoder can be realized with three OR-gates.

PRIORITY ENCODER

The encoder defined before has the limitation that only one input can be active

at any given time.

If two inputs are active simultaneously, the output produces an undefined

combination.

This is resolved by establishing an input priority function. The truth table of a

four-input priority encoder is:

In addition to the two outputs, x and y, the circuit has a third output V; this is a

valid bit indicator and is set to 1 when one or more inputs are equal to 1. X’s in

the output represent don’t-care conditions.

X’s in the input columns are for representing the truth table in condensed form.

Instead of listing all 16 minterms of four variables, the truth table uses

an X to represent either 1 or 0.

According to the table, D3 has the highest priority followed by D2 and D1.

The maps for simplifying outputs x and y are shown below:

The condition for output V is an OR function of all the input variables:

V = D0+D1+D2+D3

The priority encoder is implemented as follows:

MULTIPLEXERS

A multiplexer is a circuit that selects binary information from one of many input lines

and directs it to a single output. Normally, there are 2n

input lines and n selection lines

whose bit combination determine which input is selected.

The logic and block diagrams of a 2-to-1-line multiplexer are shown below:

The circuit has two data input lines, I1 and I2, one output line Y, and one selection

line S.

When S = 1, the lower AND gate is enabled and I1 has path to the output. This

multiplexer acts like a switch that selects one of the two sources.

A 4-to-1-line multiplexer is shown below:

A multiplexer is also called a data selector, since it selects one of many inputs

and steers the binary information to the output line.

In general, a 2n-to-1-line multiplexer is constructed from an n-to-2

n decoder by

adding to it 2n input lines, one to each AND gate. The outputs of the AND

gates are applied to a single OR gate.

As in decoders, multiplexers may have an enable input to control the operation

of the unit.

By interconnecting several multiplexers in a treelike structure, it is possible to

produce a larger multiplexer. For example, a 16-to-1 line multiplexer may be

constructed using five 4-to-1-line multiplexers as follows:

MUX/DEMUX TRANSMISSION SYSTEM

One of the primary applications of multiplexers is to provide for the transmission of

information from several sources over a single path. This process is known as

multiplexing.

Eg. the multiplexing of conversations on the telephone system.

When a multiplexer is used in conjunction with a demultiplexer, an effective means is

provided for connecting information from several source locations to several

destination locations. This basic application is illustrated below:

By using n of the structures shown above in parallel, an n-bit word from any of four

source locations is transferred to the four destination locations.

SUMMARY

Thus, this unit provides a brief knowledge over adder, subtractor circuits. It also

provides a sound knowledge on multiplexers, de-multiplexers, decoder, encoder,

parity generator and magnitude comparator circuits.