laxmi institute of technology , sarigam · half and full adder – half and full subtracter –...

Laxmi Institute of Technology , Sarigam

Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad

TEACHING SCHEME

SYLLABUS

Unit Topics Teaching Hours

Module Weightage

I Number Systems: Decimal, Binary, octal, and hexa-decimal number, systems, binary arithmetic. Number base conversion, Complements Codes: Binary code, excess-3 code, gray code, error detection and correction codes.

07 20

2 Logic families: Positive logic and Negative Logic, AND, OR,NOT,NAND,NOR, X-OR GATE, INHIBIT CIRCUIT, Significance and type like TTL, CMOS, interface with different logic families, application relevant information, electrical characteristics,

04 08

3 Boolean Algebra: Introduction, Logic Operators, Postulates and theorems, properties –Product of Sums and Sum of Products– Karnaugh Map method – Two, three, four, five variable K-maps, Converting Boolean expressions to Logic and Vice versa, NAND and NOR implementation – Don’t-Care conditions – The tabulation method

10 20

4 Combinational Logic Circuit: Half and full Adder – Half and full Subtracter – Binary

parallel adder– BCD Adder, Decimal adder – Magnitude comparator – Encoders & Decoders – Multiplexers–De-multiplexer

06 14

5 Flip Flops and Sequential Logic and Circuits: Basic difference between Combinational logic and

Sequential logic –Flip-Flops like S-R , J-K, D, Master Slave– Triggering of (level andEdge) flip-flops –Asynchronous and Synchronous Inputs –Excitation tables for flip-flops

07 15

Semester Course Title Course Code Theory Paper L T P

4 Digital Electronics 2140910 4 0 2 70



Ripple and Synchronous counters – Registers – Shift registers –Pulse Generation.

6 Memory: Role of Memory in Computer Systems– Types and

Terminology– Organization and operation, Reading & Writing, RAMs, ROMs, PROMs – Semiconductor RAM, Flash Memory

04 08

7 D/A and A/D Converters: Digital to Analog Converters D/A converter Specifications, Types of D/A converters, Mode of Operation, BCDInput D/A converter, Integrated Circuit D/A Converters, D/A converter Applications, A/D converters, A/D Converter Specifications, A/D Converter Technology, Types of A/D converters, Integrated Circuit A/D Converters, A/D converter Applications

07 15

List of Reference Books S.No Book Title Author Publication

1 Fundamentals of Digital Electronics A. Anandkumar, PHI

2 Digital Electronics Principal and Integrated Circuits

Anil K. Maini, WILEY-INDIA

3 Digital Logic and Computer Design M. Morris Mano,

PHI

4 Digital Computer Electronics Malvino & Brown, Tata McGraw Hill



LECTURE PLAN

Department: Electrical Engineering Name of Subject In charge: Ms Nipa D Modi

Subject Name: DIGITAL ELECTRONICS Subject Code: 2140910 Academic Year: 2018-19 Semester: 4

Lect No. Topics To Be Covered Planned

Date Actual Date

Remarks/ Teaching

Aids / Books Unit-01: Number Systems

1 Introduction to Number Systems Decimal, Binary,

17/12/2019 17/12/2019

2 Octal, and Hexa-Decimal number systems, 19/12/2019 19/12/2019 3 binary arithmetic, Complements 20/12/2019 20/12/2019 4 Number base conversion, 21/12/2019 28/12/2019 5 Binary code, Excess-3 code, 24/12/2019 02/01/2019 6 Gray code Conversion 26/12/2019 03/01/2019 7 Error detection and Correction Codes 27/12/2019 04/01/2019

Unit-02: Logic families:

8 Positive logic and Negative Logic, AND, OR, NOT- INHIBIT CIRCUIT

02/01/2019&

03/01/2019

07/01/2019 &

08/01/2019

9 NAND,NOR, X-OR GATE- INHIBIT CIRCUIT 04/01/2019

& 07/01/2019

09/01/2019 &

10/01/2019

10 Significance and type like TTL, CMOS, interface with different logic families, 09/01/2019 10/01/2019

11 Application relevant information, 10/01/2019 11/01/2019

12 Electrical Characteristics, 11/01/2019 16/01/2019

Unit-03: Boolean Algebra

13 Boolean Algebra: Introduction, Logic Operators, 16/01/2019

& 17/01/2019

17/01/2019, 18/01/2019, 21/01/2019,



14 Postulates and theorems, 18/01/2019

& 21/01/2019

23/01/2019, 24/01/2019

15 properties –Product of Sums and Sum of Products– 23/01/2019

16 Karnaugh Map method – Two, three, 24/01/2019

17 four, five variable K-maps, 25/01/2019

18 Converting Boolean expressions to Logic and Vice versa, 28/01/2019

19 NAND and NOR implementation – 30/01/2019

20 Don’t-Care conditions 31/01/2019

21 The tabulation method 01/02/2019

Unit-04: Combinational Logic Circuit

22 Combinational Logic Circuit: Half and full Adder 04/02/2019

23 Half and full Subtracter 06/02/2019

24 Binary parallel adder 07/02/2019

25 BCD Adder, Decimal adder 08/02/2019

26 Magnitude comparator 11/02/2019

27 Encoders & Decoders 13/02/2019

28 Multiplexers–De-multiplexer 18/02/2019

Unit-05: Flip Flops and Sequential Logic and Circuits:

29 Basic difference between Combinational logic and Sequential logic – Flip-Flops like S-R , 20/02/2019

30 J-K, D F/Fs 21/02/2019

31 Master Slave 22/02/2019


Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad 32 Triggering of (level and Edge) flip-flops 25/02/2019

33 Asynchronous and Synchronous Inputs Excitation 27/02/2019

Unit-06: Memory:

34 Role of Memory in Computer Systems 28/02/2019

35 Types and Terminology– Organization and

operation, 01/02/2019

36 Reading & Writing, RAMs, 06/03/2019

37 ROMs, PROMs 07/03/2019

38 Semiconductor RAM, Flash Memory 08/03/2019

Unit-07: D/A and A/D Converters:

39 Digital to Analog Converters D/A converter Specifications, 11/03/2019

40 Types of D/A converters 13/03/2019

41 Mode of Operation 14/03/2019

42 BCD-Input D/A converter 15/03/2019

43 Integrated Circuit D/A Converters 18/03/2019

44 D/A converter Applications, A/D converters 20/03/2019

45 A/D Converter Specifications, A/D Converter Technology 21/03/2019

46 Types of A/D converters 22/03/2019

47 Integrated Circuit A/D Converters, 25/03/2019

48 A/D converter Applications

27/03/2019



Subject In Charge Head of the Dept.

Total Planned Lectures 48

Total Actual Lectures



Mid semester -1 : Examination Paper:

Laxmi Institute of Technology , Sarigam Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmedabad

Academic Year 2018-19 Centre Code: 086 Examination : Mid Semester Examination Branch: EE Semester: 4 Sub Code: 2140910 Sub: Digital Electronics Date: 01/02/2019 Time:- 9:00 am TO 10:00am Marks: 20 Note: Attempt any TWO QUESTION

Q.1

Do as given direction: marks 1. (43)8 =( )10= ( )2 2 2. ( B9F.AE)16= ( )8 1 3. (214)10= ( )8 1 4. (10110)2=( )10=( )16 2 5. Find 1’s and 2’s complement of given binary number: (10110010)2 2 6. Compare BCD & binary Codes. State advantage & disadvantage of the same. 2

Q-2

Do as given direction: 1. Add ( 569) and (687) in BCD 3 2. Perform ( 83)10 – (21)10 using 9’s complement method 3 3. Convert (29)10 into Excess-3 and Gray code 2 4. Perform Subtraction using 2’s complement method: (1101101)2 – (11010)2 2

Q-3

Do as given direction: 1. Give the classification of Logic gates. Which gates can be consider as Universal Gate

and why? Implement Ex-OR gate using only NOR Gate. 4

2. Write the statement for De-Morgan’s theorem. Explain the terminology with logic diagram and Truth table.

3

3. What is hamming code. Write its limitations. Generate hamming code for 1 1 1 0 1 1 0 0 1 with even parity.

3



Department of Electrical Engineering Academic Year : 2018 -2019

ASSIGNMENT – I

Name of the Subject: Digital Electronics Date: 02.01.2019 Subject Code : 2140910 S. No Question Remarks

1. Do as given direction: (2140)10 = ( )8 2. (128.225)10. = ( )2 3. ( 2345.99)10 = ( )16 4. (255.255)8 = ( )2 5. ( 76.54 )8 = ( )16 6. ( 0.8 )10 = ( )2 7. ( B9F.AE )16 = ( )8 8. ( 2003.31 )10 = ( )8 9. ( 105.15 )10 = ( )2 10. ( 378.93 )8 = ( )2 11. ( 2598.675 )10 = ( )16 12. ( 756.603 )8 = ( )16 13. ( 10111.011 )2 = ( )8 =( )16 14. ( 231.23 )4 = ( )10 15. ( 4F7.A8 )16 = ( )8 16. ( F297 )16 = ( )2 17. ( 452 )10 = ( )16 18. ( 2035 )8 = ( )16 19. ( 420.6 )10 = ( )8 20. ( 2EB7 )10 = ( )10 21. ( 10110 )2 = ( )16

2. How can we obtain one's and two's compliment of a binary ? Explain with example ?

3. Find out 2's compliment of the following numbers :- (1). ( 110110)2 (2). ( 010101 )2


Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad Date of Submission: 09.01.2019

QUESTION BANK

UNIT- I

1) Convert the following numbers to decimal (i) (10001.101)2 (ii) (101011.11101)2 (iii) (0.365)8 (iv) A3E5 (v) CDA4 (vi) (11101.001)2 (vii) B2D4 2) Perform the operation of subtractions with the following binary numbers using 2’ complement (i) 10010 - 10011 (ii) 100 -110000 (iii) 11010 -10000 3) Define: Digital System Convert following Hexadecimal Number to Decimal : B28, FFF, F28 Convert following Octal Number to Hexadecimal and Binary: 414, 574, 725.25 4)Convert the following Numbers as directed: (1) (52)10 = ( )2 (2) (101001011)2 = ( )10 (3) (11101110) 2 = ( )8 (4) (68)10 = ( )16 5)Convert decimal 225.225 to binary ,octal and hexadecimal. 6) Represent the decimal number 8620 in BCD , Excess-3 , and Gray code 7) Convert the Decimal Number 250.5 to base 3, base 4, base 7 & base 16. 8) Perform the subtraction with the following decimal numbers using 1’s compliment and 2’s compliments. (a) 11010-1101 , (b) 10010-10011

UNIT- II

1) Obtain the simplified expressions in sum of products for the following Boolean functions: (i)F(A,B,C,D,E) =Σ(0,1,4,5,16,17,21,25,29) (ii) A’B’CE’+AB’C’D’+B’D’E’+B’CD’

2) Demonstrate by means of truth tables the validity of the following Theorems of Boolean algebra (i) De Morgan’s theorems for three variables

(ii) The Distributive law of + over-


Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad 3) Implement the following Boolean functions (i) F= A (B +CD) +BC′ with NOR gates (ii) F= (A + B′) (CD + E) with NAND gates

3) Explain SOP and POS expression using suitable examples Reduce the expression:

(1) A+B(AC+(B+C’)D) (2) (A+(BC)’)’ (AB’+ABC)

4) Simplify the Boolean function: (1)F(w,x,y,z) = Σ (0,1,2,4,5,6,8,9,12,13,14)

(2)F(w,x,y) = Σ (0,1,3,4,5,7)

5) Explain with figures how NAND gate and NOR gate can be used as Universal gate. 6) Simplify the Boolean function:

1) F = A’B’C’+B’CD’+A’BCD’+AB’C’

2) F =A’B’D’+A’CD+A’BC d=A’BC’D+ACD+AB’D’ Where “d ” indicates Don’t care conditions.

7) What is the principle of Duality Theorem? 8) Explain briefly: standard SOP and POS forms. 9) What are Minterms and Maxterms? 10) Define: Noise margin , Propagation delay 11) Explain NAND and NOR as an universal gates 12) Give classification of Logic Families and compare CMOS and TTL families

13)Draw the logic symbol and construct the truth table for each of the following gates. [1] Two input NAND gate [2] Three input OR gate

[3] Three input EX-NOR gate [4] NOT gate

14) Explain briefly : SOP & POS , minterm & maxterm, canonical form,propagation delay, fan out 15) Given Boolean function F= x y + x′ y′ + y′ z 1. Implement it with only OR & NOT gates 2. Implement it with only AND & NOT gates 16) Express following Function in Product of Maxterms F(x,y,z)= ( xy + z ) ( y + xz ) 17) Simplify the following Boolean functions to a minimum numbers of literals. (a) xyz+x’y+xyz’ and (b)(A+B)’(A’+B’)’


Approved by AICTE, New Delhi; Affiliated to Gujarat Technological University, Ahmadabad 18) Simplify the following Boolean function using K-map F( w,x,y,z) = Σ( 1 , 3 , 7 , 11 , 15 )

with don’t care conditions d( w,x,y,z ) = Σ( 0, 2 ,5 ) 19) Simplify the following Boolean function by using Tabulation method.

F = Σ ( 0,1,2,8,10,11,14,15 ) 20) Simplify Boolean function F ( w,x,y,z ) = Σ ( 0,1,2,4,5,6,8,9,12,13,14 )using

K-map and Implement it using (i) NAND gates only (ii) NOR gates only

21) Determine the Prime Implicants of following Boolean Function using Tabulation Method. F(A,B,C,D,E,F,G)=Σ(20,28,38,39,52,60,102,103,127) 22) btain the simplified expression in sum of product for the following Boolean functions. (a) F= Σ(0,1,4,5,10,11,12,14) and(b) F=Σ(11,12,13,14,15). 23) Implement the functions F=Σ(1,3,7,11,15) with don’t care conditions d=Σ(0,2,5) Discuss the effect of don’t care conditions.

UNIT- III

1) Design a combinational circuit whose input is four bit binary number and output is the 2’s complement of the input binary number.

2) Design a combinational circuit that accepts a three bit binary number and generates an output binary number equal to the square of the input number.

3) Discuss 4-bit magnitude comparator in detail 4) With necessary sketch explain full adder in detail.

5) Design a 4 bit binary to BCD code converter 6) Implement Boolean expression for Ex-OR gate using NAND gates only 7) Convert decimal 8620 into BCD , excess-3 code and Gray code. 8) Design a full-adder with two half-adders and an OR gate . 9) Design a combinational circuit whose input is a four bit number and whose Output is the 2’s complement of the input number. 10) Design BCD to Excess-3 code converter using minimum number of NAND gates. 11) Design the Combinational Circuits for Binary to Gray Code Conversion. 12) Explain Design Procedure for Combinational Circuit & Difference between Combinational Circuit & Sequential Circuit. UNIT- IV

1) Explain half and full adders in detail. 2) Design and implement BCD to excess 3 code converter.



3) Show how a full-adder can be converted to a full-subtractor with the addition of one inverter circuit.

4) Design a combinational circuit with four input lines that represent a decimal digit in BCD and four output lines that generate the 9’s complement of the input digit.

UNIT- V

1) Draw the general model of sequential circuits and explain. 2) Compare synchronous and asynchronous sequential circuits. 3) Explain the analysis procedure for a state machine. 4) Write a note on the excitation tables of flip flops. 1) Discuss D- type edge triggered flip flop in detail. 2) With neat sketch explain the operation of clocked RS flip flop. 3) Draw and explain the working of following flip flops (a) Clocked RS (b) JK 4) Convert SR flip flop into JK flip flop 5) With logic diagram and truth table explain the working of JK flip flop. Also obtain its

characteristics equation. How JK flip flop is the refinement of RS flip flop? 6) Draw logic diagram, graphical symbol, and characteristic table for D flip flop. (3 marks) 7) Explain working of master slave JK flip flop with necessary logic diagram, state equation

and state diagram. 8) Design sequential circuit with JK flip flop to satisfy the following state equation.

A(t+1)=A’B’CD + A’B’C + ACD + AC’D’ B(t+1)= A’C + CD’ + A’BC’ C(t+1)= B

9) Explain the procedure followed to analyze a clocked sequential circuit with suitable example.

UNIT- VI 1) Role of memory in computer system. 2) Explain RAM, ROM, EROPM, PROM EEPROM in detail. 3) Explain basic types and terminology of memory system.

UNIT- VII

1) Explain in detail digital to analog conversion analogy.

2) Explain in detail analog digital to conversion analogy.

3) Explain type of D/A conversion procedures.

4) Application of D/A and A/D technology.

1

Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER–IV(New) EXAMINATION – SUMMER 2016

Subject Code:2140910 Date:30/05/2016 Subject Name:Digital Electronics Time:10:30 AM to 01:00 PM Total Marks: 70 Instructions:

1. Attempt all questions. 2. Make suitable assumptions wherever necessary. 3. Figures to the right indicate full marks.

Q.1 Short Questions 14

1 (365.24)8 = ( )10

(a) 542.5213 b) 245.5213 c) 245.3125 d) 542.3125

2 In design of ripple counter using J-K flip flop the inputs of all flip flop are

(a) J=1, K=1 b) J=0, K=0 c) J=0, K=1 d) J=1, K=0

3 (255)10 = ( )2

(a) 11110111 (b) 11001100 (c) 11101111 (d) 11111111

4 If A = B = 1 then A XOR B equals __________.

(a) 1 (b) 0 (c) 8 (d) 16

5 The compliment of previous state is known as ___________.

(a) Toggle (b) No-Change (c) Preset (d) Clear

6 Boolean identity X + X = ___________.

(a) 0 (b) 1 (c) X (d) X'

7 The output of a logic gate is ‘1’ when all its inputs are at logic 0 (Consider 2 – inputs

Gate). The gates are

(a) NAND and EX-OR gate (b) NOR and EX-NOR gate

(c) OR and EX-NOR gate (d) AND and EX-OR gate

8 The logic gate which detects equality of two bits is

(a) OR (b) EX-NOR (c) NOR (d) NAND

9 If a 3-input NOR gate has eight input possibilities, how many of those possibilities will

result in a HIGH output?

(a) 1 (b) 2 (c) 7 (d) 8

10 Which is the fastest Analog to Digital converter

(a) Flash type (b) Successive Approximation (c) Dual Slope Integrator (d) Counter type

11 In Binary Ladder DAC, how many resistors are used?

(a) 1 (R) (b) 2 (R - 2R) (c) 3 (R-2R-3R) (d) 4 (R-2R-3R-4R)

12 Erasable ROM

(a) ROM (b) PROM (c) EPROM (d) None of the above

13 Which logic family has less power consumption

(a) TTL (b) ECL (c) CMOS (d) None of the above

14 Race around condition occurs in J-K F/F when its inputs are

(a) J = 0, K = 0 (b) J = 0, K = 1 (c) J = 1, K= 0 (d) J = 1, K = 1

Q.2 (a) Perform the following subtraction by using 2’s, 9’s and 10’s compliments.

26 – 34

03

(b) Perform the following operations.

(1) 101.11 x 111.01 (2) (1110110) ÷ (101)

04

(c) Explain Hamming codes. A seven bit Hamming code is received as 1110101. What is

the correct code for even parity?

07

OR

(c) Write a short note on Gray code. 07

Q.3 (a) Define the following general characteristics of logic families. 03

2

(i) Propagation delay time (ii) Fan-in (iii) Fan - out

(b) Reduce the expression:

a) A + B (AC + (B+C’) D)

b) (A + (BC)’ )’(AB’ + ABC)

04

(c) Explain two input TTL NAND gate. 07

OR

Q.3 (a) Simplify the following Boolean function using K-map

F (w, x, y, z) = ∑ m(1, 3, 7, 11, 15) with don’t care, d (w, x, y, z) = ∑m(0, 2, 5 ) 03

(b) Design NOR gate by using CMOS logic family. 04

(c) Simplify the following Boolean function using tabulation method

F (w, x, y, z) = ∑ (0, 1, 2, 8, 10, 11, 14, 15)

07

Q.4 (a) Implement the following Boolean function by using 8:1 MUX

F(A,B,C,D) = ∑m(0,1,3,4,8,9,15).

03

(b) Design a full adder circuit using decoder and multiplexer (4:1 MUX). 04

(c) Discuss 4 – bit magnitude comparator in detail. 07 OR

Q.4 (a) Discuss Left Mode serial in serial out shift register. 03

(b) Explain working of master-slave JK flip-flop with necessary logic diagram. 04

(c) Design 4 – bit synchronous up - counter (Use T flip-flop). 07

Q.5 (a) Compare various DAC techniques. 03

(b) Write a short note on different types of ROM. 04

(c) How many types of RAM? Describe the internal organization of RAM. 07

OR

Q.5 (a) State the applications of A to D converters. 03

(b) Explain R-2R ladder DAC network. 04

(c) Write down various ADC networks and explain any one in brief. Which is best ADC? 07

*************

1


GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER–IV(New) EXAMINATION – SUMMER 2016

Subject Code:2140910 Date:30/05/2016 Subject Name:Digital Electronics Time:10:30 AM to 01:00 PM Total Marks: 70 Instructions:


Q.1 Short Questions 14

1 (365.24)8 = ( )10

(a) 542.5213 b) 245.5213 c) 245.3125 d) 542.3125

2 In design of ripple counter using J-K flip flop the inputs of all flip flop are

(a) J=1, K=1 b) J=0, K=0 c) J=0, K=1 d) J=1, K=0

3 (255)10 = ( )2

(a) 11110111 (b) 11001100 (c) 11101111 (d) 11111111

4 If A = B = 1 then A XOR B equals __________.

(a) 1 (b) 0 (c) 8 (d) 16

5 The compliment of previous state is known as ___________.

(a) Toggle (b) No-Change (c) Preset (d) Clear

6 Boolean identity X + X = ___________.

(a) 0 (b) 1 (c) X (d) X'

7 The output of a logic gate is ‘1’ when all its inputs are at logic 0 (Consider 2 – inputs

Gate). The gates are

(a) NAND and EX-OR gate (b) NOR and EX-NOR gate

(c) OR and EX-NOR gate (d) AND and EX-OR gate

8 The logic gate which detects equality of two bits is

(a) OR (b) EX-NOR (c) NOR (d) NAND

9 If a 3-input NOR gate has eight input possibilities, how many of those possibilities will

result in a HIGH output?

(a) 1 (b) 2 (c) 7 (d) 8

10 Which is the fastest Analog to Digital converter

(a) Flash type (b) Successive Approximation (c) Dual Slope Integrator (d) Counter type

11 In Binary Ladder DAC, how many resistors are used?

(a) 1 (R) (b) 2 (R - 2R) (c) 3 (R-2R-3R) (d) 4 (R-2R-3R-4R)

12 Erasable ROM

(a) ROM (b) PROM (c) EPROM (d) None of the above

13 Which logic family has less power consumption

(a) TTL (b) ECL (c) CMOS (d) None of the above

14 Race around condition occurs in J-K F/F when its inputs are

(a) J = 0, K = 0 (b) J = 0, K = 1 (c) J = 1, K= 0 (d) J = 1, K = 1

Q.2 (a) Perform the following subtraction by using 2’s, 9’s and 10’s compliments.

26 – 34

03

(b) Perform the following operations.

(1) 101.11 x 111.01 (2) (1110110) ÷ (101)

04

(c) Explain Hamming codes. A seven bit Hamming code is received as 1110101. What is

the correct code for even parity?

07

OR

(c) Write a short note on Gray code. 07

Q.3 (a) Define the following general characteristics of logic families. 03

2

(i) Propagation delay time (ii) Fan-in (iii) Fan - out

(b) Reduce the expression:

a) A + B (AC + (B+C’) D)

b) (A + (BC)’ )’(AB’ + ABC)

04

(c) Explain two input TTL NAND gate. 07

OR

Q.3 (a) Simplify the following Boolean function using K-map

F (w, x, y, z) = ∑ m(1, 3, 7, 11, 15) with don’t care, d (w, x, y, z) = ∑m(0, 2, 5 ) 03

(b) Design NOR gate by using CMOS logic family. 04

(c) Simplify the following Boolean function using tabulation method

F (w, x, y, z) = ∑ (0, 1, 2, 8, 10, 11, 14, 15)

07

Q.4 (a) Implement the following Boolean function by using 8:1 MUX

F(A,B,C,D) = ∑m(0,1,3,4,8,9,15).

03

(b) Design a full adder circuit using decoder and multiplexer (4:1 MUX). 04

(c) Discuss 4 – bit magnitude comparator in detail. 07 OR

Q.4 (a) Discuss Left Mode serial in serial out shift register. 03

(b) Explain working of master-slave JK flip-flop with necessary logic diagram. 04

(c) Design 4 – bit synchronous up - counter (Use T flip-flop). 07

Q.5 (a) Compare various DAC techniques. 03

(b) Write a short note on different types of ROM. 04

(c) How many types of RAM? Describe the internal organization of RAM. 07

OR

Q.5 (a) State the applications of A to D converters. 03

(b) Explain R-2R ladder DAC network. 04

(c) Write down various ADC networks and explain any one in brief. Which is best ADC? 07

*************

1


GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER–IV (New) EXAMINATION – WINTER 2015

Subject Code:2140910 Date:22/12/2015

Subject Name: Digital Electronics

Time: 2:30pm to 5:00pm Total Marks: 70 Instructions:

1. Attempt all questions.

2. Make suitable assumptions wherever necessary.

3. Figures to the right indicate full marks.

Q.1 (a) Give classification of binary codes with some example and short explanation. 07

(b) Define universal gate. Prove that NAND and NOR gates are universal gates. 07

Q.2 (a) Convert:

(i) (314.24)8 to (________)10 (ii) (250.58)10 to (_________)8

07

(b) Explain in brief about error detection and correction codes. 07

OR

(b) Simplify Y=A’BCD’ + BCD’ + BC’D’ + BC’D and implement using NAND

gates only.

07

Q.3 (a) Explain CMOS NOR gate. 07

(b) Write short note on K-map. 07

OR

Q.3 (a) Explain two input TTL NAND gate. 07

(b) Express A’B + A’C as sum of minterms and also plot K-map. 07

Q.4 (a) Write short note on half adder and full adder. 07

(b) What is positive and negative edge triggering? Explain SR flip flop with

negative edge triggering.

07

OR

Q.4 (a) Explain multiplexer. 07

(b) Differentiate between excitation table and truth table. Write excitation table for

J-K flip flop.

07

Q.5 (a) Write a note on EEPROM. 07

(b) Explain working of ring counter. 07

OR

Q.5 (a) Explain binary weighted resistor digital to analog converter. 07

(b) Classify memory. Differentiate between RAM and ROM. 07

*************

1


GUJARAT TECHNOLOGICAL UNIVERSITY BE - SEMESTER– IV(NEW) EXAMINATION – SUMMER 2015

Subject Code: 2140910 Date: 28/05/2015 Subject Name: DIGITAL ELECTRONICS Time: 10:30am-1.00pm Total Marks: 70 Instructions:


Q.1 (a) Explain the working of Master-Slave J-K flip-flop. 07

(b) Explain why NAND and NOR are known as universal gates and construct AND, OR and NOT using the universal gates.

07

Q.2 (a) State and explain De Morgan’s theorems with truth tables. 07 (b) Explain how four bit combined binary adder and subtractor circuit can be

constructed using full adders? 07

OR (b) Explain TTL and CMOS logic. 07 Q.3 (a) Do as directed :-

I. Find the XS-3 code of following decimal numbers (i) 26 (ii) 42 (iii) 63 II. (4CD)16 = ( )10 = ( )2 III. Solve the following using 2’s complement

(i) (-4)-(-8) (ii) (3)-(6)

07

(b) Do as directed:- I. Add the following decimal numbers using 8421 BCD equivalent codes 679.6 + 536.8 II. Convert the following Binary to Gray Code (i)1001 (ii)1010 (iii) 1011 III. Multiply the binary numbers (1011.01) X (10.1)

07

OR Q.3 (a) Define the following general characteristics of logic families.

(i) Propagation delay time (ii) Noise margin (iii) Fan-in (iv) Hold time (v) Clear (vi) Fan-out (vii) Power dissipation

07

(b) Describe multiplexer and de-multiplexer with circuit and application of each. 07 Q.4 (a) Apply De Morgan’s theorem to solve the following

07

(b) What are SOP and POS forms of boolean expressions? Minimize the following expression using K-map Y= Σm(4,5,7,12,14,15) + d( 3,8,10)

07

OR Q.4 (a) Describe the working of look-ahead-carry adder. 07

(b) Explain in brief the working of decoders. 07 Q.5 (a) Classify the various modes of operation of shift registers. Explain the serial in

parallel out operation of shift register. 07

(b) Discuss the applications of shift registers. 07

2

OR Q.5 (a) What is the basic difference between synchronous and asynchronous counter?

Describe synchronous 3-bit up counter. 07

(b) Explain the working of Analog to Digital converter with necessary diagrams. 07

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laxmi institute of technology , sarigam · half and full adder – half and full subtracter –...

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