A Full Adder CircuitThe main difference between theFull Adderand the previousHalf Adderis that a full adder has three inputs. The same two single bit data inputsAandBas before plus an additionalCarry-in(C-in) input to receive the carry from a previous stage as shown below.Full Adder Block Diagram

Then thefull adderis a logical circuit that performs an addition operation on three binary digits and just like the half adder, it also generates a carry out to the next addition column. Then aCarry-inis a possible carry from a less significant digit, while aCarry-outrepresents a carry to a more significant digit.

Full Adder Truth Table with CarrySymbolTruth Table

C-inBASumC-out

00000

00110

01010

01101

10010

10101

11001

11111

Then the Boolean expression for a full adder is as follows.There are a number of 4-bit full-adder ICs available such as the 74LS283 and CD4008. which will add two 4-bit binary number and provide an additional input carry bit, as well as an output carry bit, so you can cascade them together to produce 8-bit, 12-bit, 16-bit, adders but the carry propagation delay can be a major issue in large n-bit ripple adders.74LS83 Logic Symbol

Half Adder and Basic (1-bit) Full AdderIn electronics, an Adder is a device that performs the addition of two numbers.A Half Adder is a Logic Circuit that performs 1-bit binary addition. Given that P and Q are two 1-bit binary numbers, S is the 1-bit Sum of P and Q, and CO is the CARRY OUT bit. Mathematically, as shown in Figure 3, S and CO form a 2-bit Arithmetic Sum of P and Q, with CO being the Most Significant Bit (MSB). Figure 4 shows all possible cases for 1-bit binary addition and Table 3 is the Half Adder Truth-Table.1P

+)1Q

10

COS

Figure 3: Addition of two 1-bit binary numbers0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0 with a Carry of 1

Figure 4: All possible cases for 1-bit binary additionInputsOutputs

PQCOS

0000

0101

1001

1110

Table 3: Half Adder Truth-TableAccording to the Truth-Table, if we consider the logic relation between the Inputs and Outputs of a Half Adder, S is the XOR operation of the Inputs and CO is the AND operation of the Inputs. This means that the Half Adder circuit can be implemented with just two Logic Gates: an XOR Gate and an AND Gate, Figure 5.

Figure 3: Half AdderThe Half Adder can only perform the addition of two 1-bit binary numbers, because it does not accept the Input of a carry bit from the addition of two previous bits.A Basic (1-bit) Full Adder is a Logic Circuit that performs the addition of two 1-bit binary numbers with a carry bit, CARRY IN (CI). It consists of one OR Gate and two Half Adders, Figure 6. The circuit generates two Outputs: S and CO. Multiple Basic Full Adders can be cascaded to form a Multi-bit Full Adder.

Figure 6: Basic (1-bit) Full Adder

Full Adder (4-bit)Multiple Basic (1-bit) Full Adders can be cascaded to form a Multi-bit Full Adder. In Figure 7, four Basic Full Adders are chained together to form a 4-bit Ripple Adder, with the Carry Out (CO) of a Basic Full Adder connected to the Carry In (CI) of the next most significant Basic Full Adder.

Figure 7: A 4-bit Ripple Adder constructed with four Basic Full AddersAddition between two Multi-bit Binary Numbers P and Q is done by adding the bits successively, starting from the Least Significant Bit (LSB), i.e. P0 + Q0. Any Carry bit from previous bits is added to the sum of the next consecutive bits, Figure 8.

Figure 8: Addition of two 4-bit Binary Numbers illustrating Carry operationFor a 5-bit Binary Number P, the weights of its significant bits are:P0 = 20= 1

P1 = 21= 2

P2 = 22= 4

P3 = 23= 8

P4 = 24= 16

The formula for converting a 5-bit Binary Number P2 (P4 P3 P2 P1 P0) to its corresponding Decimal Number P10is:P10= P4 x 24+ P3 x 23+ P2 x 22+ P1 x 21+ P0 x 20The CO bit of a 4-bit Full Adder is equivalent to the 4th significant bit and its weight is 16 (24= 16).The largest decimal sum that can be obtained from a 4-bit Full Adder is 31 (24+1- 1 = 31).Half Adder and Full Adder CircuitsAugust 15, 2014ByEH moderators teamLeave a CommentAdder is a combinational logic circuit designed to add the binary numbers. General adder circuit produces. A typical adder produces a sum (S) and a carry (C) as the output. These adders are also used to add the other formats like BCD (Binary Coded Decimal), gray code, XS 3, etc. Adder circuits are not only used for addition but also used in digital applications like table index calculation, address decoding etc. Adders are basically two types: Half adder and Full adder. This article explains you in detail about adders.Half Adder:Half adder is simple example of combinational logic circuit with 2 logic gates. This digital circuit performs addition operation between two binary numbers. The half adder operation needs two inputs: augend and addend bits and provides two outputs sum(s) and carry(c).Half Adder Circuit:The below figure shows the schematic of half adder.

Schematic Representation of Half AdderHalf Adder Truth Table:Now let us see how to get the Boolean functions for sum and carry. The truth table for half adder is given below.

In order to get the simplified Boolean equations for sum and carry we use K- map. The below figure shows you how to get logic functions for sum and carry from truth table.

K-map simplification for Half adderAbove Image Resource Link:http://books.google.co.in/books?id=9AgDwtdDIIwC&printsec=frontcover&source=gbs_ge_summary_r&cad=0#v=onepage&q&f=falseIf A and B are binary inputs to the half adder then Boolean function to calculate sum S is X OR of A and B and logic function to calculate carry C is AND of A and B. The below figure shows the realization of half adder.

Half Adder Logic DiagramFrom the above logic diagram it is clear that half adder circuit requires one EX OR gate and one and gate. NAND and NOR gates are universal gates, using these gates we can design any digital application. Now let us see how to design Half adder using NAND and NOR gates. Five NAND gates or Five NOR are required to design Half adder circuit.Half Adder using NAND Gates:

Realization Half Adder using NAND GatesAlso get an idea aboutHow to Build OR, AND, NOT Gates using NAND GateHalf Adder using NOR Gates:Below figure shows logic diagram of half adder using NOR gates.

Realization of Half Adder using NOR GatesLimitations of Half Adder:In general addition operation we need to add two binary inputs along with the carry of previous bit addition. In order to perform general addition operation we need to add 3 inputs. Such type of addition operation is not possible with half adders and this is reason to call them as half adders. Hencehalf addersare not used in real time.Full Adder:Full adder is digital circuit used to calculate the arithmetic sum of three bits. Full adder is little difficult to implement than half adder. Full adder consists of three inputs and 2 outputs. The first 2 inputs are augend and addend and 3rdinput is the carry of previous digit operation. The first two inputs are denoted by A and B, carry of previous operation is denoted by Cin.Full Adder Circuit:Schematic representation of Full adder is shown below.

Schematic Representation of Full AdderFull Adder Truth Table:The truth table for full adder is shown below.

Now let us see how to get the Boolean functions for sum and carry from the truth table using K map.

K-map simplification for Full adderAbove Image Resource Link:http://books.google.co.in/books?id=9AgDwtdDIIwC&printsec=frontcover&source=gbs_ge_summary_r&cad=0#v=onepage&q&f=falseFrom the above Boolean functions it is clear that we require 3 two input AND gates and one three input OR gate to calculateCarryfor full adder and requires 4 three input and gates and one 4 input OR gatesumfor full adder.Full Adder Logic Diagram:The below figure shows the logic diagram of Full adder.

Full Adder Logic DiagramThese full adders are used in binary adders, counters, address decoders etc.Implementation of Full Adder usingHalf Adders:We can also implement a full adder with 2 Half adders. Now let us see how to design a Full adder with 2 half adders. We know that the logic functions for full adder are S = A B Cin + A BC in + ABCin Cout = AB + ACin + BCinWe can also simplify the sum function as S = A B Cin + A BC in + ABCin = Cin (A B + AB) + C in (A B + A B ) = Cin (A X-NOR B) + C in (A X-OR B) = Cin XOR (A XOR B)Cout is simplified as Cout = AB + Cin (A B + A B ) = AB + A B Cin + A B Cin = AB (Cin + 1) + A B Cin + A B Cin = ABCin + AB + A B Cin + A B Cin = AB + ACin (B + B ) + A BCin = AB + ACin + A BCin = AB (1 +Cin) + ACin + A BCin = ABCin + AB + ACin + A BCin = AB + ACin + Bcin (A + A ) = AB + ACin + BCin

Implementation of Full Adder with 2 Half AddersFull Adder using NAND Gates:We know that NAND gates are universal gates so that we can design any type digital circuit only with NAND gates. Here is the circuit to design Full adder with NAND gates.

Full Adder using NAND Gates

Half adderLast Updated onMarch 29, 2012byadmininDigital Electronicswith14 CommentsHalf adder circuit.To understand what is a half adder you need to know what is an adder first. Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Typically adders are realized for adding binary numbers but they can be also realized for adding other formats like BCD (binary coded decimal, XS-3 etc. Besides addition, adder circuits can be used for a lot of other applications in digital electronics like address decoding, table index calculation etc. Adder circuits are of two types: Half adder ad Full adder.Full adders have been already explained in a previous article and in this topic I am giving stress to half adders.Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily constructed using one X-OR gate and one AND gate. Half adder is the simplest of all adder circuit, but it has a major disadvantage. The half adder can add only two input bits (A and B) and has nothing to do with the carry if there is any in the input. So if the input to a half adder have a carry, then it will be neglected it and adds only the A and B bits. That means the binary addition process is not complete and thats why it is called a half adder. The truth table, schematic representation and XOR//AND realization of a half adder are shown in the figure below.

Truth table, schematic and realization of half adderNAND gates or NOR gates can be used for realizing the half adder in universal logic and the relevant circuit diagrams are shown in the figure below.

Half adder using NAND & NOR logic