ncp1562a - high performance active clamp/reset pwm controller

Semiconductor Components Industries, LLC, 2010

November, 2010 -- Rev. 51 Publication Order Number:

NCP1562A/D

NCP1562A, NCP1562B

High Performance ActiveClamp/Reset PWM ControllerThe NCP1562x is a family of voltage mode controllers designed

for dc--dc converters requiring high--efficiency and low parts count.These controllers incorporate two in phase outputs with an overlapdelay to prevent simultaneous conduction and facilitates softswitching. The main output is designed for driving a forwardconverter primary MOSFET. The secondary output is designed fordriving an active clamp circuit MOSFET, a synchronous rectifier onthe secondary side, or an asymmetric half bridge circuit.The NCP1562 family reduces component count and system size by

incorporating high accuracy on critical specifications such asmaximum duty cycle limit, undervoltage detector and overcurrentthreshold. Two distinctive features of the NCP1562 are soft--stop anda cycle skip current limit with a time threshold. Soft--stop circuitrypowers down the converter in a controlled manner if a severe fault isdetected. The cycle skip detector enables a soft--stop sequence if acontinuous overcurrent condition is present.Additional features found in the NCP1562 include line feed--

forward, frequency synchronization up to 1.0 MHz, cycle--by--cyclecurrent limit with leading edge blanking (LEB), independent underand overvoltage detectors, adjustable output overlap delay,programmable maximum duty cycle, internal startup circuit andsoft--start.

Features

Dual Control Outputs with Adjustable Overlap Delay >2.0 A Output Drive Capability

Soft--Stop Powers Down Converter in a Controlled Manner

Cycle--by--Cycle Current Limit

Cycle Skip Initiated if Continuous Current Limit Condition Exists Voltage Mode Operation with Input Voltage Feedforward

Fixed Frequency Operation up to 1.0 MHz

Bidirectional Frequency Synchronization Independent Line Undervoltage and Overvoltage Detectors

Accurate Programmable Maximum Duty Cycle Limit

Programmable Maximum Volt--Second Product Programmable Soft--Start

Internal 100 V Startup Circuit

Precision 5.0 V Reference

These are Pb--Free Devices

Typical Applications Telecommunications Power Converters

Low Output Voltage Converters using Control Driven SynchronousRectifier

Industrial Power Converters

42 V Automotive System

ATX Power Supplies

TSSOP--16DT SUFFIXCASE 948F

x = Current Limit (A, B)A = Assembly LocationWL, L = Wafer LotY = YearWW, W = Work WeekG or G = Pb--Free Package

MARKINGDIAGRAMS

NCP562xALYWGG

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SO--16D SUFFIXCASE 751B

Seedetailed ordering and shipping information in the packagedimensions section on page 24 of this data sheet.

ORDERING INFORMATION

NCP1562xGAWLYWW

1

16

(Note: Microdot may be in either location)

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Figure 1. Detailed Block Diagram

Vin

1

16

VAUX

Iinhibit

IstartDisable

+--

VAUX(on)+--

CentralLogic

Disable_VREF

5.0 V Reference

VAUX

P.O.R.

Bias VREF

8

SDominantResetLatchR

Q

CAUX

VAUX(on)/VAUX(off1)/VAUX(off2)

+

--

+

--

One ShotPulse

VUV Soft--StopComplete

ThermalShutdown

STOPUVOVDetector

UVOV

Vin

R2

R1

2 V

3 V

Vref

CT

RT 6

RTCT

500 mA

SYNC

DMAX

Clock

Oscillator

7

SYNC

+

--

CSKIPComparator

+

--VCSKIP

CSKIPControlLogic

VREF

ICSKIP(C)

ICSKIP(D)

12

CSKIPCCSKIP

Clock

+--

NotSaturated

+

--3.6 V

SaturationComparator

SDominantResetLatchR

Q

Q

Clock

FF Reset

DelayLogic

Enable_Output

OUT115

VAUX

14PGND

OUT213

VAUX

11

270 kΩ

20 kΩ

VREF

--+

PWMComparator

-- +

Soft--StartComparator

-- +

FFComparator +

--0.2 V

3 V

+

--

Vin

RFF

CFF

VEA

FF

3

5

GND

FF Reset

IlimitComparator

+--+

--0.2 V = A ver.(0.5 V = B ver.) OUT

Fixed 80 ns LEBClock

Enable

NotSaturated

Soft--StartSoft--Stop

Control Logic STOPVX Soft--Start

Complete

Soft--StopComplete

VREF

ISS(C)

ISS(D)

10

SSCSS

4

CS

Enable_Output

1 V

2

tDRD

9

VX

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PIN FUNCTION DESCRIPTION

Pin Symbol Description

1 Vin Connect the input line voltage directly to this pin to enable the internal startup regulator. A constantcurrent source supplies current from this pin to the capacitor connected to the VAUX pin, eliminating theneed for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 100 V.

2 UVOV Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is usedfor both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).The minimum and maximum input supply voltage thresholds are adjusted independently. A UVcondition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltageexceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain3% accuracyallowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis.

3 FF An external R--C divider from the input line generates the Feedforward Ramp. This ramp is used by thePWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldowntransistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectivelygrounded until the next cycle begins.

4 CS Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0.5 V in the NCP1562B) the converteroperates in cycle--by--cycle current limit. Once a current limit pulse is detected, the cycle skip timer isenabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation.The leading edge blanking is disabled during soft--start and output overload conditions to improve theresponse to faults.

5 GND Control circuit ground. All control and timing components that connect to GND should have the shortestloop possible to this pin to improve noise immunity.

6 RTCT An external RT--CT divider from VREF sets the operating frequency and maximum duty cycle of OUT1.The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V isgenerated by sequentially charging and discharging CT. The peak and valley of the Ramp areaccurately controlled to provide precise control of the duty cycle and frequency. The outputs aredisabled during the CT discharge time.

7 SYNC Proprietary bidirectional frequency synchronization architecture allows two NCP1562 devices tosynchronize together. The lower frequency device becomes the slave. It can also synchronize to anexternal signal.

8 VREF Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the referencewith a capacitor. The recommended capacitance range is between 0.047 mF and 1.0 mF.

9 VEA The error signal from an external error amplifier is fed to this input and compared to the FeedforwardRamp. A series diode and resistor offset the voltage on this pin before it is applied to the PWMComparator inverting input. An internal pullup resistor allows direct connection to an optocoupler.

10 SS A 10 mA current source charges the external capacitor connected to this pin. Duty cycle is limitedduring startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady stateconditions, the SS voltage is approximately 3.8 V. Once a UV, OV, overtemperature or cycle skip faultis detected, the SS capacitor is discharged in a controlled manner with a 100 mA current source. Theduty cycle is then slowly reduced until reaching 0%.

11 tD An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2transitions.

12 CSKIP The converter is disabled if a continuous overcurrent condition exists. The time to determine the faultand the time the converter is disabled are programmed by the capacitor (CCSKIP) connected to this pin.The cycle skip timer is enabled after a current limit fault is detected. Once enabled, CCSKIP is chargedwith a 100 mA source. If the overcurrent fault is removed before entering the soft--stop mode, thecapacitor is discharged with a 10 mA source. Once CCSKIP reaches 3.0 V, the converter enters asoft--stop mode and CCSKIP is discharged with a 10 mA source. The converter is re--enabled onceCCSKIP reaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, CCSKIPdischarges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation.

13 OUT2 Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, asynchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delayagainst OUT1. OUT2 has source and sink resistances of 12 Ω (typ.). OUT2 is designed to handle upto 1.0 A.

14 PGND Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.

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PIN FUNCTION DESCRIPTION (continued)

Pin Symbol Description

15 OUT1 Main output of the PWM Controller. OUT1 has a source resistance of 4.0 Ω (typ.) and a sink resistanceof 2.5 Ω (typ.). OUT1 is designed to handle up to 2.5 A. OUT1 trails OUT2 during a low to hightransition and leads OUT2 during a high to low transition.

16 VAUX Positive input supply. This pin connects to an external capacitor for energy storage. An internal currentsource supplies current from Vin to this pin. Once the voltage on VAUX reaches approximately 10.3 V,the current source turns OFF and the outputs are enabled. It turns ON again once VAUX falls to 8.0 V. Ifthe bias current consumption exceeds the startup current, VAUX will continue to discharge. Once VAUXreaches 7.0 V, the outputs are disabled allowing VAUX to charge. During normal operation, power issupplied to the IC via this pin by means of an auxiliary winding. The startup circuit is disabled once thevoltage on the VAUX pin exceeds 10.3 V. If the VAUX voltage drops below 1.2 V (typ), the startupcurrent is reduced to 200 mA.

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MAXIMUM RATINGS (Notes 1 and 2)

Rating Symbol Value Unit

Line Voltage Vin 100 V

Auxiliary Supply, OUT1, OUT2 VAUX, Voutx 20 V

All Other Inputs/Outputs Voltage VIO 10 V

All Other Inputs/Outputs Current IIO 5.0 mA

5.0 V Reference Output Current IREF 10 mA

5.0 V Reference Output Voltage VREF --0.3 to 6.0 V

OUT1 Peak Output Current (D = 2%) Iout1 2.5 A

OUT2 Peak Output Current (D = 2%) Iout2 1.0 A

Operating Junction Temperature TJ –40 to +125 _C

Storage Temperature Range Tstg –55 to +150 _C

Power Dissipation (TA = 25_C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad)DT Suffix, Plastic Package Case 948F (TSSOP--16)D Suffix, Plastic Package Case 751B (SO--16)

PD0.750.95

W

Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad)DT Suffix, Plastic Package Case 948F (TSSOP--16)

0.36 Sq In1.0 Sq In

D Suffix, Plastic Package Case 751B (SO--16)0.36 Sq In1.0 Sq In

RθJA

155133

120105

_C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice reliability.1. This device series contains ESD protection and exceeds the following tests:

Pins 2--16: Human Body Model 2000 V per MIL–STD–883, Method 3015.Machine Model Method 160 V.

Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 100 V.2. This device contains Latchup protection and exceeds100 mA per JEDEC Standard JESD78.

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ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V, VCS = 0 V, VSS = open,RT = 13.3 kΩ, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF, RD = 25 kΩ, RSYNC = 5.0 kΩ,CREF = 0.1 mF, RFF = 29.4 kΩ, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is – 40C to 125C, unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

STARTUP CONTROL AND VAUX REGULATOR

VAUX Regulation (VUVOV = 0 V)Inhibit Threshold VoltageStartup Threshold/VAUX Regulation Peak (VAUX Increasing)Operating VAUX Valley VoltageMinimum Operating VAUX Valley Voltage after Turn--On(VUVOV = 2.3 V, VEA = 0 V)

VinhibitVAUX(on)VAUX(off1)VAUX(off2)

–9.657.426.50

1.1510.38.07.0

1.510.978.487.42

V

Minimum Startup Voltage (Pin 1)IAUX = 1.0 mA, VAUX = VAUX(on) – 0.2 V

Vstart(min)– – 23.2

V

Inhibit Bias CurrentVAUX = 0 V Iinhibit 70 170 300

mA

Startup Circuit Output CurrentVAUX = Vinhibit + 0.2 VVAUX = VAUX(on) – 0.2 V

Istart1Istart2

7.164.03

9.36.1

11.38.1

mA

Startup Circuit Off--State Leakage Current (Vin = 200 V, VUVOV = 0 V)TJ = 25_CTJ = –40_C to 125_C

Istart(off)––

25–

50100

mA

Startup Circuit Breakdown Voltage (Note 3)Istart(off) = 50 mA, TJ = 125_C

VBR(DS)100 – –

V

Auxiliary Supply Current after VAUX Turn--OnOutputs DisabledVUVOV = 0 VVEA = 0 V

Outputs EnabledVEA = 4.0 V

IAUX1IAUX2

IAUX3

––

–

3.04.2

5.5

3.64.94

7.0

mA

LINE UNDER/OVERVOLTAGE DETECTOR

Undervoltage Threshold (Vin Increasing) VUV 1.979 2.05 2.116 V

Undervoltage Hysteresis VUV(H) 0.074 0.093 0.118 V

Undervoltage Ratio (VUV(H)/VUV) VUV(ratio) 3.65 4.50 5.62 %

Overvoltage Threshold (Vin Increasing) VOV 2.80 2.95 3.10 V

Overvoltage Hysteresis VOV(H) 0.075 0.093 0.127 V

Offset Current (VUVOV = 2.8 V) Ioffset(UVOV) 38 48 58 mA

Offset Current Turn ON Threshold (5%, Ioffset(UVOV) = 40 mA) Voffset(UVOV) 2.4 2.6 2.8 V

LINE FEEDFORWARD

Peak Voltage (Volt--Second Clamp) VFF(peak) 2.8 3.0 3.2 V

Discharge Current (VFF = 0.5 V, VSS = 0 V) IFF(D) 8.5 – – mA

Offset Voltage (VFF = 0 V, Ramp Down VSS) Voffset(FF) 0.118 0.185 0.268 V

Feedforward Offset Minus Soft--Stop Reset Voltage Δ(FF--SS) 7 70 183 mV

3. Guaranteed by design only.

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ELECTRICAL CHARACTERISTICS (continued) (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V,VCS = 0 V, VSS = open, RT = 13.3 kΩ, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF,RD = 25 kΩ, RSYNC = 5.0 kΩ, CREF = 0.1 mF, RFF = 29.4 kΩ, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is – 40C to125C, unless otherwise noted.)


CURRENT LIMIT AND THERMAL SHUTDOWN

Cycle–by–Cycle Threshold Voltage (Vout = 10 V)NCP1562ANCP1562B

VILIM191472

203495

217512

mV

Propagation Delay to Output(VCS = VILIM to 1.0 V, LEB Disabled, Vout = 10 V)TJ = 25_CTJ = –40_C to 125_C

tILIM

––

78–

90110

ns

Thermal Shutdown Threshold (Junction Temperature Increasing, Note 4) TSHDN – 160 – _C

Thermal Shutdown Hysteresis (Temperature Decreasing, Note 4) TH – 25 – _C

LEADING EDGE BLANKING

Offset Voltage VLEB(offset) – 10 – mV

Blanking Time tLEB 50 80 110 ns

VEA Threshold the Disables LEB (Measured together with tLEB) VLEB(dis) 4.1 – – V

CYCLE SKIP CURRENT LIMIT MODE

Charge Current (VCSKIP = 1.25 V) ICSKIP(C) 70 90 111 mA

Discharge Current (VCSKIP = 1.25 V) ICSKIP(D) 6.5 8.6 11 mA

Number of Pulses to Exit Cycle Skip Mode PulseCSKIP – 3 – --

Upper Threshold Voltage (Ramp up VCSKIP, VCS = 1.0 V) VCSKIP(peak) 2.83 3.03 3.24 V

Lower Threshold Voltage (Ramp down VCSKIP) VCSKIP(valley) 0.39 0.465 0.52 V

Threshold Voltage Hysteresis VCSKIP(H) – 2.5 – V

5.0 V REFERENCE

Output Voltage (IREF = 0 mA) VREF 4.9 5.0 5.1 V

Load Regulation (IREF = 0 to 5.0 mA) VREF(Load) – 16 50 mV

Line Regulation (VAUX = 7.5 to 20 V, IREF = 0 mA) VREF(line) – 10 50 mV

Discharge Current (VUVOV = 0 V, VREF = 2.5 V) IREF(D) 3.8 – – mA

OSCILLATOR

FrequencyTJ = 25_CTJ = --40_C to 125_C

fOSC222211.2

246–

272.2277.2

kHz

Peak Voltage VRTCT(peak) -- 2.95 -- V

Valley Voltage VRTCT(valley) -- 2.1 -- V

Discharge Current (VRTCT = 2.3 V) IRTCT -- 490 -- mA

Maximum Operating Frequency (Note 4) fMAX 1.0 – – MHz

Duty Cycle (RD = 25 kΩ) D 58.5 62.0 64.7 %

Adjustable Maximum Duty Cycle (Note 4) DMAX 85 -- -- %


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ELECTRICAL CHARACTERISTICS (continued) (Vin = 48 V, VAUX = 12 V, VUVOV = 2.3 V, VEA = open, VCSKIP = 0 V,VCS = 0 V, VSS = open, RT = 13.3 kΩ, CAUX = 10 mF, CT = 470 pF, Cout1 = Cout2 = 100 pF, CUVOV = 0.01 mF, CCSKIP = 6800 pF,RD = 25 kΩ, RSYNC = 5.0 kΩ, CREF = 0.1 mF, RFF = 29.4 kΩ, CFF = 470 pF. For typical values TJ = 25C, for min/max values, TJ is – 40C to125C, unless otherwise noted.)


SYNCHRONIZATION

Output Pulse Width tO(SYNC) 70 110 -- ns

Output Voltage High (RSYNC =∞) VH(SYNC) – 4.3 – V

Sync Threshold Voltage (Note 5) VSYNC 3.5 – – V

Sync Input Pulse Width (VSYNC = 3.5 V) tSYNC -- – tO(SYNC)min ns

Maximum Sync Frequency (Note 5) fSYNC – – 1.0 MHz

Source Current (Note 5) ISYNC(D) – 1.0 – mA

SOFT--START/STOP

Charge Current (VSS = 1.6 V) ISS(C) 8.3 10.2 13.1 mA

Discharge Current (VUVOV = 0 V, VSS = 1.6 V) ISS(D) 72 95 115 mA

Soft--Stop Reset Voltage (VFF = 0 V) Vreset(SS) – 115 -- mV

OUTPUTS

Overlap Time Delay (Tested at 50% of Waveform)LeadingTrailing

tD(leading)tD(trailing)

3772

4590

----

ns

Output Voltage (IOUT = 0 mA, Note 5)Low StateHigh State

VOLVOH

–11.8

––

0.25–

V

Drive Resistance (FT ONLY)OUT1 Sink (VRTCT = 4.0 V, Vout1 = 1.0 V)TJ = 25_CTJ = –40_C to 125_C

OUT1 Source (VRTCT = 2.5 V, Vout1 = 11 V)TJ = 25_CTJ = –40_C to 125_C

OUT2 Sink (VRTCT = 4.0 V, Vout2 = 1.0 V)TJ = 25_CTJ = –40_C to 125_C

OUT2 Source (VRTCT = 2.5 V, Vout2 = 11 V)TJ = 25_CTJ = –40_C to 125_C

RSNK1

RSRC1

RSNK2

RSRC2

––

––

––

––

2.8–

4.7–

11.4–

11.6–

3.65.03

5.757.45

12.720.0

13.520.0

Ω

Rise Time (10% to 90%, Cout1 = 2200 pF, Cout2 = 220 pF)OUT1OUT2

tr1tr2

––

2619

––

ns

Fall Time (90% to 10%, Cout1 = 2200 pF, Cout2 = 220 pF)OUT1OUT2

tf1tf2

––

1010

––

ns

PWM COMPARATOR

Input Resistance RIN(VEA) 11 25 58 kΩ

Lower Input Threshold VEA(L) 0.48 0.83 1.04 V

Delay to Output (From VOH to 0.5 VOH) tPWM – 100 – ns


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Vinhibit,INHIBITTHRESHOLD

VOLTAGE(V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

01501251007550250--25--50

TJ, JUNCTION TEMPERATURE (C)

Figure 2. Startup Circuit Inhibit Voltage Thresholdvs. Junction Temperature

VAUX,A

UXILIARYSUPPLY

VOLTAGE(V) 11.0

6.01501251007550250--25--50


Figure 3. Auxiliary Supply Voltage Thresholdsvs. Junction Temperature

10.5

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

VAUX(on)

I start,S

TARTUPCURRENT(mA)

12

21501251007550250--25--50


Figure 4. Startup Current vs. Junction Temperature

11

10

9

8

7

6

5

4

3

VAUX = Vinhibit + 0.2 V

VAUX = VAUX(on) -- 0.2 V

Vin = 48 VI start,S

TARTUPCURRENT(mA)

4

10

9

8

7

6

5

2 4 6 8 10 12

VAUX, SUPPLY VOLTAGE (V)

Figure 5. Startup Current vs. Supply Voltage

Vin = 48 VTJ = 25C

I start(off),STA

RTUPCIRCUITLE

AKAGE

CURRENT(mA)

100

10

2001751501251007550250

Vin, INPUT VOLTAGE (V)

Figure 6. Startup Circuit Leakage Currentvs. Input Voltage

90

80

70

60

50

40

30

20

VAUX = 12 V

0

TJ = 25C

TJ = --40C

TJ = 125C

0

3

2

1

0

VAUX(off1)

VAUX(off2)

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UNDERVOLTAGE

OVERVOLTAGE

I AUX,A

UXILIARYSUPPLY

CURRENT(mA) 10

1

1501251007550250--25--50


Figure 7. Auxiliary Supply Currentvs. Junction Temperature

9

8

7

6

5

4

3

2

VUVOV = 2.3 V, Cout1 = Cout2 = 100 pF

VAUX = 12 V

0

VUVOV = 2.3 V, VEA = 0 V

VUVOV = 0 V

I AUX3,POWERSUPPLY

CURRENT(mA) 8.0

3.5

151413121110

VAUX, POWER SUPPLY VOLTAGE (V)

Figure 8. Supply Current vs. Supply Voltage

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.020

Vin = 48 VTJ = 25CfOSC≈ 230 kHzCout1 = Cout2 = 100 pF


VUV/OV,LINEUNDER/OVERVOLTAGETHRESHOLD

S(V)

3.2

2.2

--50

3.1

3.0

2.9

2.8

2.7

2.5

2.4

2.3

2.0

2.6

2.1

--25 0 25 50 75 100 125 150

Figure 9. Line Under/Overvoltage Thresholdsvs. Junction Temperature

VUV/OV(H),UNDER/OVERVOLTAGEHYSTERESIS

(mV)

150

501501251007550250--25--50


Figure 10. Line Under/Overvoltage Hysteresisvs. Junction Temperature

140

130

120

110

100

90

80

70

60

UNDERVOLTAGE

OVERVOLTAGE

I offset(UVOV),UVOVOFFSETCURRENT(mA)

75

251501251007550250--25--50


Figure 11. UVOV Offset Currentvs. Junction Temperature

70

65

60

55

50

45

40

35

30

VAUX = 12 VVUVOV = 2.8 V

I FF(D),DISCHARGECURRENT(mA)

50

01501251007550250--25--50


Figure 12. FF Discharge Currentvs. Junction Temperature

45

40

35

30

25

20

15

10

5

VCC = 12 VVSS = 0 VVFF = 0.5 V

16 1817 19

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NCP1562B

NCP1562A

VFF(peak),FFPEAKVOLTAGE(V)

3.5

2.51501251007550250--25--50


Figure 13. FF Offset and SS Reset Voltagesvs. Junction Temperature

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

VILIM,C

URRENTLIMITTHRESHOLD

VOLTAGE(mV)

550

1501251007550250--25--50


Figure 14. Feedforward Peak Voltagevs. Junction Temperature

500

450

400

350

300

250

200

150

Voffset(FF)/V

reset(SS),FFOFFSETAND

SSRESETVOLTAGES(mV)

250

01501251007550250--25--50


225

200

175

150

125

100

75

50

25

FF--Offset

SS Reset

Figure 15. Current Limit Threshold Voltagevs. Junction Temperature

t ILIM,C

URRENTLIMITPROPAGATIONDELAY(ns)

150

501501251007550250--25--50


Figure 16. Current Limit Propagation Delayvs. Junction Temperature

140

130

120

110

100

90

80

70

60

t LEB,LEBTIME(ns)

100

01501251007550250--25--50


Figure 17. Leading Edge Blanking Timevs. Junction Temperature

90

80

70

60

50

40

30

20

10

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I REF(D),VREFDISCHARGECURRENT(mA)

10

01501251007550250--25--50


Figure 18. Cycle Skip Charge Currentvs. Junction Temperature

9

8

7

6

5

4

3

2

1

VCC = 12 VVUVOV = 0 VVREF = 2.5 V

VCSKIP(peak),U

PPERTHRESHOLD

(V) 3.5

2.51501251007550250--25--50


3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

UPPER THRESHOLD

VCSKIP(valley),LOWERTHRESHOLD

(V)1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

LOWER THRESHOLD

VREF,REFERENCEVOLTAGE(V)

5.25

4.751501251007550250--25--50


Figure 19. Cycle Skip Discharge Currentvs. Junction Temperature

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

VAUX = 12 V

VREF = 0 mA

VREF = 5 mA

I CSKIP(C),CYCLE

SKIP

CHARGECURRENT(mA)

150

501501251007550250--25--50


140

130

120

110

100

90

80

70

60

VCSKIP = 1.25 V

Figure 20. Cycle Skip Voltage Thresholdsvs. Junction Temperature

f OSC,O

SCILLATO

RFREQUENCY(kHz) 750

1501251007550250--25--50


Figure 21. Reference Voltagevs. Junction Temperature

VAUX = 12 VRT = 14 kΩRD = 69.8 kΩ

650

550

500

450

400

350

300

250200

600

CT = 150 pF

CT = 470 pF

CT = 220 pF

Figure 22. VREF Discharge Currentvs. Junction Temperature

1501251007550250--25--50


VCSKIP = 1.25 V

I CSKIP(D),CYCLE

SKIP

DISCHARGECURRENT(mA)

15

14

13

12

11

10

9

8

7

6

5

Figure 23. Oscillator Frequencyvs. Junction Temperature

700

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tD(trail)

tD(lead)

tD(trail)

tD(lead)

tD(trail)

tD(lead)

D,D

UTYCYCLE

(%)

90

3010

RT, TIMING RESISTOR (kΩ )

85

75

70

65

60

55

50

45

40

80

50 70 90 110

VAUX = 12 VTJ = 25CRD = 69.8 kΩ

CT = 150 pF

CT = 220 pF

CT = 470 pFD,D

UTYCYCLE

(%)

90

1501251007550250--25--50


Figure 24. Oscillator Frequencyvs. Timing Resistor

VAUX = 12 VRD = 69.8 kΩ

85

75

70

65

60

55

50

45

40

80

RT = 15.8 kΩ, CT = 220 pF

RT = 11.8 kΩ, CT = 470 pF

RT = 20 kΩ, CT = 150 pF

I SS(C),CHARGECURRENT(mA)

15

1501251007550250--25--50


VAUX = 12 V14

12

11

10

9

8

7

6

5

13

DISCHARGE (VUVOV = 0 V)

CHARGE

I SS(D),DISCHARGECURRENT(mA)

t D,O

VERLA

PTIMEDELAY(ns)

500

800

RD, DELAY RESISTOR (kΩ)

Figure 25. Duty Cyclevs. Timing Resistor

450

350

300

250

200

150

100

50

0

400

160 240 320 400

VAUX = 12 VTJ = 25C

LEADING

TRAILING

150

140

130

120

110

100

90

80

70

6050

t D,O

VERLA

PTIMEDELAY(ns)

400

Figure 26. Duty Cyclevs. Junction Temperature

350

250

200

150

100

50

0

300

VAUX = 12 V

TJ, JUNCTION TEMPERATURE (C)1501251007550250--25--50

f OSC,O

SCILLATO

RFREQUENCY(kHz)

3010RT, TIMING RESISTOR (kΩ)

800

700

600

500

400

300

200

100

900

50 70 90 110

VAUX = 12 VTJ = 25C

CT = 150 pF

CT = 220 pF

CT = 470 pF

Figure 27. Soft--Start/Stop Charge and DischargeCurrents vs. Junction Temperature

Figure 28. Overlap Time Delayvs. Delay Resistor

Figure 29. Overlap Time Delayvs. Junction Temperature

RD = 200 kΩ

RD = 20 kΩ

RD = 69.8 kΩ

0

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SINK, Vout2 = 1 V

SOURCE, Vout2 = 11 V

RSNK/SRC,O

UTPUT2DRIVERESISTA

NCE(Ω)

1501251007550250--25--50


VAUX = 12 V17

16

15

14

13

12

11

6

18RIN(VEA),VEAINPUTRESISTA

NCE(kΩ) 50

1501251007550250--25--50


45

35

30

25

20

15

10

5

0

40

VEA(L),PWMCOMPARATO

RLO

WER

INPUTTHRESHOLD

(V)

1.5

1501251007550250--25--50


1.4

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

1.3

RSNK/SRC,O

UTPUT1DRIVERESISTA

NCE(Ω)

10

1501251007550250--25--50


Figure 30. Output 1 Drive Resistancevs. Junction Temperature

VAUX = 12 V9

7

6

5

4

3

2

1

0

8

SINK, Vout1 = 1 V

SOURCE, Vout1 = 11 V

Figure 31. Output 2 Drive Resistancevs. Junction Temperature

Figure 32. VEA Input Resistancevs. Junction Temperature

Figure 33. PWM Comparator Lower Input Thresholdvs. Junction Temperature

VEA = 0 V

10

9

8

7

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DETAILED OPERATING DESCRIPTION

The NCP1562x is a family of voltage mode controllersdesigned for dc--dc converters requiring high--efficiencyand low parts count. These controllers incorporate two inphase outputs with an adjustable overlap delay. The mainoutput is designed for driving a forward converter primaryMOSFET. The secondary output is designed for driving anactive clamp circuit MOSFET, a synchronous rectifier onthe secondary side, or an asymmetric half bridge circuit.Two distinctive features of the NCP1562 are the

soft--stop and a cycle skip overcurrent detector with a timethreshold. The soft--stop powers down the converter in acontrolled manner after a fault is detected. The cycle skiptimer disables the converter if a continuous overcurrentcondition is present.The NCP1562 reduces component count and system size

by incorporating high accuracy on critical specificationssuch as programmable maximum duty cycle, undervoltagedetector and overcurrent threshold. Additional featuresfound in the NCP1562 include line feedforward,bidirectional frequency synchronization up to 1.0 MHz,cycle--by--cycle current limit with leading edge blanking(LEB), independent under and overvoltage detectors,internal startup circuit and soft--start.

SOFT--STOP AND SOFT--STARTThe NCP1562 incorporates a novel soft--stop and

soft--start architecture that combines soft--start andsoft--stop functions on a single pin.Soft--stop reduces the duty cycle until it reaches 0%once

a fault is detected. By slowly reducing the duty cycle duringpower down, the active clamp capacitor (Cclamp) isdischarged. This prevents oscillations between the powertransformer and Cclamp, and ensures the converter turns offin a predictable state.Soft--start slowly increases the duty cycle during power

up allowing the controller to gradually reach steady stateoperation. Combined, both features reduce system stressand power surges.The duty cycle is controlled by comparing the SS

capacitor voltage (VSS) to the Feedforward (FF) Ramp.Soft--start or soft--stop is implemented by slowly chargingor discharging the capacitor on the SS pin. OUT1 isdisabled once the FF Ramp exceeds VSS. The soft--startcharge current is 10 mA and the soft--stop discharge currentis 100 mA, guaranteeing a faster turn OFF time.The converter enters a soft--stop sequence if an

undervoltage, overvoltage, cycle skip or thermal shutdowncondition is detected. Once the converter enters thesoft--stop mode, it will stay in soft--stop mode until VSSreaches 0.2 V even if the fault is removed prior to reaching0.2 V.The preset 1:10 charge:discharge ratio can be reduced by

placing an external resistor between the VREF and SS pins.The resistor should be sized such that the total charge

current does not exceed 100 mA. Otherwise the converterwill not be able to complete a soft--stop sequence.Depending on the converter state, a soft--stop sequence

is handled differently to ensure the fastest response timeand prevent system malfunction. If a soft--stop sequencestarts before VSS exceeds the maximum voltage clamp ofthe FF Ramp (typ. 3.0 V) and the PWMComparator (VEA)is not yet controlling the duty cycle, a controlled dischargeof CSS commences immediately, as shown in Figure 34.However, if VEA is controlling the duty cycle, CSS isdischargeduntil soft--stop sets a duty cycle equal to the dutycycle set by VEA. A controlled discharge commencesafterwards, as shown in Figure 35. If VSS exceeds the FFRamp and the VEA is not controlling the duty cycle, VSS isforced to the peak voltage of the FF Ramp, before startinga controlled discharge of CSS, as shown in Figure 36. Theduty cycle set at the beginning of the soft--stop event neverexceeds the duty cycle prior to the soft--stop event.

Figure 34. Soft--Stop Before Soft--Startis Complete and VEA is Open.

(VEA is not controlling the duty cycle)

VEA

VSSFF Ramp

Figure 35. Soft--Stop Behavior when VEAControls the Duty Cycle.

VSSVX = VEA -- Vf

VEA

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Figure 36. Soft--Stop Behavior After Soft--Startis Complete and VEA is Open.

(VEA is not controlling the duty cycle)

VEA

FF Ramp

VSS

If the voltage on the VAUX pin reaches VAUX(off2), CSS isimmediately discharged and the outputs are disabled. VSSshould not be pulled up or down externally.

CURRENT LIMITThe NCP1562 has two overcurrent modes,

cycle--by--cycle and cycle skip, providing the bestprotection during momentary and continuous overcurrentconditions.

Cycle--by--CycleIn cycle--by--cycle, the conduction period ends once the

voltage on the CS pin reaches the current limit voltagethreshold (VILIM). The NCP1562A has a VILIM of 0.2 Vand the NCP1562B has a VILIM of 0.5 V.

Cycle SkipTraditionally, a voltage on the CS higher than VILIM has

been used to trigger a cycle skip fault. Unfortunately, thefast response time of modern controllers makes it hard toreach a voltage on the CS pin higher than VILIM.Instead of using a higher voltage threshold to detect a

cycle skip fault, the NCP1562 uses a timer. It monitors thecurrent limit comparator and if a continuouscycle--by--cycle current limit condition exists the converteris disabled. The time to disable the converter and the timethe converter is disabled are programmed by the capacitoron the CSKIP pin, CCSKIP.The cycle skip detection circuit charges CCSKIP with a

continuous 100 mA current once cycle--by--cycle currentlimit fault is detected. If the current limit fault persists,CCSKIP continues to charge until reaching the cycle skipupper threshold (VCSKIP(peak)) of 3.0 V. Once reached, theconverter enters the soft–stop mode and CCSKIP isdischarged with a constant 10 mA current. A new soft--startsequence commences once CCSKIP reaches the lower cycleskip threshold (VCSKIP(valley)) of 0.5 V. If the overcurrentcondition is still present, the capacitor starts charging onthe next current limit event. Otherwise, CCSKIP isdischarged down to 0 V.The cycle skip capacitor provides a means of

remembering previous overcurrent conditions. If acontinuous overcurrent condition is removed beforereaching VCSKIP(peak), CCSKIP starts a controlleddischarge. If the continuous overcurrent fault is once againdetected before CCSKIP is completely discharged, CCSKIPcharges from its existing voltage level, taking less time toreach VCSKIP(peak). Figure 37 shows operating waveformsduring a continuous overcurrent condition. For optimaloperation, the cycle skip discharge time should be longerthan the soft--stop period.

Figure 37. Cycle Skip Waveforms

VCSKIP(valley)

VCSKIP(peak)

VCSKIP

CSVILIM

VSS

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In some instances it may be desired to latch (instead ofauto re--start) the NCP1562 after a cycle skip event isdetected. This can be easily achieved by adding an externallatch. Figures 35 and 36 show an implementation of anintegrated and a discrete latch, respectively. In general thecircuitswork by pulling CSKIP to VREF, preventing it fromreachingVCSKIP(valley) once the CSKIP voltage reaches theturn on threshold of the latch. The external latch is clearedby bringing the UVOV voltage below VUV and disablingVREF.

VREF

CREF

CSKIP

CCSKIP

OUTY

VCC

INA

OE MC74VHC1GT126

Figure 38. External Latch Implemented usingON Semiconductor’s MiniGatet Buffer

The latch in Figure 38 consists of a TTL level tri--stateoutput buffer from ON Semiconductor’s MiniGatetfamily. The enable (OE) and output (OUTY) terminals areconnected to CSKIP and the VCC and INA pins areconnected to VREF. The output of the buffer is in a highimpedance mode when OE is low. Once a continuouscurrent limit condition is detected, the CSKIP timer isenabled and CSKIP begins charging. Once the voltage onCSKIP reaches the enable threshold of the buffer, theoutput of the buffer is pulled to VREF, latching the CSKIPtimer. The OE threshold of the buffer is typically 1.5 V.

VREF

CREF

CCSKIP

CSKIP

BSS84L

M2

24.9 kΩ

2N7002L

Rpull--up

M1

Figure 39. External Latch Implemented usingDiscrete N and P--Channel MOSFETs

A latch implemented using discrete N and P--channelMOSFETs is shown in Figure 39. The latch is enabled oncethe CSKIP voltage reaches the threshold of M1. Once M1turns on, it pulls low the gate of M2. CSKIP is then pulledto VREF by M2. It is important to size Rpull--up correctly. IfRpull--up is too big, it will not keep M2 off while VREFcharges. Thiswill cause the controller to latch during initialpower--up. In this particular implementation the turn onthreshold of M1 is 2 V and Rpull--up is sized to 24.9 k.

Leading Edge BlankingThe current sense signal is prone to leading edge spikes

caused by the power switch transitions. The current signalis usually filtered using an RC low–pass filter to avoidpremature triggering of the current limit circuit. However,the low pass filter will inevitably change the shape of thecurrent pulse and also add cost and complexity. TheNCP1562 uses LEB circuitry that blocks out the first 70 ns(typ) of each current pulse. This removes the leading edgespikeswithout altering the currentwaveform. The blankingperiod is disabled during soft--start as the blanking periodmay be longer than the startup duty cycle. It is also disabledif the output of the SaturationComparator is low, indicatingthat the output is not yet in regulation. This occurs duringpower up or during an output overload condition.

Supply Voltage and Startup CircuitThe NCP1562 internal startup regulator eliminates the

need for external startup components. In addition, thisregulator increases the efficiency of the supply as it uses nopower when in the normal mode of operation, but insteaduses power supplied by an auxiliary winding. TheNCP1562 incorporates an optimized startup circuit thatreduces the requirement of the supply capacitor,particularly important in size constrained applications.The startup regulator consists of a constant current

source that supplies current from the input line voltage(Vin) to the supply capacitor on the VAUX pin (CAUX). Thestartup current (Istart) is typically 10 mA.Once CAUX is charged to 10.3 V (VAUX(on)), the startup

regulator is disabled and the outputs are enabled if there areno UV, OV, cycle skip or thermal shutdown faults. Thestartup regulator remains disabled until the lower voltagethreshold (VAUX(off1)) of 8.0 V is reached. Once reached,the startup circuit is enabled. If the bias current requirementout of CAUX is greater than the startup current, VAUX willdischarge until reaching the lower voltage threshold(VAUX(off2)) of 7.0 V. Upon reaching VAUX(off2), theoutputs are disabled.Once the outputs are disabled, the biascurrent of the IC is reduced, allowing VAUX to charge backup. This mode of operation allows a dramatic reduction inthe size of CAUX as not all the power required for startupneeds to be stored by CAUX. This mode of operation isknownasDynamic Self Supply (DSS). Figure 40 shows therelationship between VAUX(on), VAUX(off1), VAUX(off2) andUV. As shown in Figure 40, the outputs are not enableduntil the UV fault is removed and VAUX reaches VAUX(on).

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Figure 40. Startup Circuit Waveforms

VAUX(off1)

VAUX(on)

VAUX

Vinhibit

VUVOV

VREF

VSS

Vout1

The startup regulator is disabled by biasing VAUX aboveVAUX(on). This feature allows the NCP1562 to operate froman independent 12 V supply. If operating from anindependent supply, the Vin and VAUX pins should beconnected together. The independent supply shouldmaintain VAUX above VAUX(on). Otherwise, the OutputLatchwill not be SETand the outputswill remainOFFaftera fault condition is removed.The startup circuit sources current into the VAUX pin. It

is recommended to place a diode between CAUX and theauxiliary supply as shown in Figure 41. This allows theNCP1562 to charge CAUX while preventing the startupregulator from sourcing current into the auxiliary supply.

Disable

VinIstart VAUX

IAUX CAUX Isupply

Auxiliary Supply orIndependent Supply

Figure 41. Recommended VAUX Configuration

CAUX provides power to the controller while operatingin the self--bias or DSS mode. During the converterpowerup, CAUX must be sized such that a VAUX voltagegreater than VAUX(off2) is maintained while the auxiliarysupply voltage is building up. Otherwise, VAUX willcollapse and the controller will turn OFF. Also, the VAUXdischarge time (from 10.3 V to 7.0 V) must be greater thatthe soft--start charge period to assure the converter turns

ON. The IC bias current, gate charge load on the outputs,and the 5.0 V reference load must be considered tocorrectly size CAUX. The current consumption due toexternal gate charge is calculated using Equation 1.

IAUX(gate charge)= f ⋅QG (eq. 1)

where, f is the operating frequency and QG is the gatecharge.An internal supervisory circuit monitors VAUX and

prevents excessive power dissipation if the VAUX pin isaccidentally shorted. While VAUX is below 1.2 V, thestartup circuit is disabled and a current source (Iinhibit)charges VAUX with a minimum current of 50 mA. OnceVAUX reaches 1.2 V the startup circuit is enabled.Therefore it is imperative that VAUX is not loaded (driver,resistor divider, etc.) with more than 50 mAwhile VAUX isbelow 1.2 V. Otherwise, VAUX will not charge. If a loadgreater than 50 mA is present, a resistor can be placedbetween the Vin and VAUX pins to help charge VAUX to1.2 V.The startup circuit is rated at a maximum voltage of

100 V. If the device operates in the DSS mode, powerdissipation should be controlled to avoid exceeding themaximumpower dissipationof the controller. If dissipationon the controller is excessive, a resistor can be placed inseries with the Vin pin. This will reduce power dissipationon the controller and transfer it to the series resistor.

Line Under/Overvoltage DetectorThe same pin is used for both line undervoltage (UV) and

overvoltage (OV) detection using a novel architecture

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(patent pending). This architecture allows both the UVandOV levels to be set independently. Both the UV and OVdetectors have a 100 mV hysteresis.The line voltage is sampled using a resistor divider as

shown in Figure 42.

--+OV Comparator

VOVCOMP

3.0 V+

--

--+UV Comparator

VUVCOMP

2.0 V+

--

--+

2.5 V+

--

UVOV

CUVOV

R1

R2

Vin

Ioffset(UVOV)

Figure 42. Line UVOV Detectors

A UV condition exists if the UVOV voltage is belowVUV, typically 2.0 V. The ratio of R1 andR2 determines theUV turn threshold. Once the UVOVvoltage exceeds 2.5 V,an internal current source (Ioffset(UVOV)) sinks 50 mA intothe UVOVpin. Thiswill clamp the UVOVvoltage at 2.5 Vwhile the current across R1 is less than Ioffset(UVOV). If theinput voltage continues to increase, the 50 mA source willbe overridden and the voltage at the UVOV pin willincrease. An OV condition exists if the UVOV voltageexceeds VOV, typically 3.0 V. Figure 43 shows therelationship between UVOV and Vin.

Figure 43. UVOV Detectors Typical Waveforms

Time

VUVOV(V)

Vin(V)

VOVCOMP

VUVCOMP

VUVOV

While the internal current source is disabled, the UVOVvoltage is solely determined by the ratio of R1 and R2. Theinput voltage at which the converter turns ON is given by

Equation 1. Once the internal current source is enabled, theabsolute value of R1 together with the ratio of R1 and R2determine the turn OFF threshold as shown in Equation 2.

Vin(UV)= VUV×(R1+R2)

R2(eq. 1)

Vin(OV)= VOV(R1+ R2)

R2+ (Ioffset(UVOV)×R1)

(eq. 2)

The undervoltage threshold is trimmed duringmanufacturing to obtain3% accuracy allowing a tighterpower stage design.Once the line voltage is within the operating range, and

VAUX reaches VAUX(on), the outputs are enabled and asoft--start sequence commences. If a UV or OV fault isdetected afterwards, the converter enters a soft--stopmode.A small capacitor is required (>1000 pF) from the

UVOV pin to GND to prevent oscillation of the UVOV pinand filter line transients.

Line FeedforwardThe NCP1562 incorporates line feedforward (FF) to

limit the maximum volt--second product. It is the linevoltage times the ON time. This limit prevent saturation ofthe transformer in forward and flyback topologies.Anotheradvantage of feedforward is a controller frequency gainindependent of line voltage. A constant gain facilitatesfrequency compensation of the converter.Feedforward is implemented by generating a ramp

proportional to Vin and comparing it to the error signal. Theerror signal solely controls the duty cycle while the inputvoltage is fixed. If the line voltage changes, the FF Rampslope changes and duty cycle is immediately adjusted insteadof waiting for the change to propagate around the feedbackloop and be reflected back on the error signal.The FFRamp is generatedwith anR--C (RFFCFF) divider

from the input line as shown in Figure 44. The divider isselected such that the FFRamp reaches 3.0 V in the desiredmaximum ON time. The FF Ramp terminates byeffectively grounding CFF during the converter OFF time.This can be triggered by the FF Ramp reaching 3.0 V, orany other condition that limits the duty cycle.

To PWM and VSComparators

FF Reset IFF(D)

Vin

RFF IRFF

CFF

FF

3 V

0 V

Tton

Figure 44. Feed Forward Ramp Generation

The FF pin is effectively grounded during power orduring standby mode to prevent the FF pin from chargingup to Vin.

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The minimum value of RFF is determined by the FFRamp discharge current (IFF(D)). The current through RFF(IRFF) should be at least ten times smaller than IFF(D) for asharp FF Ramp transition. Equations 3 and 4 are used todetermine RFF and CFF.

Vin0.1× IFF(D)

≤ RFF (eq. 3)

CFF= D

ln VinVin --3 V× f×RFF

(eq. 4)

where, f is the operating frequency. It is recommended tobias the FF circuit with enough current to provide goodnoise immunity.

PWM ComparatorIn steady state operation, the PWM Comparator adjusts

the duty cycle by comparing the error signal to the FFRamp. The error signal is fed into the VEA pin. TheVEApincan be driven directlywith an optocouplerwithout the needof an external pullup resistor as shown in Figure 45. Insome instances, it may be required to have a pullup resistorsmaller than the internal resistor (R4) to adjust the gain ofthe isolation stage. This is easily accomplished byconnecting an external resistor (REA) in parallel with R4.REA is connected between the VREF and VEA pins. Theeffective pullup resistance is the parallel combination ofR4 and REA.

PWMComparator

+--

+

--0.2 V

270 kΩ

2 kΩ

VREF

REA (Optional)

VEA

FF

FeedbackSignal

FF Ramp

3 V

0 V

Figure 45. Optocoupler Driving VEA Input

20 kΩ

The drive of the VEA pin is simplified by internallyincorporating a series diode and resistor. The series diodeprovides a 0.7 V offset between the VEA input and thePWM Comparator inverting input. It allows reaching zeroduty cycle without the need of pulling the VEA pin all theway to GND. The outputs are enabled if the VEA voltage isapproximately 0.5 V above the valley of the FF Ramp.

OutputsThe NCP1562 has two in--phase output drivers with an

adjustable overlap delay (tD). The main output, OUT1, hasa source resistance of 4.0 Ω (typ) and a sink resistance of2.5 Ω (typ). The secondary output, OUT2, has a source anda sink resistance of 12 Ω (typ). OUT1 is rated at amaximum of 2.0 A and OUT2 is rated at a maximum of

1.0 A. If a higher drive capability is required, an externaldriver stage can be easily added as shown in Figure 46.

VAUX

Output

Figure 46. Discrete Boost Drive Stage

OUT1or

OUT2

OUT1 drives themainMOSFET, and OUT2 drives a lowside P--Channel active clamp MOSFET. A high sideN--Channel active clamp MOSFET or a synchronousrectifier can also be driven by inverting OUT2. OUT2 ispurposely sized smaller than OUT1 because the activeclamp MOSFET only sees the magnetizing current.Therefore, a smaller active clampMOSFETwith less inputcapacitance can be used compared to the main switch.Once VAUX reaches VAUX(on) (typically 10.3 V), the

internal startup circuit is disabled and the outputs areenabled if no faults are present. Otherwise, the outputsremain disabled until the fault is removed and VAUXreachesVAUX(on). The outputs are disabled after a soft--stopsequence if VAUX is below VAUX(on) or if VAUX reaches7.0 V.The outputs are biased directly fromVAUX and their high

state voltage is approximately VAUX. Therefore, theauxiliary supply voltage should not exceed the maximumgate voltage of the main or active clamp MOSFET.The high current drive capability of the outputs will

generate inductance--induced spikes if inductance is notreduced on the outputs. This can be done by reducing theconnection length between the drivers and their loads andusing wide connections.

Overlap DelayThe overlap delay prevents simultaneous conduction of

the main and active clamp MOSFETs. The secondaryoutput, OUT2, precedes OUT1 during a low to hightransition and trails OUT1 during a high to low transition.Figure 47 shows the relationship between OUT1 andOUT2.

tD (Leading)

OUT1

OUT2

tD (Trailing)

Figure 47. Output Timing Diagram

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The output overlap delay is adjusted by connecting aresistor, RD, from the tD pin to ground. The overlap delayis proportional to RD. A minimum delay of 20 ns isobtained by grounding the tD pin.The leading delay is purposely made longer than the

trailing delay. This allows the user to optimize the delay forthe turn on transition of the main switch and ensures theactive clamp switch always exhibits zero volt switching.

Analog and Power Ground (PGND)The NCP1562 has an analog ground, GND, and a power

ground, PGND, terminal. GND is used for analogconnections such as VREF, RTCT, feedforward amongothers. PGND is used for high current connections such asthe internal output drivers. It is recommended to haveindependent analog and power ground planes and connectthem at a single point, preferably at the ground terminal ofthe system. This will prevent high current flowing onPGND from injecting noise in GND. The PGNDconnection should be as short and wide as possible toreduce inductance--induced spikes.

OscillatorThe oscillator frequency and maximum duty cycle are

set by an RTCT divider from VREF as shown in Figure 48.A 500 mA current source (IRTCT) discharges the timingcapacitor (CT) upon reaching its peak threshold(VRTCT(peak)), typically 3.0 V. Once CT reaches its valley

voltage (VRTCT(valley)), typically 2.0 V, IRTCT turns OFFallowing CT to charge back up through RT. The resultingwaveform on the RTCT pin has a sawtooth like shape.

EnableIRTCT

VREF

RTCT

RT

CT

3 V

2 V

Figure 48. Oscillator Configuration

OUT2 is set high once VRTCT(valley) is reached, followedby OUT1 delayed by the overlap delay. Once VRTCT(peak)is reached, OUT1 goes low, followed by OUT2 delayed bytD.The duty cycle is the CT charge time (tRTCT(C)) minus the

overlap delayover the total charge and discharge (tRTCT(D))times. The charge and discharge times are calculated usingEquations 5 and 6. However, these equations are anapproximation as they do not take into account thepropagation delays of the internal comparator.

tRTCT(C)= RTCT× lnVRTCT(valley)--VREFVRTCT(peak)--VREF

(eq. 5)

tRTCT(D)= RTCT× ln (IRTCT×RT)+ VRTCT(peak)--VREF(IRTCT×RT)+ VRTCT(valley)--VREF

(eq. 6)

The duty cycle, D, is given by Equation 7.

D=tRTCT(C)--tD

tRTCT(C)+ tRTCT(D)(eq. 7)

Substituting Equations 5, 6, and 7, and after a littlealgebraic manipulation and replacing values, it simplifiesto:

D=lnVRTCT(valley)--VREF

VRTCT(peak)--VREF-- tD

RTCT

lnVRTCT(valley)--VREFVRTCT(peak)--VREF

×(IRTCT×RT)+VRTCT(peak)--VREF(IRTCT×RT)+VRTCT(valley)--VREF

(eq. 8)

It can be observed that D is set by RT, CT and tD. Thisequation has two variables and can be solved iteratively. Ingeneral, the time delay is a small portion of theON time andcan be ignored as a first approximation. RT is then selected

to achieve a given duty cycle. Once the RT is selected, CTis chosen to obtain the desired operating frequency usingEquation 9.

f= 1

RTCT× lnVRTCT(valley)--VREFVRTCT(peak)--VREF×

(IRTCT×RT)+VRTCT(peak)--VREF(IRTCT×RT)+VRTCT(valley)--VREF

(eq. 9)

Figures 23 through 26 show the frequency and duty cyclevariation vs RT for several CT values. RT should not be lessthan 6.0 kΩ. Otherwise, the RTCT charge current willexceed the pulldown current and the oscillator will be in anundefined state.

SynchronizationA proprietary bidirectional frequency synchronization

architecture allows multiple NCP1562 to synchronize in amaster--slave configuration. It can synchronize tofrequencies above or below the free running frequency.

NCP1562A, NCP1562B

http://onsemi.com22

The SYNC pin is in a high impedance mode during thecharging of the RTCT Ramp. In this period the oscillatoraccepts an external SYNC pulse. If no pulse is detectedupon reaching the peak of the RTCTRamp, a 100 nsSYNCpulse is generated. The SYNC pulse is generated byinternally pulling the SYNC pin to VREF. The peak voltageof the SYNC pin is typically 4.3 V. Once the 100 ns timerexpires, the pin goes back into a high impedance mode andan external resistor is required for pulldown as shown inFigure 49.

VREF

RTCT

SYNC

RSYNC

CT

RT

Figure 49. SYNC Pulse

The slew rate of the sync pin is determined by the pincapacitance and external pulldown resistor. The maximumsource current of the SYNC pin is 1.0 mA. The resistor issized to allow the SYNC pin to discharge before the startof the next cycle.If an external pulse is received on the SYNC pin before

the internal pulse is generated, the controller enters theslave mode of operation. Once operation in slave modecommences, CT begins discharging and the RTCT Rampupper threshold is increased to 4.0 V.If a controller in slavemode doesnot receive a sync pulse

before reaching the RTCT Ramp peak voltage (4.0 V), theupper threshold is reset back to 3.0 V and the converterreverts to operation in master mode. To guarantee theconverter stays in slave mode, the minimum clock periodof the master controller has to be less than the RTCT chargetime from 2.0 V to 4.0 V.Two NCP1562’s are synchronized by connecting their

SYNC pins together. The first device that generates a syncpulse during powerup becomes the master. A diodeconnected as shown in Figure 50 can be used topermanently set one controller as the master. The diodeprevents the master from receiving the SYNC pulse of theslave controller.

MASTERCONTROLLER

SLAVECONTROLLER

SYNC

RSYNC1 RSYNC2

SYNC

Figure 50. Master--Slave Configuration

5.0 V ReferenceThe NCP1562 has a precision 5.0 V reference output. It

is a buffered version of the internal reference. The 5.0 Vreference is biased directly fromVAUX and it can supply upto 5.0 mA. Load regulation is 50 mV and line regulation is100 mV within the specified operating range.It is required to bypass the reference with a capacitor.

The capacitor is used for compensation of the internalregulator and high frequency noise filtering. The capacitorshould be placed across the VREF and GND pins. In mostapplications a 0.1 mF will suffice. A bigger capacitor maybe required to reduce the voltage ripple caused by theoscillator current. The recommended capacitor range isbetween 0.047 mF and 1.0 mF.During powerup, the 5.0 V reference is enabled once

VAUX reaches VAUX(on) and a UV fault is not present.Otherwise, the reference is enabled once the UV fault isremoved and VAUX reaches VAUX(on).Once a UV fault is detected after the reference has been

enabled, the reference is disabled after the soft--stopsequence is complete if the UV fault is still present. If theUV fault is removed before soft--stop is complete, thereference is not disabled.

Application InformationON Semiconductor provides an electronic design tool, a

demonstration board and an application note to facilitatedesign of the NCP1562 and reduce development cycletime. All the tools can be downloaded or ordered atwww.onsemi.com.The electronic design tool allows the user to easily

determine most of the system parameters of an activeclamp forward converter. The tool evaluates the power andactive clamp stages aswell as the frequency response of thesystem. The tool is used to design a converter for a 48 Vtelecom system. The converter delivers 100 W at 3.3 V.The circuit schematic is shown in Figure 51. The converterdesign is described in Application Note AND8273/D.

NCP1562A, NCP1562B

http://onsemi.com23

UVOV

FF CS

GND

RTCT

SYNC

VREF

Vin

OUT1

PGND

OUT2

CSKIP tD SS

VAUX

VEA

J1 J2 J5

L3

C22

+ 471C10

D7

D2

21 4T

TX1

51665

1000m

1.5m

L1

C2

C1

2.2

C3

R1

523k

C16

0.01

R4

32.4k

V ref

C23 0.1

D1

R15

4.75

4X2

R17 10k

D4

33m

R2

C14 0.018

44.2k

R5

C28 0.1

0.01

C13C11

100p

R16

10kX1

C26

0.01

R3

45.3k

4 7

R23 2.0

X3 X4

R11 4.22k

R6

10k Q1 123

C8

0.1

C12 270p

27p

C30

R8

32.4k

15k

R9

CS

C24

470p

R10

100

U2

PS2703--I--M--A

1 2

R18

3.01k

BC817

R25

10k

X5X6

44

SEC_PWR1

L2 1.5m

++

C17 47

C18 47

C19 150

C20 150

-- +

7U4B

56

348

R13 R14 953

-- +

4 81U4A

32

SEC_PWR2

SEC_PWR1

Q2

BC807

C15 2.2

24.9

R26

D6

D3

49.9

R12

4.22k

R7

C9 0.1

C6

0.1

2.49k

R284.22k

R27

534

C5

1000p

R22

open

R21

16.2k

C29 1000p

D5

5.9k

R20

C25

0.056

J3 J4

R30 348

8 9

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

CS

6T1T

4

3

C27

2200p

LM258G

342

1

3

NCP1562A

4 4

U1

Figure 51. Circuit Schematic

C31 47

5,6,7,8

1,2,3

5,6,7,8 5,6,7,8

1,2,3

1,2,3

1,2,3

1,2,3

5,6,7,8

5,6,7,8

3.3V

+ --

R24

10kR29 2.0

36--72V

+ --2.2

2.2

SEC_PWR2

+

C4

2.2

C7 22

R19 10

+C21 150

D1

=MBRM120ET1G

D2--D7=MMSD914T1G

X1=FDD2582

X2=IRF6217PBF

X3--X6=NTM

FS4835NT1G

NCP1562A, NCP1562B

http://onsemi.com24

ORDERING INFORMATIONDevice Package Current Limit Shipping†

NCP1562ADBR2G TSSOP--16(Pb--Free)

200 mV2500 Tape & Reel

NCP1562BDBR2G TSSOP--16(Pb--Free)


NCP1562ADR2G SO--16(Pb--Free)


NCP1562BDR2G SO--16(Pb--Free)


†For informationon tapeand reel specifications, includingpart orientationand tapesizes, please refer toourTape andReel PackagingSpecificationBrochure, BRD8011/D.

NCP1562A, NCP1562B

http://onsemi.com25

PACKAGE DIMENSIONS

TSSOP--16CASE 948F--01

ISSUE B

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C -- -- -- 1.20 -- -- -- 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.18 0.28 0.007 0.011J 0.09 0.20 0.004 0.008J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOTEXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALLNOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTALIN EXCESS OF THE K DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.

7. DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE --W--.

_ _ _ _

SECTION N--N

SEATINGPLANE

IDENT.PIN 1

1 8

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

HG

DETAIL E

F

M

L

2X L/2

--U--

SU0.15 (0.006) T

SU0.15 (0.006) T

SUM0.10 (0.004) V ST

0.10 (0.004)--T--

--V--

--W--

0.25 (0.010)

16X REFK

N

N

7.06

16X0.36

16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

*For additional information on our Pb--Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NCP1562A, NCP1562B

http://onsemi.com26

PACKAGE DIMENSIONS

SOIC--16CASE 751B--05

ISSUE K

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATINGPLANE

F

JM

R X 45_

G

8 PLP--B--

--A--

M0.25 (0.010) B S

--T--

D

K

C

16 PL

SBM0.25 (0.010) A ST

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 9.80 10.00 0.386 0.393B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019

_ _ _ _

6.40

16X0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

16

8 9

8X

*For additional information on our Pb--Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ONSemiconductor and are registered trademarks of SemiconductorComponents Industries, LLC (SCILLC). SCILLC reserves the right tomake changeswithout further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume anyliability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidentaldamages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performancemay vary overtime. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license underits patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or deathmay occur. Should Buyer purchase or use SCILLC products for any such unintendedor unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees,subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim ofpersonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATIONN. American Technical Support: 800--282--9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81--3--5773--3850

NCP1562A/D

LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303--675--2175 or 800--344--3860 Toll Free USA/CanadaFax: 303--675--2176 or 800--344--3867 Toll Free USA/CanadaEmail: [email protected]

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your locaSales Representative

ncp1562a - high performance active clamp/reset pwm controller

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