nanoscale devices mnt-204 unit-1
TRANSCRIPT
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VLSI Technology
UNIT-1
Contents1.1 Silicon technology1.2 Processing methods
1.2.1 Cleaning1.2.2 Etching1.2.3 Oxidation1.2.4 Gettering1.2.5 Doping1.2.6 Epitaxy
1.3 Sputtering1.4 Plasma enhanced CVD1.5 Reactive ion etching1.6 Moores Law1.7 Design rules for CMOS
1.7.1 90nm1.7.2 45nm1.7.3 32nm
1.8 Semiconductor device road map1.9 Silicon on insulator technology
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Silicon vs Germanium
Types of Contamination
• Cleaning play very important role, and an important task is nanofabrication as there aremany types of contaminations.
• Water, gases and chemicals are purified of contaminants and filtered of particles.• Sources of Contamination:• 1. Particulate• 2. Films• Particulate: many bits of materials present on a wafer. As feature size shrinks size of
particulates that can cause increases.• Sources are: Silicon dust, Quarts dust, atmospheric dust, particles originating from
clean room (equipment, personnel)• Film Contamination: Layer of foreign material on wafer surface are source of film
contamination.• Sources are: Solvent residues (Acetone, isopropyl, alcohol, methyl alcohol, xylene,
photoresist developer, or post development rinsing, oil films introduce due to improperlyfiltered air or gas lines).
• Some time first cleaning process is also responsible for contamination of film or particulatetype.
• To prevent this multiple stages of cleaning is done
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Identification of Particulate Contamination
• It is necessary to identify level of contamination after each process and improve wafercleaning to minimize particulate contamination.
• Tools:• Optical Microscopy: It is used to determine scratches and solvent residue.• (down to some micrometer (1-2µm)).• SEM: It is also used to analyze wafer contamination• Automatic Laser Scanners: To measure surface defects and contamination (Shown
bealow). Use to detect particles, pits, cracks, scratches, and fingerprints. Cannot used todetect contamination on patterned surface.
1.2.1 Wafer Cleaning Procedure(Film Contamination)
• Both Chemical cleaning procedure and particulates cleaning techniques are used to producecompletely clean surface.
• When One technique follows another, the later steps must not recombinant the surface.
To remove photoresist(If present), DI water of10-20MΩ-cm
120oC, 10-20min
H2SO4+H2O2 (4:1)Preliminary Cleaning(Piranha)
1.
Avoid Storage or Storein a close glasscontainer
Using rinser Dryer,DI water to rinse,N2 to dry
Drying of Wafer
Desorption ofremaining atomic andionic contaminants.
50–80 ◦C,10–20min
HCl:H2O2:H2O(1:1:6)
RCA-24.
Not necessary if SiO2completely covers thewafer.
RoomTemperature20-30min
HF+H2O (1:10)Stripping of HydrousOxide Film formedduring RCA-1
3.
To remove residueorganic contaminationand certain metals.
50–80 ◦C,10–20min
NH4OH:H2O2:H2O(1:1:5)
RCA-1 (ammoniaperoxidemixture)
2.
UsesTemperature/ Time
ChemicalComposition
NameSr
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Wafer Cleaning(Particulate contamination)
• Removal of insoluble particulate contamination are commonly carried out by• ultrasonic scrubbing• High Pressure spraying (13.8-20.7MPa)• Mechanical scrubbing• Ultrasonic Scrubbing: Wafer are immersed in a liquid medium to which sonic energy
(20,000Hz-50,000Hz) is applied. Microscopic bubble are rapidly formed and collapseunder the pressure of the sonic agitation, producing shock waves which impinges on wafersurfaces. These shock waves loosen particle matter
• Scrubbing Process: This Process operate by rotating a brush across the surface of wafer
1.2.2 Etching
• Etching is the fabrication process in which material is removed from the siliconsubstrate. When a mask layer is used to protect specific regions of the wafer surface,the goal is to precisely is to remove the material which is not covered by the mask.
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Bias, Tolerance, Etch rate• Etch process is not completely attainable.• Means etching process is not capable of transferring the pattern established by the
protective mask into the underling surface.• Degree by which process fail is specified by two parameters: Bias and Tolerance.
• Bias: It is the difference in the lateral dimension change in the etched image and themask image.
• Tolerance: It is the measure of the statistical distribution of bias value that characterizethe uniformity of etching.
• Etching rate: Rate at which material remove from the material surface. (Ao/s).• High etching rate makes problem of lateral etching over a problem.
• Material is generally removes from both the horizontal and vertical direction.• So,• Lateral etch ratio (LR) is
Isotropic and anisotropic etching(Etching profile)
• Isotropic etching: When etching can proceed in all the direction at the same rate.etch profile is rounded. isotropic etching cannot be used to make fine features.
• Most wet etchants result in an isotropic profile.• Undercutting can be compensated by making the initial mask feature larger than the
desired width, for light field structures and vice versa for dark field structures.• Anisotropic etching: When the etching can proceed exclusively in one direction, it is
said to be [email protected]
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Degree of Anisotropy
• When LR=0, then A=1; completely anisotropic etching.• When LR=1, means horizontal and vertical etch rate are equal. then A=0; this corresponds
to completely isotropic etching.
Wet Etching• Wet etching process are generally isotropic.• For those process that involve the patterning of linewidth greater than 3µm, wet etching
is valid.• Importance of wet etching:1. Low cost2. Reliable3. High throughput process with excellent selectivity for most wet etch process.• Disadvantage:1. Higher cost of etchant and DI water (compared to dry etch gas expenses)2. Increase personal safety hazards from chemical handling.3. Exhaust fumes and the potential of explosions.4. Resist adhesion problem etching not [email protected]
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Etching of Silicon(wet etching)
• Both single crystal and polycrystalline silicon are typically wet etched in mixture of nitricacid (HNO3) and hydrofluoric acid (HF). This reaction is initially form SiO2 layer on thesilicon substrate, and HF dissolve the oxide away.
• Both single crystal and polycrystalline silicon are typically wet etched in mixture of nitricacid (HNO3) and hydrofluoric acid (HF). This reaction is initially form SiO2 layer on thesilicon substrate, and HF dissolve the oxide away.
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Etching SiO2• Wet etching of SiO2 is accomplished with various hydrofluoric acid
• HF solution is 49% in water. Thermally grown SiO2 etched at approximately 3nm/s at25oC.
Plasma etching• Anisotropy results from directional ion bombardment in the plasma reactor.• Vertical walls and highly accurate reproduction of photoresist dimensions translate to
closely spaced structures.
• Plasma etching is done in a vacuum chamber by reactive gases excited by RF-fields.• Both the excited and ionized species are important for plasma etching.• Excited molecules like CF4 are very reactive, and ionic species like CF+3 are
accelerated by the RF field, and they impart energy directionally to the surface.• Plasma etching is thus a combination of chemical (reactive) and physical
(bombardment) processes.
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• In RIE, the substrate is placed inside a reactor in which several gases are introduced.• A plasma is struck in the gas mixture using an RF power source, breaking the gas
molecules into ions.• The ions are accelerated towards, and reacts at, the surface of the material being
etched, forming another gaseous material.• If the ions have high enough energy, they can knock atoms out of the material to be
etched without a chemical reaction.• It is a very complex task to develop dry etch processes that balance chemical and
physical etching,• By changing the balance it is possible to influence the anisotropy of the etching.
Plasma Etching mechanism
• Chemical bonds need to be broken for etching to take place. Bond energies,therefore, give indications of possible etching reactions (Table).
• Reactions that lead to bonds stronger than the Si–Si bond will etch silicon.• if the products have stronger bonds than Si–O, silicon dioxide will be etched.• Example:• Fluorine, chlorine and bromium will etch silicon because silicon–halogen bonds are
stronger than silicon–silicon bonds.• Only Si–F bond is stronger than Si–O bond and therefore only fluorine is predicted to
etch oxide.• However, because of ion bombardment, oxide is slightly etched in chlorine and
bromine plasmas also, but to a much lesser extent than in fluorine plasmas.
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Silicon Etching• Silicon is easily etched by halogens both fluorides (SiF4), chlorides (SiCl4), and bromides
(SiBr4) of silicon are volatile at room temperature, at millitorr pressures.
Silicon Nitrite
• Silicon nitride (Si3N4) is etched by fluorine, producing SiF4 and NF3.
Silicon Oxide
• Only Si–F bond is stronger than Si–O bond and therefore only fluorine is used to etchoxide.
1.2.3 Oxidation• Oxidation is defined as the interaction between oxygen molecules and
all the different substances they may contact.• oxidation came to be more precisely defined as the loss of at least one
electron when two or more substances interact. Those substances mayor may not include oxygen.
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Oxidation of Silicon: Introduction
• Silicon has the unique ability to oxidized into silica, which a chemically stable,protective and insulating layer on the surface of the wafer.
• SiO2 is probably a more important material in silicon technology than silicon itself.• Silicon dioxide has functions as capacitor dielectric and isolation material , in which
case the oxide forms a part of the finished device.• oxides are used intermittently many times during silicon processing as a masking
material for diffusion or etching, and as a cleaning method to reclaim perfect siliconsurface.
Function of SiO2 on Silicon wafer
• To mask against diffusion or ion implantation.• To passivate the surface electrically and chemically.• To isolate the device from another and.• To act as a component in MOS devices.
Oxidation of Silicon: Oxidation Process• In most integrated circuits, the SiO2 is electrically isolated from overlying conductors
(either metal or additional layers of polysilicon) by silicon dioxide• A native oxide of nanometre thickness grows on the silicon surface in a couple of hours or
days, depending on surface conditions, and similar thin oxides form easily in oxygenplasma or in oxidizing wet treatment.
• Deposited CVD oxides are used in some applications where low temperatures areabsolutely necessary, but superior silicon dioxides are grown in 800 to 1200 ◦C.
• Two basic schemes are used: wet and dry [email protected]
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Dry Oxidation vs wet Oxidation• Dry oxidation has a lower growth rate than wet oxidation although the oxide film quality is
better than the wet oxide film. Therefore thin oxides such as screen oxide, pad oxide, andespecially gate oxide normally use the dry oxidation process. Dry oxidation also results in ahigher density oxide than that achieved by wet oxide and so it has a higher breakdownvoltage.
• In case of wet oxidation where water is use instead of oxygen, the water molecule candissociate at high temperatures to form hydroxide OH that can diffuse in the silicon fasterthan molecular O2. Therefore the wet oxidation process has a significantly higher oxidationrate than the dry oxidation. It is used to grow thick oxides such as masking oxide, blanketfield oxide, and the LOCOS oxide.
The chemical reaction occurring at the silicon surface during dry oxidation is
Si + O2 → SiO2 -----------------DRY OXIDATION
And for wet oxidation is
Si + 2H2O → SiO2 + 2H2--------WET OXIDATION
• Thermal oxidation is a slow process: dry oxidation at 900 ◦C for 1 h produces 20nmthick oxide and wet oxidation for 1h produces 170nm.
• Exact values are dependent on silicon crystal orientation and doping:• Oxidation rate of <111> is somewhat higher than that of <100> silicon• Highly doped silicon oxidizes faster than lightly doped materia.
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1.2.4 Gettering• A material added in small amounts during a chemical or metallurgical process to
absorb impurities.• Gettering is the trapping of impurities either intrinsically inside the wafer or
extrinsically by a wafer backside layer.• Gettering collects impurities in known and designed regions, where they do not
interfere with device operation.• Gettering is incorporated in a few critical steps to reduce metal contamination.
1.2.4.1 Intrinsic gettering
• Intrinsic gettering refers to gettering that involves impurity trapping sites created byprecipitating supersaturated oxygen out of the silicon wafer.
• The precipitation of supersaturated oxygen creates clusters that continuously grow,• introducing stress to the wafer as this happens.
• These stresses reach the point where they need to be relieved.
• Dislocation loops or stacking faults are thus formed to provide the necessary stressrelief. These dislocations and faults subsequently serve as trapping sites forimpurities.
• A basic requirement of intrinsic gettering is, of course, starting wafers that havesufficient, but not excessive oxygen levels (15-19 ppm)[email protected]
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1.2.4.2 Extrinsic gettering• Extrinsic gettering refers to gettering that employs external means to create the damage
or stress in the silicon lattice in such a way that extended defects needed for trappingimpurities are formed.
• These chemically reactive trapping sites are usually located at the wafer backside.• introduction of mechanical damage:• The introduction of mechanical damage by abrasion, grooving or sandblasting, can
produce stresses at the backside of a wafer, which when annealed create dislocations thattend to relieve these stresses.
• These locations can then serve as gettering sites.• Drawback of this method, of course, is its tendency to initiate and propagate wafer
backside microcracks that may compromise the mechanical strength of the wafer.• Diffusion of phosphorous:• Diffusing phosphorus into the wafer backside is another technique used for external
gettering. P diffusion into silicon result in phosphorus vacancies or dislocations that serveas trapping sites for impurity atoms.
• Laser Gettering:• Introduction of damage by laser is another external gettering method.• Scanning a laser beam across the wafer surface induce damage that is very similar to
mechanical damage, with the exception that the laser damage is 'cleaner.'• Laser subjects the irradiated areas to thermal shock, forming dislocation nests that serve
as gettering sites.
Advantages of intrinsic gettering over extrinsicgettering are:
• 1) It does not require subjecting the wafer to any treatment except for heating;
• 2) Its volume of impurity sink (to a lower level ) is significantly larger than that of externalgettering on the wafer backside.
• 3) Its gettering regions are much closer to the device regions.
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1.2.5 Doping• Doping: introducing impurities into an extremely pure (also referred to as intrinsic)
semiconductor for the purpose of modulating its electrical properties.• There are two doping techniques:1. Diffusion and2. ion-implantation• Diffusion: The movement of one material through another.• Two conditions are necessary for a diffusion to take place:• First, one of the materials must be at a higher concentration than the other.• Second, there must be sufficient energy in the system for the higher concentration
material to move into or through the other.
1.2.6 Epitaxy (upon)• The term "epitaxial" is applied to a film grown over a crystalline substrate in such a way
that the atomic arrangement of the film bears a defined crystallographic relationship to theatomic arrangement of the substrate.
• Ordered layer deposition upon substrate, Epitaxy is the regularly oriented growth of onecrystalline substance upon another.
• The epitaxial process (crystal growth) substrate serves as the seed.• Epitaxy is performed at temperatures well below the melting point of either the film or
substrate.• Epitaxial layers are prepared by• Chemical Vapor Deposition (CVD). (Layers are commonly 1-20µm)• Molecular Beam Epitaxy (MBE)• (MBE), Widely used for compound semiconductors, (growing 2µm).
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1.2.6.1 Homoepitaxy and Heteroepitaxy• Homoepitaxy: When a material is grown epitaxially upon a substrate of the same material,
the process is called homoepitaxy.• Homoepitaxial takes place when the two materials have the same crystalline and chemical
structure.• It is easy to achieve high quality epitaxial layer it this category, because there are no lattice
miss match.• Example: Growth of silicon upon a silicon substrate.
• Heteroepitaxy: The layer is grown upon a chemically different substrate the process istermed heteroepitaxy.
• Heteroepitaxy involve different materials.• Strain can takes place due to lattice miss match elastically if the layer is thinner than a
certain critical thickness.• Example: Is the epitaxial deposition of silicon on sapphire (SOS). AlAs on GaAs, GaN on
SiC or SiGe on Si.
• Almost maximum epitaxy processes are hetroepitaxy.
1.2.6.2 Fundamental Aspects of Epitaxy (VPE process)• Epitaxial growth can be achieved from solid-phase, liquid-phase, vapor-phase, and
molecular-beam deposition.• For a Si epitaxy-layer, vapor-phase epitaxy.• Prior to the layer deposition, the growth system is purged by nitrogen or hydrogen for a
short period, and followed by a vapor HC1 etching.• The deposition process initiated by directing the reactant gases into the growth reactor.• The substrate is located and kept at a desired growth temperature, Tg.• Once the reactant gases are fed into the growth reactor, these chemical species undergo
a series of physical and chemical reactions, which result in the layer deposition.
• 1. Introduction of the reactant species tothe substrate region
• 2. Transfer of the reactant species to thesubstrate surface
• 3. Adsorption of the reactant species onthe substrate surface
• 4. Surface diffusion, site accommodation,chemical reaction, and layer deposition
• 5. Desorption of residual reactants and by-products
• 6. Transfer of residual reactants and by-products from the substrate surface
• 7. Removal of residual reactants and by-products from the substrate region
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1.2.6.3 Growth kinetics of epitaxy
1.2.6.4 Methods of Epitaxy• The most direct being the physical transport of material to the heated substrate.• Molecular beam epitaxy (vacuum evaporation): Principle is similar to evaporation. MBE
systems are operate at much high-vacuum environment.• Use: III-V (i.e., Al, Ga, In, As, P, and Sb) and mixed III-V (SiGe)• Vapor phase epitaxy: It is based on the transport of the epilayer constituent (Si, Ga, As,
dopants etc.) in the form of one or more volatile componants to the substrate.• This involves additional consideration associated with chemical reaction.• Example: Radical species produced during VPE can often be used to provide an inherent
substrate cleaning action.• VPE can to carried out at atmospheric pressure.• High quality material can be grown by this technique.• It is widely used for silicon (Si) and GaAs.• Chemical vapor deposition: The silicon and dopant atoms are brought to the single
crystal surface by gaseous transport.• Chemical vapor deposition is the formation of stable solids by decomposition of gaseous
chemicals using heat, plasma, ultraviolet, or other energy sources, or a combination ofsources.
• Liquid phase epitaxy (previously used methid): Many optoelectronic devices are stillfabricated using this process.
• in the approach most common to multilayer film growth a graphite holder slides a samplebetween melts of differing composition.
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1.3 Sputtering• Introduction:• Sputtering is a process whereby atoms are ejected from a solid target material due to
bombardment of the target by energetic particles. It is commonly used for thin-filmdeposition.
• It is more versatile than vacuum evaporation, because• Ability to deposit verity of metals, insulators and mixture of both.• Sputtering is driven by momentum exchange between the ions and atoms in the
materials, due to collisions.• When incident ion reach the target surface with an energy above the surface binding
energy, an atom can be ejected.
Physics behind sputtering• Sputter deposition is carried out in a self-sustained glow discharge which is created by the
breakdown of a heavy inert gas such as argon.• The physics of this process is:• Here, a d.c. electric field is impressed across two
electrodes which are located in this gas. At sufficientlylow electric field intensities, a very small current willflow, primarily by the transport of electrons betweenthese electrodes. These electrons may be produced byphotoemission or by cosmic ray stimuli, and are alwayspresent to some degree in any gaseous medium
• Transport of electrons between the electrodes will result in some collisions with the gasmolecules.
• so that ionization will occur in those encounters where a sufficiently large amount of energy istransferred to the gas.
• The products of these few ionizing collisions (namely, Ar and electrons) are themselvesaccelerated (in opposite directions) because of the electric field.
• It can also enter into collisions with neutral argon molecules, thus resulting in an avalanchemultiplication effect.
• At sufficiently high applied voltages, some of these Ar+ ions can eject secondary electrons fromthe cathode, thus adding to the supply of electrons which contribute to the avalanchemultiplication process. For this condition, Ar+ ions bombard the cathode resulting in sputteringof its surface material by momentum transfer. In addition, secondary electrons** emitted at thecathode participate in sustaining the discharge by ionizing collisions with argon molecules.
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1.4 Plasma enhanced CVD• Plasma enhancement is a extension of LPCVD, since system pressures for both techniques
are comparable. 11w principles underlying thc use and advantage of plasma processes forthe growth of native films hold for deposited films as well, Thus, the high elcctrontemperature allows growth at greatly reduced temperatures compared to those which arerequired for thermally activated processes.
• Growth at reduced temperature greatly expandsthe number of situations where deposited films canbe used. By way of example, Si3N4, grown at800—900’C by conventional CVD, cannot bedeposited on top of an aluminum metallization,which melts at 660°C. Plasma-grown nitride, at350oC.
• The rotating substrate electrode is grounded, withprovision for reactant feed at its center. Internalparts of the reactor are usually made of anodizedaluminum, so that they have a protective coating ofalumina. Substrate rotation is provided forimproving the uniformity of the grown layers.
Obviously the reduced deposition temperature is a bonus for the semiconductor industry which must worry about dopantdiffusion and metal interconnects melting at the temperatures required for thermal CVD. Also, the low pressures(between 0.1 - 10 Torr) required for sustaining a plasma result in surface kinetics controlling the reaction and thereforegreater film uniformity. A disadvantage of plasma CVD is that it is often difficult to control stoichiometry due to variationsin bond strengths of various precursors. For example, PECVD films of silicon nitride tend to be silicon rich because of therelative bond strength of N2 relative to the Si-H bond. Additionally, some films may be easily damaged by ionbombardment from the plasma.
1.6 Moores Law• The number of transistors on a chip roughly doubles every two years. As a result the scale
gets smaller and smaller. For decades, Intel has met this formidable challenge throughinvestments in technology and manufacturing resulting in the unparalleled silicon expertisethat has made Moore’s Law a reality.
Kurzweil speculates that it is likely that some new type of technology (e.g.optical, quantum computers, DNA computing) will replace current integrated-circuit technology, and that Moore's Law will hold true long after 2020.
Moore’s Law is the foundation forexciting new technological capabilitiesand improved energy efficiency. Theseimprovements integrate moretransistors on each chip to boostproductivity and performance whilecutting the cost per transistor inspiringsmarter, more adaptive technologiesthat optimize function integration atgreater speeds while reducing energyconsumption.
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90nm Technology
• The 90 nm process refers to the level ofCMOS process technology that was reachedin the 2002–2003 timeframe, by most leadingsemiconductor companies, like Intel, AMD,Infineon, Texas Instruments, IBM, and TSMC.
• Use of 300 mm wafer size• Use of 248 nm lithography with optical
proximity correction• 512 Mbit• 1.8 V operation
45nm technology• 160 nm gate pitch (73% of 65 nm generation)• 200 nm isolation pitch (91% of 65 nm generation) indicating a slowing of
scaling of isolation distance between transistors• Extensive use of dummy copper metal and dummy gates• 35 nm gate length (same as 65 nm generation)• 1 nm equivalent oxide thickness, with 0.7 nm transition layer• Gate-last process using dummy polysilicon and damascene metal gate• Squaring of gate ends using a second photoresist coating.• 9 layers of carbon-doped oxide and Cu interconnect, the last being a
thick "redistribution" layer.• Contacts shaped more like rectangles than circles for local
interconnection.• 1.36 mA/um nFET drive current• 1.07 mA/um pFET drive current, 51% faster than 65 nm generation, with
higher hole mobility due to increase from 23% to 30% Ge in embeddedSiGe.
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32nm• The test chips had a cell size of 0.182 μm2, used a
second-generation high-k gate dielectric and metalgate, and contained almost two billion transistors.193 nm immersion lithography was used for thecritical layers, while 193 nm or 248 nm drylithography was used on less critical layers. Thecritical pitch was 112.5 nm
• a 30 nm NAND Flash patterning process, using self-aligned double patterning. Starting from a 60 nmhalf-pitch pattern, new material was deposited andetched in between features to produce a 30 nm half-pitch pattern.
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Semiconductor Device Roadmap
• A semiconductor device roadmap is a plan that matches short-term and long-term goals withsemiconductor technology solutions to help meet those goals.
• It is a plan that applies to a new product or process, or to an emerging technology.• Developing a roadmap has three major uses.
• The Roadmap is based on the opinion ofindustrial experts.
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Roadmap for semiconductor• First the design rule will continue to follow the traditional rate of 40% reduction every 3
years.• However, the industry has not yet decided which lithography alternatives (e.g., deep
ultraviolet, projection electron beam, proximity X-ray, or extreme ultraviolet) will beadopted for future mass production.
• The design rule, of course, has a major impact on the gate length (usually slightly smallerthan the design rule), the minimum contact size (slightly larger than the design rule), theoxide thickness, and the supply voltage.
•Second for DRAM capacity, Figure shows theactual DRAM density versus the year of firstproduction from 1979 to 1999. The density for 2002to 2011 is based on the SIA Roadmap. It isinteresting to note that before 1999 the DRAMdensity almost exactly followed the Moore's law,25that is, it increased by a factor of 4 every 3 years (ordoubling every 18 months). However, in the next 10years, the density is expected to increase by afactor of 8 every 6 years or to double every 24months to reach 64 Gb in year 2011.
• Finally, for the clock frequency,
• For example, at a 0.1-ltm design rule, a CMOS inverter can have a speed of 10 ps per
gate, and a power dissipation of 1µW per gate, corresponding to a power dissipation delay
time product of only 10-17J.
• This is about 100 times smaller than a MODFET, and 1000 times smaller than a bipolar
logic circuit based on the same design rule.
• To increase the system speed, we also have to minimize the RC (resistance x capacitance)
delays due to parasitic resistance and capacitance.
• Low-dielectric-constant insulators should be used as interlayer materials.
• Copper is recommended as the metal material, and multilayer interconnection is
recommended to minimize the total wiring length.
• It is anticipated that in the early twenty-first century, 50% of the electronic systems will be
portable.
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1.9 Silicon on insulator• A monocrystalline Si film on amorphous SiO2 on a single crystalline Si substrate.
• Especially microelectronics, to reduce parasitic device capacitance and thereby improving
performance.
• Silicon-on-insulator (SOI) technology is used for the fabrication of radiation-hard circuits.
• In SOI the silicon junction is above an electrical insulator, typically silicon dioxide.
• The background idea is that in a bulk silicon MOS transistor, only a superficial layer
approximately 100-nm thick is actually useful for electron transport, whereas the substrate
causes undesirable effects.
• SOI wafers are primarily used for advanced CMOS applications
• Thicker Si and SiO2 films are needed for power and high voltage devices.
• This process helps reduce the amount of electrical charge that the transistor has to move
during a switching operation, thus making it faster and allowing it to switch using less
energy.
Importance of SOI• The inherent advantages of SOl devices over bulk CMOS are listed below:
• Very low junction capacitance
• The source and drain junction capacitance is almost entirely eliminted in SOI
MOSFETs. The capacitance through the thick buried oxide layer to the substrate is
very small.
• No body effect
• The threshold voltage of stacked devices in SOI not changed.
• Soft error immunity
• In bulk devices, minority carriers are generated along the track of any high-energy
particle or ionizing radiation that strikes through the silicon. If the collected charge of
a junction node exceeds a certain threshold, it may cause an upset of the stored logic
state. This is commonly referred to as a soft error. SOI devices offer a potential
improvement in the soft-error rate since the presence of the buried oxide greatly
reduces to ionizing radiation.
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Types of SOI MOSFET
• Partially depleted (PO) when the silicon film is thicker than the maximum gate
depletion width and the devices exhibit floating-body effect. (Like a bulk MOSFET)
• Fully depleted (FO) when the silicon film is thin enough that the entire film is depleted
before the threshold condition is reached.
Methods of making SOI wafers1. Smart Cut
• Smart Cut technology relies on transfer of a high quality layer from one wafer to another.
In typical applications, a thin layer of Si that is coated with thermal oxide is moved from its
original donor or seed wafer to another Si wafer that is coated with only native oxide.
• Step 1: The process sequence starts with oxidizing the donor wafer, followed by
implanting ions, typically hydrogen, through the oxide and into silicon.
• Step 2: Then the donor wafers and the handle wafers are very carefully cleaned to remove
any particles and to provide surface chemistry that is most favorable to wafer bonding.
• Step 3: Wafer pairs are properly positioned with respect to each other, lightly pressed
together and the fusion wave spreads and makes the wafers stick together.• Typically thermal energy provides a sufficient impetus for the split to occur, but mechanical
force is used in some cases instead of [email protected]
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Methods of making SOI wafers2. Bond and Etchback
• Bond and etchback SOI (BESOI) consists of bonding together of two oxidized and
properly cleaned silicon surfaces, followed by a combination of mechanical grinding
and chemical etching of a very significant fraction of one of the wafers in the two-
wafer sandwich.
• By its very nature, this process is useful when the final Si film should be ≥5 µm.
Methods of making SOI wafers3. ELTRAN (Epitaxial layer transfer)
• ELTRAN is based on wafer bonding.
• It utilizes a layer of porous Si formed by well-known electrochemical
processes as the weak zone that facilitates the transfer of a Si film from the
donor wafer to a new handle wafer.
• In this process, the top surface of the porous region has to be sealed by
thermal annealing in hydrogen to provide a template for epitaxial Si growth.
• After the epitaxy and oxide formation, wafer pairs are bonded, and then a
fine water jet is used to cut, Through the weak porous layer.
• Surface finishing steps complete the process.
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Methods of making SOI wafers4. Separation by implantation of oxygen
• SIMOX or separation by implantation of oxygen.
• This method relies on synthesis of BOX inside silicon by means of implanting a
sufficient density of oxygen ions under a superficial layer of crystalline Si.
• The main challenge is placing enough oxygen under the surface of Si, while
preserving the single crystalline nature of the superficial silicon.
• Temperatures of the order of 500oC–600oC during implantation prevent
amorphization of the superficial layer of silicon.
• Much higher annealing temperature, greater than 1300oC, subsequent to
implantation causes segregation of the implanted oxygen into a continuous buried
layer of SiO2.