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  • 7/29/2019 MOSFET CHARACTERISTICS

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    BASICS OF VLSI LAB-1 REPORT

    Submitted by,

    Richu Jose Cyriac (M120128EC)Davis Oommen Abraham (M120133EC)

    Aim1. To plot current-voltage characteristics of NMOSFET and PMOSFET.

    2. To measure MOS model parameters.

    1. CURRENT VOLTAGE CHARACTERISTICSCurrent-Voltage equations for the n-channel MOSFET

    0DI f o r TGS VV

    ])().(2[2

    )(2

    ...

    DSTGSoxn

    D VVVLWC

    linI

    fo r TGS VV an d TGSDS VVV

    for TGS VV and TGSDS VVV

    Current-Voltage equations for the p-channel MOSFET

    0DI f o r TGS VV

    ])().(2[2

    )( 2...

    DSTGSoxp

    D VVVLWC

    linI for TGS VV an d TGSDS VVV

    )1()(2

    )( 2... DSTGSoxpD VVVLWCsatI f o r TGS VV an d TGSDS VVV

    Figure 1.1 : Drain current vs gate voltage characteristics for NMOS and PMOS

    -1.00E-04

    -5.00E-05

    0.00E+00

    5.00E-05

    1.00E-04

    1.50E-04

    2.00E-04

    -2 -1 0 1 2

    Id(A),D

    rain

    current

    Vgs(V),Gate to source volt age

    NMOSVds=-1.8V

    Vds=-1.35V

    Vds=-0.9V

    Vds=-.45V

    Vds=0V

    Vds=1.80V

    Vds=1.35V

    Vds=0.90V

    Vds=0.45V

    Vds=0.00V

    PMOS

    )1()(2

    )( 2...

    DSTGSoxn

    D VVVLWC

    satI )1()(2

    )( 2...

    DSTGSoxn

    D VVVLWC

    satI

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    Figure 1.2: Drain current vs Drain to source voltage characteristics for NMOS and PMOS

    2. MOS MODEL PARAMETER EXTRACTION

    2.1THRESHOLD VOLTAGE TV

    Fig2.1: Gate to Source Voltage vs Drain current and its second derivative

    TV =478.74 mV

    -0.0001

    -0.00005

    0

    0.00005

    0.0001

    0.00015

    0.0002

    -2 -1.5 -1 -0.5 0 0 .5 1 1.5 2

    Id,D

    rain

    Current(A)

    Vds,Drain to source Voltage(V)

    Vgs=1.80

    Vgs=1.44V

    Vgs=1.08

    Vgs=0.72V

    Vgs=0.00V

    Vgs=-0.36V

    Vgs=-0.72V

    Vgs=-1.08V

    Vgs=-1.44V

    Vgs=-1.8V

    N M O SPM O S

    -5.00E-05

    0.00E+00

    5.00E-05

    1.00E-04

    1.50E-04

    2.00E-04

    2.50E-04

    3.00E-04

    3.50E-04

    4.00E-04

    4.50E-04

    0 0.5 1 1 .5 2

    Drain

    current(A)

    Vgs(V)

    Threshold Voltage

    second derivat ive

    Ids(A)

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    2.2 DRAIN-INDUCED BARRIER LOWERING

    THEORY

    A part of the region below gate is already depleted a smaller threshold suffices to cause strong inversion in short

    channel devices. By increasing the drain-source voltage the width of drain-junction depletion region increases

    consequently threshold decreases with increasing DSV .This effect is known as drain-induced barrier

    lowering(DIBL).

    It can be estimated asDS

    T

    V

    V

    Fig 2.2.: Gate to Source Voltage vs Drain current and its second derivative at differentvalues of Vds

    CALCULATIONS

    2THV =0.48V, 1THV =0.52V ,Vds2=1.8V,Vds1=1.0V, DIBL= -0.05

    -1.00E-04

    -5.00E-05

    0.00E+00

    5.00E-05

    1.00E-04

    1.50E-04

    2.00E-04

    2.50E-04

    3.00E-04

    3.50E-04

    4.00E-04

    4.50E-04

    0 0.5 1 1.5 2

    Id

    (A)

    Vgs(V)

    DIBL

    Vds =1.0V

    Vds =1.8V

    2n d

    der ivat iveat Vds=1.8V

    2n d

    der ivat iveat Vds=1.0V

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    2.3 EFFECT OF CHANNEL LENGTH MODULATION

    Figure 2.3: Drain current vs Drain to source voltage characteristics for NMOS at

    Vgs=1.8V

    THEORY

    If DSV is increased beyond )(satDSV the additional voltage applied to the drain appears across the end of the channel and

    drain region. This voltage accelerates the electrons that reach the drain end of the channel and sweeps them across the

    depletion region into drain. Channel length in effect is reduced since DI is inversely proportional to channel length

    current increases with DSV after )(satDSV

    1

    2

    1

    2

    1

    1

    )(

    )(

    DS

    DS

    satD

    satD

    V

    V

    I

    I

    CALCULATION

    Selecting values

    2DSV =1.8V and 1DSV =1.7V ,both greater than )(satDSV

    2)(satDI = 0.0001747 A and 1)(satDI = 0.0001731 A

    =0.109661

    V

    0

    0.00002

    0.00004

    0.00006

    0.000080.0001

    0.00012

    0.00014

    0.00016

    0.00018

    0.0002

    0 0.5 1 1.5 2

    Ids(A),D

    rain

    current

    Vds(V),Drain to Source Volt age

    Channe l length m odulat ion

    Vgs=1.8V

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    2.4 BODY EFFECT COEFFICIENT

    THEORY

    The effect of substrate bias is to widen the depletion region and raise the threshold voltage.

    CALCULATION

    0TV =478.74mV, TV =542.96M v, SBV =0.4V, typically F2 =0.8V

    =0.319 21

    V

    RESULTS AND INFERENCES

    1. The difference in amount of drain currents in NMOS and PMOS is due to the difference in electron hole

    mobility. For electron mobility is higher therefore NMOS structures provides higher currents.

    2. Threshold voltage at Vsb=0 is 478.74Mv.

    3. DIBL= -0.05V .As Vds increases threshold voltage lowers.

    4. = 0.10966 1

    V In saturation region current increases as Vds increases.

    5. =0.3192

    1

    V .As Vsb increases threshold voltage also increases

    -5.00E-05

    0.00E+00

    5.00E-05

    1.00E-04

    1.50E-04

    2.00E-04

    2.50E-04

    3.00E-04

    3.50E-04

    4.00E-04

    4.50E-04

    0 0.5 1 1.5 2

    Id(A)

    Vgs(V)

    Body effect coefficient secondder ivat iveat Vsb=0

    Ids(A) at

    Vsb=0

    second

    der ivat ive

    at Vsb=0.4V

    Ids at

    Vsb=0.4V

    )22(0 FSBFTT VVV

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