micromachined inductors and transformers for
TRANSCRIPT
MICROMACHINED INDUCTORS AND TRANSFORMERS FOR MINIATURIZEDPOWER CONVERTERS
By
CHRISTOPHER D. MEYER
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOLOF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2012
c© 2012 Christopher D. Meyer
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I dedicate this to my loving family.
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ACKNOWLEDGMENTS
I would like to thank everyone who has contributed to the success of the work
presented in my dissertation. I thank my adviser, Dr. David Arnold, who provided me
with the opportunity to work on exciting topics in power magnetics and who introduced
me to microfabrication at the University of Florida cleanroom. I thank Dr. Rizwan
Bashirullah who served on my committee and who is developing the very high frequency
power converter circuits that motivated my work. I thank Drs. Yong-Kyu Yoon and Peng
Jiang for their valuable insights while also serving on my committee. I thank Xue Lin
for testing my microinductor within his hybrid boost converter. I thank Christopher
Dougherty for enlightening me on the considerations that affect high frequency converter
designs. I thank Jessica Meloy for her help in wirebonding.
I thank the U.S. Army Research Laboratory (ARL) for funding the project and
my colleagues at ARL for their support. I thank Dr. Brian Morgan not only for leading
the Power for Microsystems project from which my research derived, but also for the
clarity he brought and for his mentoring me. I thank Dr. Sarah Bedair for countless
discussions and for her sage advice contributing to my growth both technically and
professionally. I thank Manrico Mirabelli for his microfabrication assistance and for
sharing his photolithography expertise. I thank James Mulcahy of the cleanroom staff for
maintaining and fixing the tools that were vital to this work. I thank William Benard for
heading the cleanroom and keeping it running smoothly.
I thank my grandfather, whose pride in me inspired me to complete my doctoral
degree. I thank my wife, Jennifer, for her steadfast love. Finally, I would like to thank my
parents for their continuous support and loving devotion.
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TABLE OF CONTENTS
page
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CHAPTER
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 The Case for Small . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.1.1 Distributed On-Chip Power for Microprocessors . . . . . . . . . . . 171.1.2 Mobile Autonomous Microsystems . . . . . . . . . . . . . . . . . . 18
1.2 Switched-Mode Power Converters . . . . . . . . . . . . . . . . . . . . . . 181.3 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.4 High Frequency Benefits and Challenges . . . . . . . . . . . . . . . . . . 221.5 Survey of Existing Microfabricated Inductors and Transformers . . . . . . 231.6 Air-Core Passive Components for Microscale Power Converters . . . . . . 24
2 BACKGROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 High Frequency Power Converters . . . . . . . . . . . . . . . . . . . . . . 272.2 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.3 Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 INDUCTOR DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1 Quality Factor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.1.1 Quality Factor of Non-Ideal Reactive Components . . . . . . . . . 353.1.2 Quality Factor of Inductor . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Performance Trilemma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.3 Stacked Planar Spiral Layout . . . . . . . . . . . . . . . . . . . . . . . . . 393.4 Low Frequency Analytical Inductor Model . . . . . . . . . . . . . . . . . . 403.5 Trends and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.5.1 Analytical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.5.2 FastHenry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6 Radio Frequency Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473.6.1 Capacitive Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . 473.6.2 Eddy Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.7 Summary of Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . 57
5
4 TRANSFORMER DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1 Overview and Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.2 Maximum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.1 From Scattering Parameters . . . . . . . . . . . . . . . . . . . . . . 604.2.2 From Coil Quality Factors and Coupling Coefficient . . . . . . . . . 61
4.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.3.1 Turns Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4 Performance Under Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.4.1 Derivation of Efficiency and Voltage Gain for Arbitrary Load . . . . 664.4.2 Conjugate Impedance Matched Loading . . . . . . . . . . . . . . . 69
4.5 Summary of Transformer Design . . . . . . . . . . . . . . . . . . . . . . . 70
5 FABRICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.1 Process Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.1.1 Sequential Layer Removal . . . . . . . . . . . . . . . . . . . . . . . 735.1.2 Ultrasonic Agitation in Solvents . . . . . . . . . . . . . . . . . . . . 74
5.2 Features and Variations on the Process . . . . . . . . . . . . . . . . . . . 765.2.1 Planar Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.2.2 Photoresist as a Structural Element . . . . . . . . . . . . . . . . . . 785.2.3 Substrate Versatility . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3 Process Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795.4 Special Processing Considerations . . . . . . . . . . . . . . . . . . . . . . 82
5.4.1 Sputtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.4.2 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855.4.3 Electroplating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.4.4 Argon Sputter Etch . . . . . . . . . . . . . . . . . . . . . . . . . . . 895.4.5 Photoresist Skin Removal . . . . . . . . . . . . . . . . . . . . . . . 905.4.6 Copper Seed Etch . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6 INDUCTOR CHARACTERIZATION . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.1 Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936.2 Inductor Characterization Methods . . . . . . . . . . . . . . . . . . . . . . 94
6.2.1 One-Port Inductor Methods . . . . . . . . . . . . . . . . . . . . . . 946.2.2 Two-Port Inductor Methods . . . . . . . . . . . . . . . . . . . . . . 956.2.3 Inductor Characteristics Obtained from Impedance . . . . . . . . . 97
6.3 One-Port Inductor Characterization . . . . . . . . . . . . . . . . . . . . . . 986.3.1 One-Port Inductors on Pyrex Substrates . . . . . . . . . . . . . . . 98
6.3.1.1 Comparison to model predictions . . . . . . . . . . . . . . 1016.3.1.2 Current rating . . . . . . . . . . . . . . . . . . . . . . . . 1016.3.1.3 Interwinding capacitance . . . . . . . . . . . . . . . . . . 102
6.3.2 One-Port Inductors on Silicon Substrates . . . . . . . . . . . . . . 1056.3.2.1 Copper layer thickness: 10 ”m vs. 30 ”m . . . . . . . . . 1056.3.2.2 Inductor shape: square vs. circular spirals . . . . . . . . 106
6
6.4 Two-Port Inductor Characterization on Silicon Substrates . . . . . . . . . 1106.4.1 Capacitive Coupling through the Substrate . . . . . . . . . . . . . . 1106.4.2 Winding Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.5 Summary of Inductor Characterization . . . . . . . . . . . . . . . . . . . . 118
7 TRANSFORMER CHARACTERIZATION . . . . . . . . . . . . . . . . . . . . . 119
7.1 Equipment and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197.2 Impedance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207.3 Load-Dependent Efficiency and Voltage Gain . . . . . . . . . . . . . . . . 1227.4 Characterization of Transformers with 10 ”m Thick Layers . . . . . . . . . 124
7.4.1 Extraction of Nominal Inductances and Resistances . . . . . . . . 1257.4.2 Load-Dependent Performance of 1 : 1 Transformer . . . . . . . . . 1277.4.3 Load-Dependent Performance of 1 : 3.5 Transformer . . . . . . . . 131
7.5 Characterization of Transformer with 30 ”m Thick Layers . . . . . . . . . . 1357.6 Summary of Transformer Characterization . . . . . . . . . . . . . . . . . . 140
8 PACKAGING AND TESTING WITH CIRCUITS . . . . . . . . . . . . . . . . . . 142
8.1 Microinductor Wire Bonded to Very High Frequency Boost Converter . . . 1428.1.1 About the Microinductor . . . . . . . . . . . . . . . . . . . . . . . . 1428.1.2 About the Converter and Test Results . . . . . . . . . . . . . . . . 143
8.2 Testing with Commercial Surface-Mount Converter . . . . . . . . . . . . . 1458.2.1 About the Texas Instruments TPS61240 Converter . . . . . . . . . 1468.2.2 Module Design and Processing . . . . . . . . . . . . . . . . . . . . 1468.2.3 Converter Module Testing . . . . . . . . . . . . . . . . . . . . . . . 149
8.3 Summary of Inductor Packaging and Testing within Converter Circuits . . 154
9 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
9.1 Summary of Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579.2 Lessons Learned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
BIOGRAPHICAL SKETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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LIST OF TABLES
Table page
2-1 Literature survey of microinductors . . . . . . . . . . . . . . . . . . . . . . . . . 33
2-2 Literature survey of microtransformers . . . . . . . . . . . . . . . . . . . . . . . 34
3-1 Coefficients for modified Wheeler and current sheet expressions . . . . . . . . 41
5-1 Process parameters for passives fabrication . . . . . . . . . . . . . . . . . . . . 81
5-2 Recipe for acid copper sulfate electroplating bath . . . . . . . . . . . . . . . . . 88
6-1 Comparison of measured inductor performance . . . . . . . . . . . . . . . . . . 99
6-2 Comparison of model-predicted to measured inductor performance . . . . . . . 100
6-3 Performance comparison of inductors with different layer thicknesses . . . . . . 106
6-4 Geometric parameters of square and circular inductors . . . . . . . . . . . . . 107
6-5 Performance comparison of square and circular inductors . . . . . . . . . . . . 107
7-1 Comparison of transformer circuit parameters . . . . . . . . . . . . . . . . . . . 126
8-1 Component sizes in functional converter module . . . . . . . . . . . . . . . . . 149
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LIST OF FIGURES
Figure page
1-1 Common converter circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1-2 Review of microinductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1-3 Review of microtransformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3-1 Circuit diagram of simple inductor model . . . . . . . . . . . . . . . . . . . . . . 39
3-2 Diagram of spiral dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3-3 Trends of inductance to resistance ratio vs. packing density . . . . . . . . . . . 45
3-4 Trends of inductance to resistance ratio vs. outer diameter . . . . . . . . . . . 46
3-5 Trend of inductance vs. vertical gap between stack simulated in FastHenry . . 46
3-6 Diagram of capacitive coupling of traces through substrate . . . . . . . . . . . 49
3-7 Circuit model of inductor with substrate capacitance . . . . . . . . . . . . . . . 49
3-8 Substrate resistance effect on inductor impedance . . . . . . . . . . . . . . . . 50
3-9 Circuit model of inductor with winding and substrate capacitances . . . . . . . 51
3-10 Substrate vs. winding capacitance effect on inductor impedance . . . . . . . . 52
3-11 COMSOL simulations of skin effect in winding cross sections . . . . . . . . . . 55
3-12 Measured effect of eddy currents on inductor impedance . . . . . . . . . . . . 57
4-1 Transformer energy flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4-2 Transformer efficiency calculated by quality factors and scattering parameters . 64
4-3 Transformer layout winding diagram . . . . . . . . . . . . . . . . . . . . . . . . 65
4-4 Circuit diagram of two-port network cascaded with shunt load . . . . . . . . . . 67
4-5 Circuit diagram of two-port network cascaded with series load . . . . . . . . . . 68
4-6 Circuit diagram of two-port network with source and load impedances . . . . . 69
5-1 Illustrations of additive process stage . . . . . . . . . . . . . . . . . . . . . . . . 74
5-2 Illustrations of subtractive process stage . . . . . . . . . . . . . . . . . . . . . . 75
5-3 Scanning electron micrograph (SEM) of inductor with 10 ”m thick layers . . . . 75
5-4 SEM of inductor with 30 ”m thick layers . . . . . . . . . . . . . . . . . . . . . . 76
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5-5 Cross section diagrams of process additive stage . . . . . . . . . . . . . . . . . 83
5-6 Cross section diagrams of process subtractive stage . . . . . . . . . . . . . . . 84
5-7 Adhesion of copper to photoresist . . . . . . . . . . . . . . . . . . . . . . . . . 85
5-8 Electroplating leakage between features . . . . . . . . . . . . . . . . . . . . . . 86
5-9 Electroplated copper cantilever . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5-10 Comparison images showing argon sputter etch effect on adhesion . . . . . . . 90
5-11 Photoresist blocking layer formed by argon sputter etch . . . . . . . . . . . . . 91
5-12 Sidewall roughening caused by copper etch . . . . . . . . . . . . . . . . . . . . 92
6-1 SEM images of one-port and two-port inductors . . . . . . . . . . . . . . . . . . 94
6-2 Two-port inductor impedance network . . . . . . . . . . . . . . . . . . . . . . . 95
6-3 Identification of inductor specifications from plots . . . . . . . . . . . . . . . . . 99
6-4 Current rating of inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6-5 Comparison images of interlayer photoresist . . . . . . . . . . . . . . . . . . . 103
6-6 Comparison of interlayer dielectric effect on impedance of small inductor . . . . 104
6-7 Comparison of interlayer dielectric effect on impedance of large inductor . . . . 104
6-8 Comparison of layer thicknesses for small inductor . . . . . . . . . . . . . . . . 108
6-9 Comparison of layer thicknesses for large inductor . . . . . . . . . . . . . . . . 108
6-10 Comparison of shape of small inductor . . . . . . . . . . . . . . . . . . . . . . . 109
6-11 Comparison of shape of large inductor . . . . . . . . . . . . . . . . . . . . . . . 109
6-12 Pad capacitance diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6-13 Shunt capacitance at two ports of inductor . . . . . . . . . . . . . . . . . . . . . 115
6-14 Impedance plots from two-port inductor . . . . . . . . . . . . . . . . . . . . . . 115
6-15 SEM images of inductors with solid vs. filamented traces . . . . . . . . . . . . 116
6-16 SEM images of solid vs. filamented traces . . . . . . . . . . . . . . . . . . . . . 116
6-17 Impedance plots of filamented vs. solid traces . . . . . . . . . . . . . . . . . . 117
6-18 Change in resistance due to filamented vs. solid traces . . . . . . . . . . . . . 117
7-1 Circuit representation of two-port impedance parameters . . . . . . . . . . . . 121
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7-2 Low frequency transformer model . . . . . . . . . . . . . . . . . . . . . . . . . 122
7-3 SEM images of microfabricated transformers . . . . . . . . . . . . . . . . . . . 125
7-4 Impedance plots of 1 : 1 transformer with 10 ”m thick layers . . . . . . . . . . . 126
7-5 Impedance plots of 1 : 3.5 transformer with 10 ”m thick layers . . . . . . . . . . 127
7-6 Efficiency of 1 : 1 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7-7 Voltage gain of 1 : 1 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7-8 Magnitude and phase of matched load impedance for 1 : 1 transformer . . . . . 129
7-9 Efficiency and voltage gain vs. load impedance for 1 : 1 transformer . . . . . . 130
7-10 Efficiency of 1 : 3.5 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7-11 Voltage gain of 1 : 3.5 transformer . . . . . . . . . . . . . . . . . . . . . . . . . 132
7-12 Magnitude and phase of matched load impedance for 1 : 3.5 transformer . . . 133
7-13 Efficiency and voltage gain vs. load impedance for 1 : 3.5 transformer . . . . . 134
7-14 SEM image of microtransformer with 30 ”m thick layers . . . . . . . . . . . . . 136
7-15 Impedance plots of 1 : 1 transformer with 30 ”m thick layers . . . . . . . . . . . 137
7-16 Efficiency of thicker 1 : 1 transformer . . . . . . . . . . . . . . . . . . . . . . . . 138
7-17 Voltage gain of thicker 1 : 1 transformer . . . . . . . . . . . . . . . . . . . . . . 138
7-18 Magnitude and phase of matched load impedance for thicker 1 : 1 transformer 139
7-19 Efficiency and voltage gain vs. load impedance for thicker 1 : 1 transformer . . 141
8-1 Microinductor wire bonded to circuit for testing . . . . . . . . . . . . . . . . . . 143
8-2 Impedance of wire bonded inductor . . . . . . . . . . . . . . . . . . . . . . . . 144
8-3 Measured efficiencies of converter with wire bonded microinductor . . . . . . . 145
8-4 Copper layout of converter module . . . . . . . . . . . . . . . . . . . . . . . . . 147
8-5 Photograph of released copper framework . . . . . . . . . . . . . . . . . . . . . 148
8-6 Photographs of functional converter module . . . . . . . . . . . . . . . . . . . . 149
8-7 Impedance of inductor used in converter module . . . . . . . . . . . . . . . . . 151
8-8 Measured efficiency vs. output current of converter module . . . . . . . . . . . 152
8-9 Boost converter circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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8-10 Inductor voltage waveform for several input voltages . . . . . . . . . . . . . . . 153
8-11 Waveforms of inductor voltage for different load currents . . . . . . . . . . . . . 155
8-12 Waveforms of output voltage for different load currents . . . . . . . . . . . . . . 155
9-1 Review of microinductors including new results . . . . . . . . . . . . . . . . . . 159
9-2 Review of microtransformers including new results . . . . . . . . . . . . . . . . 159
9-3 Illustrations of package assembly . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9-4 SEM images of copper sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
9-5 SEM images of teeth contacting to surface-mount component . . . . . . . . . . 163
9-6 Surface-mount resistor and capacitor alongside microinductors . . . . . . . . . 164
9-7 Measured impedances of socketed resistor and capacitor . . . . . . . . . . . . 165
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Abstract of Dissertation Presented to the Graduate Schoolof the University of Florida in Partial Fulfillment of theRequirements for the Degree of Doctor of Philosophy
MICROMACHINED INDUCTORS AND TRANSFORMERS FOR MINIATURIZEDPOWER CONVERTERS
By
Christopher D. Meyer
May 2012
Chair: David P. ArnoldMajor: Electrical and Computer Engineering
Switched-mode dc-dc power converters are a ubiquitous part of modern, feature-rich
portable electronic devices and are essential for efficiently transferring electrical energy
out of battery sources and into various power-hungry loads, such as microprocessors,
displays, sensors, and communications systems. These converters often comprise
a significant portion of total system size/weight, and the largest offenders are often
the associated power inductors and transformers. A significant reduction in the size
the inductors and transformers would have a transformative effect in enabling new
applications, such as mobile autonomous microsystems.
Increasing the switching frequency of the power converters offers to reduce the
values of the required passives. However, the expected switching frequencies of
next generation power converters fall into a gap between magnetic film inductors
and transformers operable at < 10 MHz and microwave air-core devices with high
performance at > 1 GHz. In answer, a new class of air-core microinductors and
microtransformers is presented in this document that leveraged microfabrication-enabled
advancements to attain high performance in the desirable very high frequency (VHF)
switching range and to enable fully integrated power management systems in the
smallest possible packages.
In order to design these devices, models were analyzed to uncover the ideal
characteristics for operating in the VHF range. Compared to traditional air-core
13
components, these new ones featured thicker windings and had more intricate windings
for lower loss and higher density. A multilevel microfabrication process was developed
for molding three-dimensional (3D) copper parts with the necessary characteristics of
thickness, minimum feature size, and out-of-plane stacking.
The 3D copper process enabled the microfabrication of inductors with measured
inductance densities up to 170 nH/mm2 and quality factors as great as 33. Transformers
were measured with even greater inductance densities: up to 325 nH/mm2 was
obtained in a configuration for voltage gain of 3.5 with up to 78% efficiency. Performance
figures for both inductors and transformers were shown to outstrip a number of other
microfabricated examples found in the literature, particularly in the frequency range of
10 MHzâ1 GHz.
Microfabricated inductors were tested within the circuits of both a prototype
100 MHz switched-mode hybrid boost converter and a commercially-available surface-mount
converter with up to 4 MHz switching frequency. With up to 37% efficiency at a
conversion ratio of 6, the performance of the prototype 100 MHz converter when using
a 14 nH microfabricated inductor largely matched that obtained when a larger 43 nH
surface-mount inductor was used in the same converter at up to 1 mA load current.
A packaging solution was devised for testing with the surface-mount converter. An
embedded multilevel copper module consisting of both an inductor and interconnects
was detached from its silicon fabrication substrate and served as a platform to which a
surface-mount converter and capacitors were soldered.
14
CHAPTER 1INTRODUCTION
Switched-mode dc-dc power converters are a ubiquitous part of modern, feature-rich
portable electronic devices. These power converters are essential for efficiently
transferring electrical energy out of battery sources and into various power-hungry
loads, such as microprocessors, displays, sensors, and communications systems.
The need for power converters arises from the fact that electricity is utilized in
many different forms even within a single system. Often each subsystem has a different
expectation for electrical current (the ârateâ), voltage (the âforceâ), and duty cycle (the
on/off times). Loads may operate erratically or not at all if the source is incapable of
delivering enough electrical current, at a given voltage level, and for a certain amount of
time. Batteries are designed to provide current at a fixed voltage, which may not match
the needs of the loads. The battery voltage also often decreases with higher current
draws or with time as its energy storage is depleted. Power converters provide the
handshaking that is necessary for the sources and loads to interoperate with each other.
One basic role of the dc-dc switched-mode power converter is to accept electrical
power that is input to it at one voltage level and output that power at a different voltage
level. Intelligent control mechanisms within the converter can respond to fluctuations in
source and load conditions to help smooth the delivery of power and prevent levels from
falling out of specification.
Although the term âdcâ implies that the input and output voltages of the dc-dc
converter are ideally constant to the outside world, inside the converter are switches
that dynamically reconfigure the electrical current paths of the converter circuit many
thousands to millions of times per second. Power conversion utilizes the reactions of
inductors and transformers to the switch-induced changes in electrical current within
the converter to raise or lower the voltage to desired levels. Such inductive components
possess the characteristic of inducing a voltage difference to resist changes in the level
15
of current passing through them. The fundamental equation describing this behavior is
vL(t) = Ldi
dt, (1â1)
where vL(t) is the voltage induced across the inductor, di/dt is the change in current
through it, and the ratio L is defined as the inductance, measured in henries (H). For an
electrical current initially at 0 and rising to a level I , the energy E stored in the inductor is
E =1
2LI 2. (1â2)
Inductance is generally proportional to the area enclosed by a coiled conductor.
Because physical volume and mass are placed at a premium in portable electronics
applications, small inductors are desired but have correspondingly small inductances.
The inductors and transformers must, for the sake of efficiency however, store enough
energy per switching cycle to overshadow the power lost during conversion. As a result,
the inductive components can comprise a major portion of the entire converter system
size and mass, especially when the rest of the converter circuit is integrated onto a
single, tiny semiconductor chip with nm-scale transistors.
The large inductive components are, due to their size, generally added as discrete
components connected outside the converter package. External connections further
add to the bulk of the system as each component requires its own packaging, pads,
and solder joints. A significant size and weight savings would be obtained if the
inductors and transformers could be integrated with the rest of the converter circuit
within the same package. Bulky external connections could be replaced by much leaner
wire bonds, embedded interconnects, or flip-chip bumps via a System-in-Package
(SiP) approach. Further size savings would be obtained through the System-on-Chip
(SoC) approach of monolithically fabricating inductors and transformers directly on the
integrated circuits chip.
16
To realize these SiP or SoC concepts for power converters, inductive components
must first decrease in size to the point where integration is not cost-prohibitive. One
route to decreasing the inductor/transformer size is to increase the switching frequency
of the converter, so that the current variations, di/dt, are greater and occur more often.
The other means of reducing size is to increase the inductance density of the inductors
and transformers.
The inductors and transformers presented in this document leverage microfabrication
technologies for increased density and are designed to operate at increased frequencies
that have been emerged from innovative integrated-circuit converters. The goal of this
work is to enable fully-integrated high-frequency switched-mode dc-dc power converters
with ultra-miniaturized, high-density inductors and transformers.
1.1 The Case for Small
From the advent of the integrated circuit in the 1950s up to the present day,
electronic systems have been continually packed into rapidly shrinking devices with
ever-greater processing power. Contemporary consumer electronics are marked
by examples of portable computers, mobile phones, and media players in svelte
forms with increasingly convergent functionality. The need for fully integrated power
converters is reaching a critical point, however, as the scaling of power components
has struggled to keep pace with that of data processing and storage. But beyond just
the consumer-driven aesthetic of small for the sake of small, a significant reduction in
the size of power subsystems could also have a transformative effect in enabling new
applications, like mobile autonomous microsystems, and in improving the distribution of
power, such as for microprocessors.
1.1.1 Distributed On-Chip Power for Microprocessors
Modern microprocessors are highly parallel in operation. Facing the upper limits
of using higher clock frequencies to process data quicker, designers have leveraged
the benefits of a continually-shrinking transistor size and are integrating multiple
17
microprocessor copies, or cores, on a single chip. The cores are able to process
data in parallel, but have a tendency to be under-utilized in situations where tasks
require serial processing. Although todays microprocessors receive power that is
supplied by a converter located outside the microprocessor package, the ability to
integrate many power converters on the chip itself could enable individual portions of
the microprocessor circuit to be rapidly turned on and off as needed, reducing power
consumption and increasing the thermal budget of the active portions. On-die power
converters would additionally reduce the complexity of utilizing independent voltage
levels for portions of the microprocessor operating at different frequencies for further
reductions in power consumption [1, 2].
1.1.2 Mobile Autonomous Microsystems
An emerging research effort is focused at developing mobile autonomous
microsystems, tiny robotic devices that can navigate through their environment by
flying, crawling, or hopping. The number and complexity of subsystems envisioned for
these mobile microsystems is staggering. In addition to the actuators for locomotion,
these manmade bugs are expected to contain sensors for situational awareness, logic
blocks for data processing, communications systems for relaying information, and
possibly generators for harvesting energy from the environment. Interoperation of these
subsystems is likely to be a challenge as each is likely to require operation at unique
voltages, currents, and duty cycles for best performance, and will require an advanced
power management system that must furthermore be vanishingly small and light so as
to not interfere with the mobility of the bug [3].
1.2 Switched-Mode Power Converters
A multitude of circuit topologies exist to achieve switched-mode power conversion.
Some provide a step-up from lower input voltage to a higher output voltage, and some
provide a step-down. Some are capable of providing either step-up or step-down
on-the-fly, while others have input and output voltages that are equal to one another but
18
provide isolation to protect the output from high voltage spikes that may occur on the
input side of the circuit. Common switched-mode converter topologies include the boost,
buck, buck-boost, and flyback circuits.
The basic boost converter is drawn in Figure 1-1A. Current flows through the
inductor L when switch Q is closed, and energy is stored in the magnetic field of the
inductor. When Q is opened, a voltage is induced across the inductor to oppose any
sudden reduction in current, pushing current through diode D, onto the output capacitor
C , and out to the load R. The voltage induced across the inductor in this last step is
negative with respect to the reference for vL(t) labelled on Figure 1-1A, meaning that the
voltage across the load is greater than the input voltage Vin. The role of the capacitor C
is to store charge between switching cycles and ensure that the output voltage remains
at a relatively steady value. The conversion ratio M for the boost converter is controlled
by the duty cycle of the switch in its closed position, as plotted in Figure 1-1B. When the
switch is closed for a longer portion of the cycle than it is closed, the conversion ratio of
the converter is larger.
The buck (Figure 1-1C) and buck-boost (Figure 1-1E) circuits operate similarly in
that transient current through charged inductors induce voltages across the inductors
that are utilized to create voltage differences with respect to the input. The duty cycle of
the switch-closed time again provides modulation of the output voltage. As per Figure
1-1D the buck circuit is able to provide an output voltage that is less than the input, while
the buck-boost provides an inverted voltage that can range in magnitude from levels that
are both greater and lesser than the input (Figure 1-1F).
The flyback converter of Figure 1-1G derives from the buck-boost converter, except
that the inductor of the buck-boost is replaced by an isolating transformer. The switch
in Figure 1-1G is positioned for non-inverting output, so the conversion ratio plotted in
Figure 1-1H for a 1 : 1 transformer is the same as that of the buck-boost but opposite in
polarity. A step-up transformer with non-unity gain may be utilized in this circuit to realize
19
+â
+ vL(t) -
L
Q
D
C R
+
Vout-
Vin
A Boost converter circuit
0 0.25 0.5 0.75 10
1
2
3
4
5
Con
vers
ion
Rat
io M
(V
/V)
Duty Cycle D
B Boost conversion ratio
+â
LQ
D C R
+
Vout-
Vin
C Buck converter circuit
0 0.25 0.5 0.75 10
0.5
1
Con
vers
ion
Rat
io M
(V
/V)
Duty Cycle D
D Buck conversion ratio
+â L
Q D
C R
+
Vout-
Vin
E Buck-boost converter circuit
0 0.25 0.5 0.75 1â5
â4
â3
â2
â1
0
Con
vers
ion
Rat
io M
(V
/V)
Duty Cycle D
F Buck-boost conversion ratio
+â
Q
D
C R
+
Vout-Vin
1 : n
G Flyback converter circuit
0 0.25 0.5 0.75 10
1
2
3
4
5
Con
vers
ion
Rat
io M
(V
/V)
Duty Cycle D
H Flyback conversion ratio
Figure 1-1. Common converter circuits and their idealized conversion ratios M asfunctions of switching duty cycle D. Figures adapted from Erickson andMaksimovic [4].
20
more drastic conversion ratios than would be had from the buck-boost. The transformer
additionally provides isolation protection between input and output.
1.3 Impedance
While Equation 1â1 describes the characteristic transient behavior of inductive
components in inducing voltages in opposition to changes in the current passing through
it, an impedance analysis is useful for characterizing the behavior of an inductor when
the changes are sinusoidal or periodic. The impedance Z of an inductor relates the
voltage V across the inductor to the current I passing through it
Z =V
I, (1â3)
where both voltage and current are sinusoidally varying. Other non-sinusoidal periodic
excitations can be considered using Fourier analysis to decompose the signal into a
summation of sinusoidal signals.
When determining impedance, the voltage and current waveforms are represented
by phasors, each being a vector with magnitude equal to the amplitude of the waveform
and with angle equal to the phase difference between the waveform and some common
reference. In complex form, the real part of the impedance represents the in-phase
energy-dissipative (resistive) component and the imaginary part represents the
out-of-phase energy-storage component. The impedance of an ideal inductor with
inductance L at an angular frequency of Ï is,
ZL = jÏL. (1â4)
While the current through an ideal inductor lags the voltage across it by 90 (a quarter
wavelength), resistive and capacitive effects cause frequency-dependent magnitude and
phase relationships.
21
1.4 High Frequency Benefits and Challenges
Because the impedance of an ideal inductor scales with frequency, power
converters with higher switching frequencies can utilize lower-valued and physically
smaller inductors. However, increasing to very high frequency (VHF) switching
(> 10 MHz) also introduces several challenges that could severely limit performance of
these converters if not addressed.
Many magnetic core materials, which are used to increase magnetic induction in
inductors/transformers, are unable to physically switch their magnetization fast enough
in response to a VHF applied field. The time lag between changes in the applied field
and the responding change in magnetic induction in the material leads to power losses
in the core. Designers often utilize magnetic material anisotropy (or sometimes a dc bias
magnetic field) perpendicular to the applied magnetic field in order to improve the high
frequency response time of magnetic materials at the expense of lower permeability [5].
Eddy current generation within electrically conductive materials results in the skin
effect, the confinement of electric and magnetic fields to the materialsâ surface at high
frequency excitation. The skin effect limits the effective cross sectional area of both
the electric winding and the magnetic core, leading to greater resistance and lesser
inductance.
In the VHF switching range, the converter circuit design demands components with
inductance and capacitance values that are on the order of the unintended parasitic
inductances and capacitances that inherently occur between components and in the
interconnections between them [6]. The design of the inductors and transformers must
consider the large parasitic capacitance experienced as energy is stored in the electric
field between adjacent conductor traces. This parasitic capacitance limits the maximum
operating frequency and efficiency of the inductor/transformer.
22
1.5 Survey of Existing Microfabricated Inductors and Trans formers
Gardner et al. [7] published in late 2009 a comprehensive review of contemporary
on-chip inductors with magnetic films and evaluated their application to integrated
power converters. The review reached some interesting conclusions. A majority of
the works featured inductors with inductance densities of less than 100 nH/mm2,
calling into question whether the magnetic films are providing sufficient inductance
improvement to warrant their inclusion. Additionally, few results were applicable to high
frequency switching (> 100 MHz). The review identified quality factor as performance
parameter of interest for efficient power conversion, with quality factor of 1 as the
minimum below which inductors acted more like resistors than as intended as energy
storing components [7]. Air-core microinductors, on the other hand, have mostly been
designed for GHz radio frequency (RF) applications. Such devices can attain high quality
factors when suspended above conductive substrates but typically have low inductances
on the order of only several nH.
Ahn, NiFe
Yamaguchi, FeAlO
Sato, FeCoBN
Song, FeZrBAg
Fukuda, NiZn
Wang, NiFe Viala, FeHfN
Flynn, NiFe
Orlando, NiFe
Lee, CoTaZr
Park, Air
Young, Air
Choi, Air
Weon, Air Yoon, Air
1
10
100
1 10 100 1000 10000
Pe
ak
Qu
ali
ty F
ac
tor
Frequency for Peak Quality Factor (MHz)
Figure 1-2. Review of both magnetic-film (shaded in blue) and air-core (shaded in green)microinductors with each plotted in terms of peak quality factor and thefrequency at which the peak quality factor was obtained. Bubble size isproportional to inductance density.[8â22]
23
A survey of existing microinductors, including both magnetic film and air cores,
revealed that there was a significant gap where few microfabricated inductors were
designed for frequencies ranging from tens of MHz up to 1 GHz. The gap was evident
in Figure 1-2, where a number of microinductors were plotted against their peak quality
factor and the frequency at which the peak quality factor was attained. A typical
magnetic film microinductor had an inductance density of about 55 nH/mm2, almost
twice that of the typical air core counterpart, which had about 30 nH/mm2. The situation
was reversed for the peak quality factor where the median air core inductor had a peak
quality factor of 50, far greater than the median magnetic film inductor at a quality factor
of 9.
A similar frequency gap was found amongst the results gathered from works
reporting existing microtransformers as can be seen on the plot in Figure 1-3. Both
magnetic film and air core microfabricated inductors were plotted against maximum
efficiency of power transfer through the transformer and the frequency at which
the maximum efficiency occurred. Most of the works were found to focus only on
transformers with 1 : 1 turns ratios with near-unity voltage/current gain.
1.6 Air-Core Passive Components for Microscale Power Conve rters
Between magnetic-film-core devices operable at < 10 MHz and microwave RF
air-core devices with high performance at > 1 GHz lies a large frequency gap amongst
the reported microinductors and microtransformers. Coincidentally, the expected
switching frequencies of next generation power converters fall right into this gap for
which no inductor/transformer technology can yet claim championship. However,
the development is presented here for a new class of air-core microinductors and
microtransformers that leverage microfabrication-enabled advancements to attain high
performance in this desirable switching frequency range and to enable fully integrated
power management systems in the smallest possible packages.
24
Yamaguchi, Air
Laney, Air
Zolfaghari, Air
Ng, Air Aly, Air
Mino, CoZrRe
Kurata, CoFeSiB
Yamaguchi, CoNbZr
Mino, CoZrRe
Xu, NiFe
Sullivan, NiFe
Sullivan, NiFe
Brunet, NiFe
Park, NiFe
Rassel, NiFe
Yun, NiFe
Wang, NiFe
0%
20%
40%
60%
80%
100%
1 10 100 1000 10000
Eff
icie
nc
y
Frequency for Maximum Efficiency
Figure 1-3. Review of both magnetic-film (shaded in blue) and air-core (shaded in green)microtransformers with each plotted in terms of maximum efficiency and thefrequency at which the maximum efficiency was obtained. Bubble size isproportional to voltage gain. [23â40]
In order to design these devices, models are analyzed to uncover the ideal
characteristics for operating in the VHF range. Compared to traditional air-core
components, the devices here feature thicker metal traces arranged into intricate
three-dimensional windings for lower loss and higher density. A multilevel microfabrication
process is developed for molding copper parts with the necessary characteristics of
thickness, minimum feature size, and out-of-plane stacking.
This dissertation has been organized as follows. In Chapter 2 information gathered
from a survey of existing microfabricated inductors and transformers is presented.
Chapter 3 highlights the goals and considerations that motivated the design of
the microinductors. Similarly, the design of the microtransformers is discussed in
Chapter 4 alongside an introduction to the math and methods used to characterize the
microtransformer performance. Presented in Chapter 5 is the fabrication process that
was developed to response to the aforementioned design needs and the shortcomings
of existing processes in meeting these needs. Characterization of the microfabricated
25
inductors and transformers at radio frequencies is covered separately in Chapters 6 and
7 for the inductors and transformers, respectively. Chapter 8 presents the packaging
and testing of microfabricated inductors within a prototype VHF hybrid boost converter
circuit and with a commercial converter chip. Chapter 9 concludes the dissertation with
a summary of the advancements led by this work in filling the gap for microscale power
inductors and transformers at VHF and enabling fully integrated power converters.
26
CHAPTER 2BACKGROUND
This chapter provides background information on existing works that have
contributed to the state of the art of microfabricated inductors and transformers.
Highlighted first are several significant demonstrations of very high frequency switched
mode power converters that have created the possibility for full integration of all
converter components in a single package. Power inductors and transformers from prior
works are then surveyed with attention focused on the challenges and accomplishments
met by each. Quantitative results from the surveyed inductors and transformers are
outlined in tabular form at the end of the chapter along with results from selected
GHz RF air core components for comparison. The works have been selected for their
inclusion of detailed performance characteristics relevant toward enabling integrated
switched mode power converters.
2.1 High Frequency Power Converters
Examples of very high frequency switching power converters are summarized
here to demonstrate the viability of this new breed of converters in providing high
performance with nH-level inductive components. The results from these works provided
an idea of what switching frequencies would be used in next-generation converters and
what size inductors would be required.
Hazucha et al. [2] reported results from a four-phase dc-dc buck converter
implemented in 90nm CMOS and designed to operate at switching frequencies ranging
from 100â 600 MHz. The optimal switching frequency was determined by the size of the
inductors. Four 6.8 nH discrete inductors were soldered onto the package for a switching
frequency of 233 MHz. The authors quoted quality factors for the inductors of Q = 20 at
100 MHz and Q = 30 at 300 MHz. The chip area of the converter was 1.26 mm2. The
converter delivered 0.3 A at 0.9 V from a 1.2 V input with 83% efficiency.
27
Li et al. [41] reported two discontinuous conduction mode dc-dc boost converters
fabricated in standard 0.13 ”m CMOS, both utilizing off-chip discrete inductors. One
was a 100 MHz 4-phase boost converter that delivered 240 mW from a 1.2 V supply with
output ranging from 3 â 5 V and peak efficiency of 64%. This converter used four 22 nH
inductors, one per phase, and the CMOS area alone comprised 0.55 mm2. The other
reported converter was a 45 MHz hybrid boost converter delivering 20 mW at 6 â 10 V
also from a 1.2 V supply, with peak efficiency of 37%. The hybrid converter used a single
43 nH inductor, while the CMOS area was 0.17 mm2. The authors stated that both high
switching frequency and discontinuous conduction mode were utilized to reduce the size
of the required off-chip components.
2.2 Inductors
Ahn et al. [22] constructed a 4 mm à 1 mm à 130 ”m toroidal inductor on a silicon
wafer via a multilevel metallization process. The inductor consisted of 33 turns of
40 ”m-thick copper traces wound around a 30 ”m-thick electroplated Ni81Fe19 magnetic
core. This composition of NiFe was cited as being chosen for achieving maximum
permeability, minimum coercivity, minimum anisotropy, and maximum mechanical
hardness. Permeability of the magnetic core was determined at approximately ”r = 800
both by vibrating sample magnetometry and magnetic circuit evaluation with a core
of known dimensions. The measured inductance was 400 nH at 10 kHz, but this value
decreased with frequency to a value of approximately 50 nH at 1 MHz. Such applications
for the inductor were listed as sensors, actuators, and power converters.
Yamaguchi et al. [42] demonstrated a 7.6 nH thin-film inductor with quality factor
of 7.4 at 1 GHz intended for use in impedance matching at the front-end receiver
of a 1 GHz mobile communication handset. The square-spiral inductor measured
370 ”m à 370 ”m and was comprised of 4 turns of 2.8 ”m-thick sputter deposited
AlSi windings. After encapsulating the windings with a 3.5 ”m-thick insulating layer of
polyimide, a 0.1 ”m-thick Fe61Al13O26 magnetic film was sputter deposited over the coils
28
and was patterned by ion milling. The authors acknowledged that simply covering the
inductor with the magnetic film could only double the inductance at best but predicted
the improvement would prove sufficient for commercial use. An inverse relationship was
found in the FeAlO films between the magnetic film resistivity and its resonant frequency,
although high values of each were desired to avoid excess losses at the GHz range. Slits
were created in the magnetic film to inhibit eddy current generation, resulting in a 31%
reduction in the ac resistance at 1 GHz compared to the case of the film without slits.
Sato et al. [11] developed a rectangular spiral inductor for 5 MHz switching
dc-dc converters. The inductors measured 6310 ”m à 3466 ”m in area and featured
50 ”m-thick electroplated copper windings capped with a FeCoBN magnetic thin film.
The magnetic film was deposited by dc magnetron sputtering with four alternating layers
of 1.5 ”m FeCoBN and 0.4 ”m AlNx to suppress eddy currents. Film permeability was
estimated at 900 up to 300 MHz. The multilayer film was etched in a single wet step
with mixture of phosphoric, acetic, and nitric acids used to dissolve both constitutive
materials at once. Inductance was measured at 370 nH with a peak quality factor
of 15 at 7 MHz. The inductor was tested in 5 MHz switched mode power converters
constructed of discrete components in both boost and buck configurations. The buck
converter produced an output of 3 V from a 5 V input with a peak efficiency of about
82% at an output current up to 500 mA. The boost converter operated with the same
conversion ratio in reverse; an output of 5 V was obtained from a 3 V input. A similar
peak efficiency of about 82% was achieved from the boost converter at 150 mA output
current.
Fukuda et al. [9] fabricated a 6 mm Ă 6 mm planar square spiral inductor that
was fully encapsulated between two NiZn ferrite magnetic layers. Ferrite composition
was NiO/CuO/ZnO/Fe2O3 in ratios of 16/12/23/49. The lower ferrite layer was first
screen-printed over a silicon wafer and sintered at 900 â 1000C to a final thickness
of 40 ”m. Relative permeability of the lower ferrite layer was measured at 120. Copper
29
windings were then electroplated 50 ”m-thick on top of the lower ferrite layer. The
upper ferrite layer was screen printed on top of the windings and was hardened but not
sintered. Due to the lower relative permeabilityâmeasured at 25âthe final upper ferrite
layer was deposited more than twice as thick at 100 ”m. Characterization of the inductor
revealed an inductance of 1.4 ”H with a peak quality factor of 40 at 5 MHz. Magnetic
field analysis by the finite element method indicated that the inclusion of magnetic ferrite
in the spaces between adjacent turns of the coil were beneficial in confining magnetic
flux to the core, minimizing eddy current loss in the copper coil.
Viala et al. [14] reported a square spiral inductor with a density around 90 nH/mm2
and peak quality factor of about 10 at 1.5 GHz with sputtered FeHfN films over spiral
inductors, but only noted a modest increase in inductance of 35% over the air-core case.
The magnetic films were laminated and consisted of ten alternations of 0.1 ”m-thick
(Fe97.6Hf2.4)90N10 magnetic and 500 A-thick SiO2 insulating layers. The authors noted
difficulty in using magnetic films with spirals due to their having both in-plane and
out-of-plane magnetic field components.
Characteristics of the above mentioned inductors were summarized in Table 2-1
alongside those from other significant works.
2.3 Transformers
Mino et al. [23] presented a 3 mm Ă 4 mm transformer fabricated by a completely
dry process on a silicon substrate and consisting of copper coils wrapped around a
magnetic layer of CoZrRe. The magnetic film was deposited by ion beam sputtering and
was quoted as having a relative permeability > 3000. The copper coils were wrapped
around the core in a primary:secondary ratio of 12 : 3 to obtain associated primary and
secondary inductances of 350 nH and 40 nH, respectively. The microtransformer was
mounted in a ceramic package and tested within a forward converter circuit operating at
32 MHz. Output from the converter was 0.6 V to a 10 Ω load with 10 V source input. The
30
efficiency of the converter was not given but was reportedly âlowâ due to the low primary
inductance of the transformer.
Yamaguchi et al. [33] fabricated a 2.4 Ă 3.1 mm2 microtransformer with stacked
primary and secondary spiral copper coils sandwiched between multilayered CoNbZr/SiO2
magnetic films on a glass substrate. RF sputtering was used to deposit both the copper
windings and the magnetic films, which were each patterned by a photoresist lift-off
method. Annealing of the magnetic core was performed at 250 C for 1 hour under
vacuum with a rotating magnetic field. The copper traces were deposited 7.5 ”m thick
and patterned 100 ”m wide with 10 ”m spacing. The turns ratio of primary:secondary
coils was 8 : 7.3. A 10 Ω load was attached to the secondary winding for measurement
of the transformer efficiency with 1 V sinusoidal input to the primary in the frequency
range of 1 â 20 MHz. A maximum efficiency of 67% was obtained at 10 MHz, beyond
which point efficiency was said to decrease due to core loss.
Sullivan and Sanders [27] measured the performance of microfabricated power
conversion transformers with areas on the order of 10 mm2 and primary:secondary
turns ratios of 8 : 4. Primary and secondary windings were interleaved in an elongated
spiral (racetrack) and consisted of 20 ”m-thick electroplated copper. A multilayer
laminated NiFe/SiO2 material acted as the magnetic core with a relative permeability of
2000. Two designs were fabricated: one had a sandwich configuration with the copper
windings embedded between separate layers of magnetic material, while the other
design featured a closed core that fully enclosed the windings. The sandwich design
was said to not only decrease inductance by a factor of 5 compared to the closed core,
but also produced an âunfavorable field distributionâ that further increased losses. A
half-bridge forward converter served as a test bed for the sandwich transformer and
measured 43.4% efficiency with 3.74 W input at 30 V and 1.625 W output at 4.21 V. The
same converter circuit was tested again with a litz wire transformer having the same
inductance as the sandwich transformer but assumed to have no loss. By comparing
31
the difference in efficiency with the litz wire versus the sandwich transformer, the
sandwich transformer efficiency was estimated at 61%. The closed core transformer was
tested with a network analyzer and projected to have an efficiency of 70%. Higher than
expected losses were attributed to hysteresis losses and shorting between layers in the
core.
Brunet et al. [28] presented a 30 mm2 microfabricated transformer consisting of
interleaved, racetrack-shaped primary and secondary coils encapsulated in 4 ”m-thick
electroplated Ni81Fe19 magnetic core. The copper coils were electroplated 43 ”m thick
and were arranged in a turns ratio of 4 : 2. Electrical characteristics were obtained using
an impedance analyzer. A primary inductance of 0.9 ”H was measured to be constant
up to 5 MHz. Leakage inductance was determined at 0.4 ”H measuring the primary
inductance while shorting the secondary coil. The transformer was tested in a full-bridge
dc-dc converter at 2 MHz. Converter efficiency was measured at 40% for input voltages
> 2 V. The core was found to saturate at an input voltage of 4.5 V for a maximum output
power of 0.4 W.
Characteristics of the above mentioned inductors were summarized in Table 2-2
alongside those from other significant works.
32
Table 2-1. Literature survey of microinductors.Inductance Peak Q DC
Reference Layout Core Area Inductance density Peak frequency resistancematerial (mm2) (nH) (nH/mm2) Q (MHz) (Ω)
Ahn et al. [22] Toroid Ni81Fe19 4 400 100 1.5 1 0.3Yamaguchi et al. [42] Spiral Fe61Al13O26 0.137 7.6 56 7.4 1000 6.5Sato et al. [11] Racetrack FeCoBN 21.9 370 16.9 15 7Song et al. [13] Racetrack FeZrBAg 146 1000 6.84 25 10 3.95Fukuda et al. [9] Spiral NiZn 36 1400 38.9 40 5 0.67Wang et al. [10] Racetrack NiFe 5.69 160 28.1 6 4 0.261Viala et al. [14] Spiral FeHfN 0.09 10 111 10 1500Flynn et al. [20] Toroid NiFe 10 1940 194 2 2Orlando et al. [21] Toroid NiFe 31.4 500 15.9 20 2 0.095Lee et al. [19] Solenoid CoTaZr 0.88 70.2 79.7 6.5 25 0.67Park and Allen [8] Spiral Air 1.69 37.8 22.4 44 1200 2.76Young et al. [15] Solenoid Air 0.25 14 56 18 820Choi et al. [16] Spiral Air 0.144 4.6 31.8 50 3500Weon et al. [17] Solenoid Air 0.05 2.1 42 78 4000 0.342Yoon et al. [18] Solenoid Air 0.06 1.17 19.5 84 2600
33
Table 2-2. Literature survey of microtransformers.Primary Secondary
Reference Area inductance inductance Coupling Voltage Efficiency Frequency Core(mm2) (nH) (nH) coefficient gain (MHz) material
Mino et al. [23] 12.0 350 40 0.5 0.3â 3% 32 CoZrReYamaguchi et al. [33] 7.44 500 450 0.7 67% 10 CoNbZrKurata et al. [24] 1.38 50 50 0.92 1â 54% 100â250 CoFeSiBMino et al. [25] 25 820 820 0.93 1â 58%â 25 CoZrReXu et al. [26] 4 800 800 0.9 0.63 77%â 10 Ni80Fe20Sullivan and Sanders [27] 8.42 1380â 345 0.5â 61% 8 NiFeSullivan and Sanders [27] 11.85 3176â 794 0.5â 70% 10 NiFeBrunet et al. [28] 29.92 900 225â 0.58â 40% 2 Ni81Fe19Park and Bu [29] 5.7 440 440 0.85 1â 32% 25 Ni80Fe20Rassel et al. [30] 4.95 100 80 0.9 0.9â 1% 0.5 NiFeYun et al. [31] 78.4 830 830â 0.91 0.9 84%â 5 Ni81Fe19Wang et al. [32] 23.7 400 400 0.93 0.89 72% 5 NiFeYamaguchi et al. [33] 7.44 70 65 0.4 30% 10 AirCheung et al. [34] 0.16 8â 8â 0.75â 1â 1000 AirCheung et al. [34] 0.25 0.5â 12â 0.75â 5â 1000 AirLaney et al. [35] 0.16â 1.65 1.65 0.55 1â 56% 2500 AirLong [36] 0.16 8.5 8.5 0.84 1â 2000â AirRibas et al. [37] 0.09 8.6 8.6 0.79 1â 32%â 10000â AirZolfaghari et al. [38] 0.06â 11â 180â 3 29%â 1500 AirNg et al. [39] 0.09 2 3 0.8 1.2â 60% 8000 AirAly and Elsharawy [40] 0.32 4.79 4.79 0.88 1â 56%â 2000â AirâAsterisked values were estimated based on the other information gathered from the respective references.
34
CHAPTER 3INDUCTOR DESIGN
This chapter outlines a methodology for designing microinductors for use in
high-frequency switched-mode power supplies. The quality factor is investigated as
a metric for the efficiency of the inductor in storing energy. Three inductor attributes
affecting peak quality factorâinductance, resistance, and maximum operating
frequencyâare discussed in terms of the trade-offs in attempting to maximize any
one of these quantities. The stacked planar spiral layout is chosen for the microinductors
with the goal of reaching high quality factor by maximizing inductive coupling while
minimizing electrical resistance. A modeling strategy is presented for optimization
of the design of such inductors and prediction of their performance. The models
provide a method for determining the optimal geometric proportions based on certain
combinations of desired criteria: inductance, size, operating frequency, and maximum
quality factor.
3.1 Quality Factor Definition
The quality factor, Q, of a circuit is a dimensionless quantity that generally provides
a metric of how much energy is stored in a circuit versus how much energy is dissipated
by it. However, the generality of this concept has led to confusion of the definition of
Q amongst researchers since there are many application-specific interpretations and
methods of extraction of Q [38, 43â46]. For example, one traditional use of Q is in
quantifying the selectivity of a resonant filter circuit [47]. In such filtering applications, Q
is defined as the ratio of the circuit resonant frequency to its half-power bandwidth.
3.1.1 Quality Factor of Non-Ideal Reactive Components
In contrast to the single-valued quality factor of resonant circuits, the quality factor
Q of an energy storing circuit component (e.g. inductor or capacitor) quantifies how
much energy is stored in the component versus how much is dissipated by it at each
35
frequency. However, even this alternate definition can take on different meanings to
different communities when the device is operated near its resonant frequency.
The discrepancy in definition arises from the fact that although the impedance of a
device under alternating current (ac), sinusoidal excitation at its resonant frequency is
purely resistive, energy is being stored and transferred within the electrical and magnetic
fields within the device. By definition, the reactive part of the impedance falls to zero at
resonance, and none of the energy stored in the device is available to the external circuit
attached to it. Passive components in power conversion applications, however, need to
store energy from the circuit and then provide that energy back to the circuit. For this
reason, a separate definition of Q is most appropriate for power conversion application
with the property that Q falls to zero at resonance. The simplified definition of Q used for
quantification of power-passive performance is the ratio of the imaginary to the real part
of the complex impedance looking into the device,
Q =âZâ Z . (3â1)
It can be shown that the above definition of Q for any one-port, energy-storing
component correctly provides a measure of the storage efficiency as seen by the
external circuit. The expected measure for the component under sinusoidal excitation is
the rate energy is stored in and retrieved from the device to the rate energy is dissipated
in it,
Q =Reactive power transfer
Real power transfer. (3â2)
Assuming root mean square (RMS) quantities for voltage and current, the complex
power transfer to/from a component is the product of the ac voltage V across the
component and the complex conjugate of the current I through it, so that Equation 3â2
is rewritten in terms of voltages and currents as
Q =â
V I
â
V I . (3â3)
36
Applying properties of complex conjugates, the real and imaginary part operators can be
expanded into equivalent algebraic expressions as
Q =
(
V I â V I)
/j2(
V I + V I)
/2, (3â4)
which simplifies through manipulation to,
Q =
(
VIâ V
I
)
/j2(
VI+ V
I
)
/2. (3â5)
The voltage and current terms in Equation 3â5 are arranged so that the impedance
equivalent is readily identified as,
Q =
(
Z â Z)
/j2(
Z + Z)
/2. (3â6)
By properties of complex conjugates, Equation 3â6 is identical to the original formulation
of Q in Equation 3â1 as the ratio of the imaginary to the real part of the complex
impedance of component.
3.1.2 Quality Factor of Inductor
As discussed in Section 3.1.1, the quality factor Q provides a metric of the ac
energy storage efficiency of actual, non-ideal reactive circuit components, such as
microinductors. The formulation of Q as the ratio of imaginary to the real part of the
inductor impedance (as in Equation 3â1) provides a figure of merit that quantifies the
degree to which an inductor acts like an inductor to an attached circuit.
For example, when used with direct current (dc) there is no electrical characteristic
that differentiates an inductor from a trace of wire with some resistance. Although
energy is stored in the magnetic field induced by the current flowing through the inductor
even at dc, in the absence of any variation in current over time, that energy is never put
back into the circuit.
When there are ac fluctuations in the current flowing through the inductor, energy
is stored as the current increases in magnitude to its peak level and is then retrieved
37
from the magnetic field back into the circuit as the current decreases in magnitude.
Some energy is dissipated as heat due to the resistance of the electrical path through
the inductor. At low frequencies, the rate of energy storage/retrieval is less than the
power dissipated by the inductor, and the inductor has consequently low quality. As
the frequency of the current oscillation increases, however, so too does rate of energy
storage/retrieval while the power dissipated remains relatively constant, and the inductor
therefore attains a higher Q. If the inductor is modeled as the serial combination of an
ideal resistor R and an ideal inductor L, the expression for quality factor at an angular
frequency of Ï as calculated from Equation 3â1 is
QRL =ÏL
R. (3â7)
This simplified expression ignores the changes in resistance that occur at very high
frequencies and also ignores capacitive energy storage in the electric field that invariably
exists in the inductor.
Because of parasitic capacitance, Q diminishes near the self-resonant frequency of
the inductor as more energy is stored in the electric field between traces. By definition,
Q = 0 at resonance as equal amounts of energy are traded between electric and
magnetic fields, and the spiral again appears as a resistor to the circuit.
3.2 Performance Trilemma
From Equation 3â7 the quality factor of a quasi-ideal inductor (ignoring effects
of capacitance) is dependent on its inductance, resistance, and operating frequency.
Ideally, the quality factor would be maximized if the inductance and operating frequency
were maximized and the resistance minimized. In practice, however, all of these
quantities are linked, so that improvements to any one of these three attributes is
often done at the detriment of the other two.
Consider the simple model of the inductor shown in Figure 3-1 with inductance
L, series resistance R, and shunt capacitance C . Self-resonance limits the maximum
38
operating frequency of the inductor and for the case of low resistance is approximately
equal to the natural frequency,
Ï0 =
â
1
LC. (3â8)
The above equation clearly shows that increasing inductance directly results in
decreasing resonant frequency. However, attaining higher inductance often entails
increasing the trace length of the inductor winding, resulting in higher capacitance,
which in turn further decreases the resonant frequency. The increased trace length
also increases the resistance of the inductor. Designing inductors must balance these
competing goals to deliver a device that is tailored to the application.
C
R
L
Figure 3-1. Circuit diagram of simple inductor model with inductance L, series resistanceR, and shunt capacitance C .
3.3 Stacked Planar Spiral Layout
In response to the previously mentioned concerns for maximizing inductance while
minimizing resistance and capacitance, the stacked planar spiral layout was selected
for the inductors of this work. The planar spiral layout features conductive traces that
are concentrically wound into a flat spiral as depicted in Figure 3-2. This layout is the
most popular amongst all integrated inductors because it offers high density through
tight spiral packing and it is easy to fabricate via conventional planar microfabrication
steps. When all traces are constrained to only a single plane, however, performance is
limited by poor magnetic coupling between outer and inner windings. As the number of
spiral turns is increased, the separation between inner and outer windings can become
so great that the inner turns contribute more towards increasing the resistance of the
inductor than towards its inductance.
39
To overcome the planar limitation, vertical stacking of planar spirals is used to
increase both the inductance density and the quality factors of the inductors. Because
the planar spiral is by nature wider in diameter than it is thick (given typical conductor
thicknesses), stacking spirals provides excellent magnetic field coupling in the vertical
direction. Assuming perfect coupling, the inductance of a two-layer stacked-spiral
inductor can reach up to four times that of a single layer while the resistance is only
doubled. In this simplified example, the inductance to resistance ratio of the two-layer
device is improved to twice that of a single-layer device.
3.4 Low Frequency Analytical Inductor Model
The low-frequency model of the inductor includes only the electrical resistance
along the length of the trace winding and the magnetic field generated when an
electric current passes through the winding. The current is assumed to flow uniformly
through the cross section of each trace, ignoring current crowding due to interactions
between moving charge carriers. Inductance and resistance are first calculated for a
single-layer winding of uniform trace width and thickness. The values are then extended
as appropriate when two layers are vertically stacked.
By the year 1928 Wheeler [48] had derived by empirical data an expression to
predict the inductance of discrete radio coils. More than 70 years later Mohan et al. [49]
modified the existing expression only slightly to be valid also for microinductors,
Lmw =K1”0n
2davg
1 + K2p. (3â9)
In the above expression, K1 and K2 are empirically derived values that are specific to
the shape of the spiral (i.e. square, hexagonal, octagonal) and are listed in Table 3-1.
An additional expression was presented in Mohan et al. [49] for calculating inductance
based on a current sheet approximation [50],
Lgmd =”n2davgc12
[
ln
(
c2
Ï
)
+ c3Ï+ c4Ï2
]
, (3â10)
40
Table 3-1. Coefficients for modified Wheeler (Equation 3â9) and current sheet (Equation3â10) expressions [49].
Shape K1 K2 c1 c2 c3 c4Square 2.34 2.75 1.27 2.07 0.18 0.13Hexagonal 2.33 3.82 1.09 2.23 0.00 0.17Octagonal 2.25 3.55 1.07 2.29 0.00 0.19Circle - - 1.00 2.46 0.00 0.20
for which expression the shaped-dependent coefficients (c1, c2, c3, and c4) are provided
not only for square, hexagonal, and octagonal shapes but also for circular. These
coefficients are also listed in Table 3-1. The choice between using the two previously
listed expressions depends on the situation. If a circular layout is desired, the current
sheet expression in Equation 3â10 provides the best accuracy. If rearranging the
expression to solve for a different variable, the modified Wheeler expression in Equation
3â9 is simpler to solve.
The authors of these expressions noted that each had been validated only for
inductors < 100 nH with outer diameters ranging from 100 â 480 ”m [49]. As part of
this dissertation work, the inductance values calculated from Equation 3â9 were verified
against magnetoquasistatic simulations with less than 5% error for inductors up to
1050 nH and outer diameters up to 2.5 mm (see Section 6.3.1.1).
All of the other variables in both Equation 3â9 and Equation 3â10 â i.e. the number
of turns n, the packing density p, and the average diameter davg â are obtained from the
geometry of the spiral. The geometry of the spiral can be uniquely specified in terms of
the winding trace width w , the spacing between adjacent winding traces s, the number
of winding turns n, and the outer diameter D. These dimensions are marked on the
diagram of an example spiral in Figure 3-2. Inner (d) and outer (D) diameters were
measured from the centerlines of the innermost and outermost traces, respectively.
The inner diameter d represents the space contained within the spiral that is clear of
41
w s
d
D
Figure 3-2. Diagram of planar spiral layout with n = 3 turns and all other dimensionslabelled.
windings and is calculated as a function of the other dimensions,
d = D â 2 [wn + s (n â 1)] . (3â11)
The average diameter is then simply calculated as
davg =D + d
2. (3â12)
The packing density p represents the fraction of the inductor area that is filled with
windings and is defined as
p =D â dD + d
. (3â13)
Extending the aforementioned inductance and resistance calculations for a single
layer spiral, the total inductance for an inductor with two identical spirals stacked
vertically is calculated in proportion to L0, the inductance of a single-layer spiral from
either Equation 3â9 or 3â10,
Ldc = 2 (1 + k)L0, (3â14)
42
where k is the coupling coefficient representing the portion of shared magnetic flux
linking the top and bottom spirals. The value of k can vary between â1 and 1. If the
spirals are positioned so that no magnetic flux is shared between spirals, k = 0 and the
total inductance is twice that of the single-layer coil. When all flux is shared between
coils, k = 1 and the total inductance is four times that of the single-layer coil. If the
coils are stacked so that the magnetic fluxes of each coil are in opposition, k can have
a negative value as the opposing magnetic fields nullify and reduce the total amount of
flux linking the coils.
The dc resistance of the inductor can be calculated by the familiar expression for
resistance,
Rdc =Ïl
wt, (3â15)
where Ï is the electrical resistivity of the trace material, l is the total electrical path length
of the inductor, and t is the thickness of the trace. The total trace length of the stacked
spiral windings can be calculated from the geometry design variables. For the two-layer
stacked square spiral, the total electrical trace length is evaluated as
l = 2[
4nD â (2n â 1)2 (w + s)]
. (3â16)
The trace length for the two-layer stacked circular spiral case is calculated as
l = 2Ï [nD â n (n â 1) (w + s)] . (3â17)
3.5 Trends and Optimization
3.5.1 Analytical
The expressions listed in Section 3.4 for estimating the low-frequency inductance
and resistance of spirals were used to explore performance trends associated with
sweeping certain design variables. A square spiral shape was assumed for ease in
rapidly iterating layout and modeling. Perfect coupling (k = 1) was assumed for all
cases. The target metric for this simplified analysis was the inductance to resistance
43
ratio L/R, which is proportional to the quality factor at low frequencies (see Equation
3â7).
The first case was to determine the optimal packing density. The spacing between
turns was fixed at s = 10 ”m, while the width of the traces was varied. The number of
turns was swept from the minimum number of turns (n = 1) turn up to the maximum
number of turns that could physically be packed within the allotted area. Separate
runs were completed for each different outer diameter D. The results were plotted for
D = 500 ”m (Figure 3-3A) and D = 1000 ”m (Figure 3-3B). For all outer diameters and
widths, the Ldc/Rdc ratios increased drastically as the number of turns was increased
from 1 but then reached their maximal values at a packing density of approximately
p = 0.4, which is equivalent to the points at which inner diameters were barely greater
than 40% of the outer diameters. Also from these plots, the maximum Ldc/Rdc ratio
increased with increasing trace width up to about w = 50 ”m, past which no significant
further increases were recorded.
The plots of Figures 3-3A and 3-3B also suggested that the Ldc/Rdc might also
increase with outer diameter. To test this idea, outer diameters from D = 0.5 mm up
to D = 2.5 mm were evaluated using the optimal widths and packing densities already
learned. For each trial with different outer diameter, the trace spacing was fixed at
s = 10 ”m, the trace width was fixed at w = 50 ”m, and the number of turns n was
calculated such that the packing density would be approximately p = 0.4. In this setup,
the Ldc/Rdc computed for each outer diameter should represent approximately the peak
values of the curves seen in Figure 3-3. The results from sweeping the outer diameter
are plotted in Figure 3-4 and indicate a linear relationship between the Ldc/Rdc ratio and
the outer diameter of the inductor.
3.5.2 FastHenry
FastHenry is a software program that can solve the magnetoquasistatic inductance
and resistance of a three-dimensional structure using integral equation-based mesh
44
0 0.2 0.4 0.6 0.8 16
8
10
12
14
16
18
20
22
24
26
Packing Density p
L dc/R
dc (
nH/Ω
)
20 ”m30 ”m40 ”m50 ”m60 ”m70 ”m80 ”m
Width w
A Outer diameter D = 500 ”m
0 0.2 0.4 0.6 0.8 15
10
15
20
25
30
35
40
45
50
55
Packing Density p
L dc/R
dc (
nH/Ω
)
20 ”m30 ”m40 ”m50 ”m60 ”m70 ”m80 ”m
Width w
B Outer diameter D = 1000 ”m
Figure 3-3. Trends of inductance to resistance ratio vs. packing density for various tracewidths and outer diameters.
45
0.5 1 1.5 2 2.520
40
60
80
100
120
140
Outer Diameter D (mm)
L dc/R
dc (
nH/Ω
)
Figure 3-4. Trends of inductance to resistance ratio vs. outer diameter using w = 50 ”m,s = 10 ”m, and n such that p â 0.4
10â1
100
101
102
103
80
100
120
140
160
Interlayer spacing (”m)
Indu
ctan
ce (
nH)
4L0
2L0
FastHenry simulation results
k=0
k=1
Figure 3-5. Trend of inductance vs. vertical gap between stack in 1 mmĂ 1 mm assimulated in FastHenry.
46
analysis combined with a multipole-accelerated iterative solution algorithm [51]. A
variety of stacked inductor designs were simulated in FastHenry, first to validate the
analytical model results and then also to determine the effect of vertical separation
between the two stacked layers on the mutual inductance between them. The same
inductor design was simulated several times in FastHenry but with increasing vertical
layer separation in each simulation trial. Plotted in Figure 3-5 is the low frequency
inductance obtained for a 1 mm Ă 1 mm with interlayer separation varied from 0.1 â
1000 ”m. Drawn on the plot are lines indicating 2à and 4à the inductance L0 that would
be obtained for a single winding layer. For the simulation with two winding layers the
inductance asymptotically approaches 4L0 (k = 1) and 2L0 at the extremes of short
and long separations, respectively. FastHenry simulations indicated that there would be
minimal improvement to the inductance with separations less than 1% of the inductor
diameter. A vertical separation of 10 ”m was used for the microfabricated devices as
shorter separations would serve only to detrimentally increase the parasitic capacitance
between layers.
3.6 Radio Frequency Effects
Although direct current (dc) assumptions (e.g. uniform current distribution) enabled
a simplified optimization of the inductor layout (such as diameter and number of
turns), inductors designed for microscale power systems need to operate at such
high frequencies (> 10MHz) that complex electromagnetic behavior alters the
apparent inductances and resistances from the expected dc values. The dominant
electromagnetic effects can be classified as due to capacitive coupling or due to eddy
current generation.
3.6.1 Capacitive Coupling
Capacitive coupling results from variations in voltage potential that exist within
different parts of the inductor. It is especially prominent between the terminal ends of the
inductors where the difference in potential is the greatest. Because the terminal ends
47
are where the inductor is connected to the rest of a circuit or where large landing pads
provide electrical connection to probe tips for measurement and characterization, the
effect of capacitive coupling can be highly dependent on factors that are external to the
design of the inductor.
Intrinsic to the design of the inductor, however, is the capacitive coupling that
occurs between adjacent windings of an inductor. Microinductors intended for GHz RF
applications typically consist of a single winding layer and a metal underpass providing
electrical connection to the innermost turn. The interwinding capacitance of these
single-layer inductors has long been known to be dominated by the areas where the
windings and the underpass overlap [52, 53]. The stacking of windings for greater
inductance density, as in the inductors of this work, would result in even greater levels of
interwinding capacitance due to the significantly increased area of overlap. The general
expression for capacitance between parallel plate electrodes,
C =Ç«A
g, (3â18)
shows that in addition to the overlap area between plates A, the other aspects affecting
capacitive coupling are the permittivity Ç« of the material between the plates and the
distance g of the gap between them. The multilevel thick-film fabrication technology
presented in Chapter 5 minimizes the capacitive coupling between upper and lower
winding layers by separating the layers by up to 30 ”m and removing all dielectric
material from between layers.
If the inductors are fabricated on a conductive substrate such as silicon, the
substrate creates an additional path for capacitive coupling. To electrically isolate
the inductor from the substrate a thin dielectric layer such as silicon dioxide is often
deposited over the substrate. Considering a scenario where two traces of an inductor at
different voltage potentials sit atop the dielectric layer in close proximity, capacitors are
48
formed with the dielectric layer between each trace and the substrate with the substrate
providing an electrical connection between the two traces as illustrated in Figure 3-6.
Copper Trace Copper Trace
Conductive Substrate
Dielectric Layer
Figure 3-6. Diagram illustrating capacitive coupling through substrate between coppertraces of inductor winding.
Like the interwinding capacitance, the shunt capacitance through the substrate
contributes to resonant behavior as energy oscillates between inductive and capacitive
storage elements. However, the finite resistance of the capacitive link through the
substrate can have a profound effect on the perceived inductor behavior near the
resonance. The substrate resistance can be modeled as a resistor Rc in series with the
capacitance to the substrate Cs , as drawn in the circuit diagram in Figure 3-7.
Cs
Rdc
Ldc
Rc
Figure 3-7. Circuit diagram of inductor model with dc inductance Ldc , series resistancethrough the inductor Rdc , shunt capacitance to the substrate Cs , andresistance along the capacitive path through the substrate Rc .
49
107
108
109
10â9
10â8
10â7
10â6
10â5
Frequency (Hz)
Indu
ctan
ce (
nH)
R
c=0 Ω
Rc=10 Ω
Rc=100 Ω
Rc=1000 Ω
A Effective Inductance
107
108
109
10â2
100
102
104
106
Frequency (Hz)
Res
ista
nce
(Ω)
R
c=0 Ω
Rc=10 Ω
Rc=100 Ω
Rc=1000 Ω
B Effective Resistance
107
108
109
0
20
40
60
80
100
120
Frequency (Hz)
Qua
lity
Fac
tor
R
c=0 Ω
Rc=10 Ω
Rc=100 Ω
Rc=1000 Ω
C Effective Quality Factor
Figure 3-8. Modeled effect of substrate resistance on overall inductor impedance.Impedance calculated from circuit model for inductor with dc inductanceLdc = 100 nH and dc resistance Rdc = 1 Ω. Substrate resistance Rc varied inseries with substrate capacitance Cs = 1 pF in circuit model.
50
When the capacitance through the substrate is the dominant capacitance
contributing to resonance with the inductor, the substrate resistance causes a damping
of the resonant behavior. To illustrate the effect of this damping, the circuit model of
Figure 3-7 was simulated with values of inductance, resistance, and capacitance that
would be typical of microinductors fabricated according to the methods of this work.
The effective inductance, resistance, and quality factor looking into the lumped inductor
circuit were extracted from the modeled data and plotted in Figure 3-8 for different
values of substrate resistance. The plots show that, compared to the case of zero
substrate resistance, increasing substrate resistance results in a lower peak inductance
near resonance and a lower frequency point at which the effective resistance raises
above its dc value due to resonance. The overall effect is a smoothing of the resonant
peaks and a decrease in the quality factor of the inductor at higher frequencies.
Cs
Rdc
Ldc
Rc
CL
Figure 3-9. Circuit diagram of inductor model with dc inductance Ldc , series resistancethrough the inductor Rdc , shunt capacitance between windings of CL, shuntcapacitance to the substrate of Cs , and resistance along the capacitive paththrough the substrate of Rc .
At even higher values of substrate resistance, this simple model (including only
capacitance with the substrate) shows that the resonant behavior would become ever
increasingly damped. With more and more damping, the inductance would remain ever
flatter with frequency, and the rise in effective resistance would be pushed out to greater
frequencies. As this resonance is damped out with very high substrate resistance,
the quality factor would improve again as the inductor would behave more ideally (i.e.
without capacitance). In practice, however, as the substrate capacitance is damped
51
107
108
109
10â9
10â8
10â7
10â6
10â5
Frequency (Hz)
Indu
ctan
ce (
nH)
CL=100 pF
CL=10 pF
CL=1 pF
CL=0.1 pF
A Effective Inductance
107
108
109
10â4
10â2
100
102
104
Frequency (Hz)
Res
ista
nce
(Ω)
CL=100 pF
CL=10 pF
CL=1 pF
CL=0.1 pF
B Effective Resistance
107
108
109
0
20
40
60
80
100
120
Frequency (Hz)
Qua
lity
Fac
tor
C
L=100 pF
CL=10 pF
CL=1 pF
CL=0.1 pF
C Effective Quality Factor
Figure 3-10. Modeled effect of competition between winding capacitance and substratecapacitance on overall inductor impedance. Impedance calculated fromcircuit model for inductor with dc inductance Ldc = 100 nH and dcresistance Rdc = 1 Ω. Winding capacitance CL varied with no seriesresistance while substrate capacitance Cs = 1 pF had series resistanceRc = 1000 Ω in circuit model.
52
out, the intrinsic interwinding capacitance begins to dominate. To more accurately
model the behavior of the microinductors the circuit must include the interwinding
capacitance as drawn in Figure 3-9, with the interwinding capacitance CL placed in
parallel with the capacitance through the substrate. Unlike the capacitance through
the substrate, the interwinding capacitance is relatively lossless, assuming only air or
a low-loss dielectric between the traces. If the value of the interwinding capacitance
is of similar value or larger than the capacitance to the substrate, the interwinding
capacitance will dominate the overall resonant behavior of the inductor. The circuit of
Figure 3-9 with both interwinding and substrate capacitance was simulated to show the
competition of the two capacitances. The simulated impedance looking into an inductor
with typical parameters was plotted in Figure 3-10 for various values of interwinding
capacitance. As shown in the plots, the resonance showed sharper peaks in effective
inductance and resistance when the interwinding capacitance was greater than the
substrate capacitance, due to the absence of resistance in series with the interwinding
capacitance. The quality factor, however, is lowered even further by interwinding
capacitance compared to the case of assuming only substrate capacitance. This is
due to the resonant frequency of the inductor being lowered from the case in which
resonance is governed by the substrate capacitance.
3.6.2 Eddy Currents
Eddy currents disrupt the flow of current through current through inductor traces
and result from the interaction of a conductor with the time-varying magnetic field of high
frequency electrical currents. When an electric current is passed through any conductor,
a corresponding magnetic field is generated in the space surrounding the current.
When the direction of current flow alternates (ac excitation), so too does the polarity of
the associated magnetic field. According to Lenzâs law electrical currents are induced
in nearby conductors so as to oppose the incident alternating magnetic field. These
induced currents are called eddy currents, and these confine the current to flowing only
53
through a reduced cross-section of the inductor traces. The effects of eddy currents
have commonly been separated into the effects of an ac current to its own distribution
(skin effect) and the effects to other nearby current paths (proximity effect).
The skin effect refers to the tendency of a high-frequency ac current to confine itself
only along the surface of a conductor rather than flowing evenly throughout the cross
section of the conductor. This effect is the result of eddy currents generated within the
conductor of the ac current itself. An oft-cited parameter related to this effect is the skin
depth, which refers to the distance from the surface of a conductor at which the current
density is reduced to 1/e â 0.37 of its nominal value at the surface. For good conductors
(Ï/ÏÇ« â« 1) the skin depth is approximately given by
ÎŽ ââ
2
Ï”Ï, (3â19)
where Ï is the conductivity and ” is the magnetic permeability of the conductor material
and Ï is the angular frequency of the ac current.
However, the approximation above is only applicable in certain cases, such as that
of an electromagnetic wave incident on an infinite slab of conductor or of current through
a conductor with circular cross section. However, the traces of the microinductors in this
and most contemporary works are of rectangular cross section. To illustrate the effect
of shape on the skin effect, COMSOL simulations were performed to plot the current
density and magnetic fields across the cross sections of two copper windings with the
same area but different aspect ratios as in Figure 3-11. The trace with closer to 1 : 1
aspect ratio exhibited a more uniform distribution of current density around its perimeter,
while the flatter trace exhibited greater current crowding along its shorter edges. For the
same level voltage excitation, the maximum current density in the 50 ”mà 10 ”m trace is
15% greater than that of the 25 ”m à 20 ”m trace. The minimum current density is also
15% less in the thinner trace compared to the thicker one.
54
A Copper trace: 50 ”mà 10 ”m
B Copper trace: 25 ”mà 20 ”m
Figure 3-11. COMSOL simulations at 100 MHz of current density and magnetic field incross sectional view of copper windings having the same area but differentaspect ratios.
55
Regarding the general question as to which surfaces of a conductor would carry
high frequency current, Wheeler [54] answered with a simple rule:
âThe rule is, that the current follows the path of least impedance.â
This simple rule aids in the understanding of the segregation of current along the short
sides of a rectangular conductor. At dc, impedance is purely resistive and current flows
uniformly through a straight conductor. With increasing ac frequency, a conductorâs
impedance is increasingly dominated by an inductive component. As Wheeler [54]
observed, the answer as to determining the distribution of high frequency current then
becomes one of finding the path of least inductance. In a flat rectangular conductor, the
regions of greatest current density at the short ends (see Figure 3-11A) can be thought
of as separate parallel wires with current flowing in the same direction. Inductance
is then minimized when the parallel current paths are farthest separated and their
magnetic fields cancel in the interior of the conductor.
The relationship between inductance and resistance at high frequencies is evident
in how these values change in an inductor as functions of frequency. Wheeler [54]
discussed an âincremental-inductance ruleâ by which the effective resistance of
conductors could be calculated as equal to the change in reactance resulting from eddy
currents in certain cases. Although the premise of this rule is invalid for the traces with
rectangularly-shaped cross sections [55], a similar result was found in the measurement
of the microinductors. After measuring the frequency-dependent resistance R (f )
and reactance ÏL (f ) of an example inductor, the deviations in resistance (âR) and
reactance (âX ) from their values at lower frequencies (Rdc and ÏLdc , respectively)
were plotted in Figure 3-12. While the large increases in both resistance and reactance
in the plot past 200 MHz are due to self-resonance, the deviations in resistance and
reactance from their lower-frequency values are roughly equal and opposite from about
20â200 MHz as indicated by the plot of âR + âX remaining relatively flat.
56
107
108
109
â10
â5
0
5
10
Frequency (Hz)
Impe
danc
e (Ω
)
âX=ÏL(f)âÏLdc
âR=R(f)âRdc
âR+âX
Figure 3-12. Measured effect of eddy currents on inductor impedance. Plot shows themeasured deviations in resistance (âR) and reactance (âX ) from theirvalues at lower frequencies (Rdc and ÏLdc , respectively).
3.7 Summary of Inductor Design
The preceding chapter outlined a methodology for designing air-core inductors for
switched mode power converters.
âą Quality factor was shown to be a metric of how much energy is stored in aninductor per cycle compared to how much is dissipated by it.
âą The three complementary effects of inductance, resistance, and parasiticcapacitance were discussed for their roles in affecting inductor quality factor,which motivated a stacked planar spiral design that balanced the three effects.
âą An analytical model was presented with the goal of predicting inductor performanceat low frequencies.
⹠The model was analyzed to uncover trends affecting the inductance to resistanceratio when varying geometric parameters. An optimal geometry was found with atrace width of 50 ”m and a packing density of 40%.
âą A circuit model for capacitive coupling between the inductor and substrate revealedthat increases in substrate resistance would result in a dampening of the resonantbehavior of the inductor and a reduction in the peak quality factor.
57
âą Eddy currents were discussed as leading to skin and proximity effects thatwould increase the resistance of inductor windings at higher frequencies as thecurrent would seek to flow through a path of minimum impedance (i.e. minimuminductance at high frequencies).
58
CHAPTER 4TRANSFORMER DESIGN
This chapter discusses the considerations that shape the design of transformers.
The similarities and differences between the designs of inductors and transformers
are first established. Maximum transducer efficiency is introduced as a metric for
transformer optimizing transformer performance. In an effort to utilize lessons learned
from the inductor design, a high-level, abstracted look at energy flowing through a
transformer shows how the quality factors of individual inductors can provide insights
into the maximum efficiency of a transformer. From these insights, a winding layout
scheme for the transformers is selected that allows both high performance and
step-up/down opportunities. A circuit model for the transformers is then presented
to explain the frequency behavior of the devices. Finally, network analysis is used to
derive expressions for the load-dependence of the transformer efficiency and voltage
gain.
4.1 Overview and Goals
The transformers presented in this work consist essentially of a pair of coiled
inductors so positioned that their magnetic fluxes are linked and energy can be
transferred from one to another. While it is possible to create transformers incorporating
more than two coils for more complex power distribution, the analyses in this chapter
are limited to two-coil devices. The two coils are referred to as primary and secondary;
the power source is connected to the primary coil and power is transferred to the load
connected to the secondary coil.
Just as the quality factor is important in establishing the efficiency of magnetic
energy storage in an inductor, so too does the magnetic energy transfer in a transformer
rely on currents flowing through its windings, ideally with as little resistive loss as
possible for high efficiency. However, due to imperfect magnetic flux coupling between
the coils in a transformer, some energy is stored in the individual windings and not
59
transferred. At high frequencies a significant proportion of energy is also capacitively
stored in the electric field between coils. The interactions between these effects is
further complicated by the load impedance, which can alter the phase at different
parts of the transformer to help or harm efficiency. The primary goal of the design is to
maximize the efficiency of power transfer through the transformer.
4.2 Maximum Efficiency
As two port devices, the transformers require a different metric for efficiency
than the quality factor used for inductors. Further, the efficiency of the transformer
will depend on the load that is attached to it. For the following analyses efficiency is
defined as the ratio of real power output to the load versus the real power input to the
transformer. One useful case is that of the maximum possible efficiency assuming
conjugate-impedance matched loading.
4.2.1 From Scattering Parameters
In the realm of radio frequency (RF) systems, efficiency is referred to as power
gain, the ratio of output to input power. Characterization of RF devices typically
entails determination of scattering parameters, which are obtained by measurement
of sinusoidal signals incident on, reflected from, and transmitted through the device to
be tested [56]. The maximum power gain (efficiency) that can be attained from a generic
two-port transducer (e.g. a transformer) is obtained for the case of conjugate-impedance
matched loading and can be calculated from the scattering parameters [57],
Gmax =|S21||S12|
(
K ââK 2 â 1
)
, (4â1)
where K is the Rollet Stability Condition, which is defined as
K =1â |S11|2 â |S22|2 + |S11S22 â S12S21|2
2 |S12S21|. (4â2)
However, this complicated expression for efficiency does not lend itself to being easily
interpreted to aid in the design of transformers.
60
4.2.2 From Coil Quality Factors and Coupling Coefficient
A simplified analysis may be performed for the case of conjugate-impedance
matched loading, which enables the derivation of maximum transformer efficiency in
terms of targetable design variables, namely coil quality factor and coupling coefficient
between primary and secondary coils. Under matched conditions, no power is reflected
to the source. When a certain energy Ein is input to the primary transformer coil some
of that energy is stored in the magnetic field around the primary coil and some Ed1 is
dissipated by it. The magnetically stored energy is comprised of both that energy Em
which is mutually shared between the primary and secondary and that energy Es1 which
is not coupled with the secondary. Written algebraically, the sum of primary coil energies
is
Ein = Ed1 + Es1 + Em. (4â3)
Of the energy Em that is coupled to the secondary coil, some energy some Ed2 is
dissipated, while some Es2 is stored solely in the magnetic field of the secondary. Finally,
the remaining energy Eout is output to the load. The sum of secondary coil energies is
Em = Ed2 + Es2 + Eout . (4â4)
This energy flow is shown schematically in Figure 4-1.
Ed1 Ed2
Es1 Es2
Ein Eout
Primary Secondary
Em
Figure 4-1. Diagram of energy flowing into primary transformer coil. Some of that energyis stored or dissipated, and the rest is transferred to the secondary coil.Some of that energy is stored or dissipated, and the rest is output to theload.
61
The coupling coefficient k specifies the fraction of the total magnetically-stored
energy that is transferred between the primary and secondary coils. In the primary coil,
the magnetically-stored energy is that which is input minus that which is dissipated by
the primary, so that the coupling coefficient can be written as
k =Em
Ein â Ed1=
Em
Es1 + Em. (4â5)
The same coupling coefficient can be equivalently written in terms of the secondary
coil energies. In the secondary coil, the total magnetically-stored energy is that which
is transferred from the primary plus that which is stored solely in the secondary. The
coupling coefficient can therefore be written as
k =Em
Es2 + Em. (4â6)
The quality factors of each coil are the other design variables of interest and
represent the total energy stored in the magnetic field of each coilâboth coupled (Em)
and uncoupled (Es )âto that dissipated by it. For the primary coil the quality factor is
Q1 =Es1 + EmEd1
, (4â7)
and for the secondary the quality factor is similarly
Q2 =Es2 + EmEd2
. (4â8)
If Equations 4â7 and 4â8 are multiplied with Equations 4â5 and 4â6, the resulting
expressions are simply
kQ1 =Em
Ed1(4â9)
and
kQ2 =Em
Ed2. (4â10)
Finally, the above Equations 4â9 and 4â10 can be combined to derive a simple
expression for the maximum transformer efficiency. In terms of the energy variables,
62
the overall efficiency η of the transformer is defined as the ratio of useful energy of the
secondary, that is, the output energy plus the secondary stored energy, over the useful
energy of the primary, that is, the input energy minus the primary stored energy,
η =Eout + Es2Ein â Es1
. (4â11)
From the sums at the primary (Equation 4â3) and secondary (Equation 4â4) energy
nodes, Equation 4â11 can be rewritten as
η =Em â Ed2Em + Ed1
=1â Ed2/Em1 + Ed1/Em
. (4â12)
Substituting the ratios of dissipated to transferred energy in the above equation with
expressions of coupling coefficient and quality factor of Equations 4â9 and 4â10,
Equation 4â12 becomes
η =1â 1
kQ2
1 + 1
kQ1
=k â 1/Q2k + 1/Q1
. (4â13)
This final expression calculates the maximum transformer efficiency given only
the individual coil quality factors and the coupling between coils. To validate this result,
Equation 4â13 and the classic expression for Gmax given by Equation 4â1 were both
used to calculate efficiency using the same measured data. Both calculations were
plotted as in Figure 4-2 and displayed excellent agreement at frequencies well below the
first resonant frequency of the transformer. Near the resonant frequency (> 200 MHz
in Figure 4-2 for example), the efficiency calculated as Gmax was much greater due to
its accounting for the capacitive energy storage and adjusting the load accordingly,
whereas the simple expression of Equation 4â13 was derived assuming no capacitive
storage.
Equation 4â13 reveals several insights that are useful for designing transformers for
optimal efficiency. The first insight is that the importance of coupling between primary
and secondary diminishes with increasing quality factor of each coil.
63
107
108
0
20
40
60
80
100
Frequency (Hz)
Effi
cien
cy (
%)
G
max(S
11,S
12,S
21,S
22)
η(Q1,Q
2,k)
Figure 4-2. Transformer efficiency calculated by both Q factors and S parameters andmeasured data taken from an example inductor. Excellent agreement wasobtained up to 200 MHz, at which point the transformer approachedresonance and capacitive storage dominated.
The second insight is that, because the quality factors of Equation 4â13 are
dependent on frequency, the primary and secondary coils should attain their highest
quality factors at the same frequencies to obtain the highest overall transformer
efficiency. Isolation transformers with 1 : 1 turns ratios usually have nearly identical
primary and secondary coils and thus easily satisfy the requirement for matching
frequency behavior. Transformers with non-unity turns ratios, however, are comprised
by necessity of mismatching coils with unequal inductances. The coil with lesser
inductance is often physically smaller with less parasitic capacitance and higher self
resonant frequency than the coil with greater inductance. The smaller coil is therefore
likely to attain higher quality factor at higher frequency than the larger coil. This issue
limits the efficiency of high frequency transformers with large turns ratios.
64
4.3 Layout
The layout for the transformers of this work employed a hybrid combination of two
winding techniques: interleaving and nesting. Utilizing the same analytical expressions
from the inductor design (Section 3.4), the primary coil was first laid out according to
the required specification, except with extra space provided between turns. Within this
space, the secondary coil was interleaved as an exact copy of the primary but rotated
180. The resulting layout would be that of a 1 : 1 transformer. In order to achieve
voltage/current gain, additional secondary turns were then nested within the space
cleared by the primary coil. An example layout of a microtransformer is depicted in
Figure 4-3.
A Lower winding layer B Upper winding layer
Primary Winding
Secondary Winding
Via
C Key
Figure 4-3. Diagrams illustrating transformer winding layout on lower and upper windinglayers. Key identifies windings belonging to primary and secondary coils andlocation of vias.
4.3.1 Turns Ratio
The turns ratio of a transformer is roughly a measure of its voltage or current gain.
This ratio has been traditionally useful for transformers with such high permeability
magnetic cores that the magnetic flux induced by wires wrapped around the core are
essentially fully contained within the core. For such transformers with nearly perfect
magnetic coupling, the magnetic flux induced by the primary coil is fully sensed by the
65
secondary coil. The gain is then equal to the primary to secondary ratio of the number of
physical turns of wire around the core, as suggested by the term âturns ratio.â
However, microscale transformers with no or low permeability magnetic cores do
not exhibit perfect coupling. Furthermore, not all turns of the microtransformer coils have
equal contributions to the inductance due to the difference in areas enclosed by inner
and outer loops. The turns ratio of a 1 : n microtransformer is instead calculated by
n =
â
L2
L1, (4â14)
where L1 is the primary inductance that would be obtained if the secondary were
open-circuited and L2 is the secondary inductance that would be obtained if the primary
were open-circuited.
4.4 Performance Under Load
The Vector Network Analyzer (VNA) was used for characterizing microtransformers.
Because the VNA measurement is typically performed with 50 Ω loading, the results
must be re-interpreted to derive performance for other loading conditions.
Although Equation 4â1 can be used to quickly calculate the maximum attainable
transformer efficiency from measured scattering parameters, it has several shortcomings:
it assumes matched loading at every frequency point but does not actually indicate
the matched load impedance required, it does not provide information about how
big a performance hit is suffered if the frequency or load deviates from their optimal
intersections, and it does not provide the associated voltage gain. For this reason,
a set of expressions was derived that could provide more detailed information about
load-dependent performance.
4.4.1 Derivation of Efficiency and Voltage Gain for Arbitrar y Load
Modified transmission parameters AâČB âČC âČD âČ were found that represented not true
transmission parameters but instead provided relationships between the input and
output voltages and currents. These modified parameters were calculated in terms of
66
the original ABCD transmission parameters of the transformer and the load impedance
ZL. The ABCD parameters could be derived either from modeling or from measurement.
The voltage across the load and the current through it were represented by V âČ
2
and I âČ2, respectively. These quantities were found separately through network analyses
of two cascaded networks representing the same situation of a load attached to the
transformer. Relationships of each of these quantities to the input voltage V1 and input
current I1 were defined as
AâČ = V1V âČ
2
B âČ = âV1I âČ2
C âČ = I1V âČ
2
D âČ = â I1I âČ2
. (4â15)
Load-conditioned parameters AâČ and C âČ were found by cascading the transformer
network with a shunt load and leaving the output as an open circuit,
A BC D ZL
âI2 = 0
V âČ
2
I1
V1
Figure 4-4. Circuit diagram of two-port transformer transmission (ABCD) networkcascaded with shunt load.
The resulting network with shunt load was
AâČ B
C âČ D
=
A B
C D
·
1 0
1/ZL 1
=
A+ B/ZL B
C + D/ZL D
. (4â16)
Load-conditioned parameters B âČ and D âČ were found by cascading the transformer
with a series network representing the load and then shorting the output, as shown in
the figure below.
The resulting network with parallel load network was
A B âČ
C D âČ
=
A B
C D
·
1 ZL
0 1
=
A AZL + B
C CZL +D
. (4â17)
67
A BC D
ZLâI âČ2
V2 = 0
I1
V1
Figure 4-5. Circuit diagram of two-port transformer transmission (ABCD) networkcascaded with series load.
The modified parameters taken from each of the two cascaded networks together
formed the following set of relationships,
AâČ = V1V âČ
2
= A+ BZLB âČ = âV1
I âČ2
= AZL + B
C âČ = I1V âČ
2
= C + DZLD âČ = â I1
I âČ2
= CZL +D. (4â18)
Efficiency was defined as the ratio of the real power delivered from the transformer
to a load versus the real power delivered from a source to the transformer, that is,
η =Pload
Pin=
â
âV âČ
2IâČ
2
â
V1I1 (4â19)
By properties of complex numbers, the expression was simplified as
η =
(
âV âČ
2IâČ
2 â V âČ
2IâČ
2
)
/2(
V1I1 + V1I1)
/2=
1 +V âČ
2
I âČ2
I âČ2
V âČ
2
âV1V âČ
2
I1
I âČ2
â V1
I âČ2
I1V âČ
2
=1 + ZL/ZL
AâČD âČ + B âČC âČ
. (4â20)
This expression could also be written in terms of the original transformer ABCD
parameters and the load impedance,
η =ZL + ZL
(AZL + B) (CZL + D) + (AZL + B) (CZL + D)=
âZLâ
(AZL + B) (CZL + D) (4â21)
The efficiency was thus found to be a function of the load impedance and operating
frequency.
68
The voltage gain provided to the transformer to varied loads was also derived from
this analysis, simply as the inverse of AâČ,
Av =|V âČ
2||V1|
=
âŁ
âŁ
âŁ
âŁ
1
AâČ
âŁ
âŁ
âŁ
âŁ
=
âŁ
âŁ
âŁ
âŁ
ZL
AZL + B
âŁ
âŁ
âŁ
âŁ
. (4â22)
4.4.2 Conjugate Impedance Matched Loading
The maximum efficiency through the transformer occurs when the source and load
impedances attached to the transformer are conjugate matched to its input and output
impedances, respectively [57]. A generic two-port ABCD network was analyzed to
determine the ZL that would result in conjugate impedance matching for a given ABCD.
As labelled in Figure 4-6, the impedances looking into the primary and secondary
coils of the transformer were denoted Z1 and Z2, respectively, and the source and load
impedances were denoted ZS and ZL.
A BC D ZL
ZLZ2Z1ZS
Figure 4-6. Circuit diagram of two-port transformer transmission (ABCD) network withsource and load impedances ZS and ZL, respectively.
Conjugate impedance matching requires that ZS and Z1 are complex conjugate
pairs, that is,
ZS = Z1. (4â23)
The same condition is required of ZL and Z2,
Z2 = ZL. (4â24)
From network theory, the impedance looking into the transformer input port is given by
Z1 =AZL + B
CZL + D, (4â25)
69
and the impedance looking into the output port is
Z2 =DZS + B
CZS + A. (4â26)
From Equation 4â23 and Equation 4â25, the matched source impedance is written,
ZS =
(
AZL + B
CZL +D
)
(4â27)
The above expression for matched source impedance is then replaced into the
expression for output port impedance of Equation 4â26,
Z2 =D(
AZL+B
CZL+D
)
+ B
C(
AZL+B
CZL+D
)
+ A
= ZL, (4â28)
which is related to ZL from Equation 4â24. Equation 4â28 can then be algebraically
manipulated into the form,
(
AC + AC)
ZL2+
(
BC â BC + AD â AD)
ZL â(
BD + BD)
= 0, (4â29)
which is identified as a quadratic equation.
Solving the quadratic equation for ZL yields the load impedance required for the
conjugate matched impedance condition for maximum power gain. The value of Gmax , as
calculated from Equation 4â1, is identically equal to the result obtained when the value
of ZL (Equation 4â29) is replaced into Equation 4â21. However, the latter calculation
reveals the required matched load impedance, which is not otherwise known.
4.5 Summary of Transformer Design
The preceding chapter outlined considerations affecting the design of transformers
intended for switched mode power converters.
âą Efficiency was forwarded as a metric for maximizing the power delivered to theload while minimizing that dissipated in the transformer.
70
âą A two-layer hybrid combination of both interleaved and nested primary andsecondary coils was presented as a layout that would provide both strong couplingand opportunities for non-unity voltage gain.
âą Three methods of determining efficiency were discussed based on the informationrequired to calculate each: measured scattering parameters, measured ordesigned quality factors and coupling coefficient, and measured or modeledABCD parameters.
âą ABCD analysis was further used to calculate efficiency for any arbitrary loadimpedance and to determine the corresponding voltage gain.
71
CHAPTER 5FABRICATION
This chapter describes a multilevel wafer-level microfabrication process that was
specially developed as a means to realizing three-dimensional (3D) electroformed
copper components. The process was tailored to deliver the fine dimensions and
complex routing needed for microinductors and transformers with high performance in
integrated high frequency power converters. In this chapter, an overview first outlines
the fundamental steps at the heart of this microfabrication process. Several variations
to enable extended capabilities of the core process are then discussed. Details of
the major steps in the process are then provided for a deeper understanding of the
considerations motivating the selection various sequences and parameters. Scanning
electron microscope (SEM) images are frequently used in this chapter to depict features
of the microfabricated devices.
The 3D copper microfabrication process was developed in response to deficiencies
that have so far prevented air-core microinductors from being integrated with power
converters. This process was required to simultaneously achieve three goals: thick
copper windings, multilayer stacking of windings, and low capacitance between
windings. While magnetic materials have been used in other works to increase the
inductance through a given length of conductor, the air core spirals presented here
required a longer electrical path to achieve the same inductance. The length of the
coils could lead to a high series resistance. Thick copper was necessary in order to
minimize the electrical resistance through the inductors. Because the planar spiral
design occupied a large area compared to its thickness, multilayer stacking provided
the best magnetic coupling to increase inductance densities. Multilayer stacking also
enabled the complex routing schemes needed for transformers with strong magnetic
coupling between primary and secondary coils. Removal of dielectric from between
72
adjacent traces reduced the capacitance that limited the upper operating frequency.
These design decisions have been covered in greater detail in Chapters 3 and 4.
5.1 Process Overview
The microfabrication process consisted principally of two stages: an additive
stage in which copper was electroplated layer-by-layer through patterned photoresist
molds and a following subtractive stage in which the molds were removed leaving a
freestanding 3D copper structure.
During the additive stage, thick copper traces were formed via a through-mold
electroplating technique. A thin copper seed layer was first deposited across the entire
surface of the wafer to serve as a conductive base onto which thicker copper would
be electroplated. A photoresist mold was then patterned on top of the seed, and the
thick layer of copper was electroplated through the mold. These mold-filling steps were
repeated as illustrated in Figure 5-1 for each layer of the device so that structures with
three-dimensional features may be obtained.
After all desired layers were added, the fabrication process entered the subtractive
stage, during which the photoresist molds and copper seeds were removed in one of two
ways.
5.1.1 Sequential Layer Removal
Thin (10 ”m) suspended features with greater widths than thicknesses were prone
to snapping down during the wet removal process, a problem known as stiction [58]. For
wafers having such structures, the photoresist molds and copper seed layers had to be
sequentially removed in photoresist developer and copper etchant, respectively. The
sequential removal enabled the patterning of selective portions of the photoresist mold
into insulating structural elements to prevent stiction between floating traces. Figure
5-2 illustrates the progression of releasing a suspended inductor by sequential layer
removal.
73
A Layer 1 mold over copper seed B Layer 1 plated through mold.
C Layer 2 plated through mold. D Layer 3 plated through mold.
E Layer 4 plated through mold.
Figure 5-1. Illustrations of additive process stage.
A microinductor that was released by sequential layer removal with 10 ”m thick
traces and an outer diameter of 500 ”m is depicted in the scanning electron micrograph
(SEM) image of Figure 5-3. Both upper and lower winding layers are visible in this image
along with the scaffolding and support posts that aid in anchoring and propping up the
windings.
5.1.2 Ultrasonic Agitation in Solvents
If the electroplated coppers were sufficiently robust, removal both photoresist
and copper seed was accomplished through ultrasonic agitation in a photoresist
74
A Layer 4 mold and seed removed. B Layer 3 mold and seed removed.
C Layer 2 mold and seed removed. D Layer 1 mold and seed removed.
Figure 5-2. Illustrations of subtractive process stage.
Figure 5-3. SEM image of microfabricated inductor with 10 ”m thick copper windinglayers with photoresist support posts between winding layers.
75
Figure 5-4. SEM image of microfabricated inductor with 30 ”m thick copper windinglayers with upper winding layer held in place only by vias.
stripper such as acetone or a solution containing nâmethylâ 2â pyrrolidone (BAKER
PRS-3000).This simplified release method was appropriate for devices where any
suspended structures were at least 30 ”m thick and not considerably wider than thick.
Figure 5-4 shows a 600 ”m microinductor with 30 ”m thick layers, the molding layers
of which were removed by ultrasonic agitation in BAKER PRS-3000. No photoresist
support posts were required for this inductor, as the thicker traces provided ample
mechanical support to resist stiction.
5.2 Features and Variations on the Process
5.2.1 Planar Processing
The sequence of steps in this process was devised so that a flat, planar surface
would be maintained throughout the fabrication of the devices for compatibility with
planar microfabrication techniques. A consequence of the through-mold electroplating
technique was that the conductive copper seed in regions between electroplated
traces of each layer was covered by the mold. The copper seed electrically shorted
76
all traces together and had to be removed, which in turn necessitated removal of the
mold to gain access. Removing the mold and seed immediately after electroplating
would have resulted in a non-flat surface topography with recessed regions where
the mold once existed between thicker electroplated regions. This topography would
create problems when building multilayer structures: most photoresists need to be spun
on top of a flat surface with topographical disturbances much less than the desired
thickness of the photoresist layer in order to obtain a uniform photoresist thickness.
A non-uniform photoresist thickness would not develop properly since thicker regions
would underdevelop, while thinner regions will overdevelop. Also, the topography of the
surface would not allow the regions of photoresist to be in contact with the mask in the
case of contact mask lithography or would lead to regions that are exposed out of focus
in the case of projection lithography. In either case the result would be poor resolution
with diffraction of light around the areas to be exposed.
Various works have presented options for creating a planar surface above
electroplated features. Some have utilized photosensitive benzocyclobutene (BCB)
applied over the electroplated features after removal of the mold [59, 60]. BCB exhibits
redistribution of material to fill gaps between underlying features to form a planar surface
while curing [61]. Another option that has been used extensively in industry for surface
planarization while processing the copper metal layers of microprocessors is chemical
mechanical polishing (CMP).
The fabrication method described in this chapter on the other hand maintained
a planar processing surface by leaving the copper seed layers in place throughout
the additive stage and finally removing each of the seed layers during the subtractive
stage. Additionally, because the electroplating steps were timed so that the deposited
copper filled to the height of the surrounding mold, a planar surface was maintained after
electroplating each layer without the need for any reflow or CMP planarizing steps.
77
5.2.2 Photoresist as a Structural Element
One capability that differentiated this process from other multilevel metallization
processes was that portions of the photoresist mold could be left as structural
elements to provide mechanical support to the molded copper parts. The ability
to form photoresist structural elements was devised in response to finding that the
wet processing steps for the removal of the moldings caused bending and binding
of device elements to each other, a problem known as stiction [58]. In the case of
the microfabricated inductors and transformers this stiction led to electrical shorting
of windings that drastically lowered the performance of the devices. Because the
photoresist that formed the plating molds was a dielectric material with negligible
conductivity, it was usable to provide mechanical and electrical isolation between
windings.
The fabrication of the photoresist structural elements specifically required a
positive-tone photoresist, one in which exposure to ultraviolet light initiates a chemical
modification in the photoresist that makes it soluble (i.e. etchable) in a basic solution
(the developer). The capability also required use of the sequential removal method for
the subtractive stage. In this process each layer of photoresist was exposed twice. The
first exposure defined the mold. Regions of the photoresist were exposed and removed
in developer solution to form the desired mold. This photoresist mold was then exposed
a second time everywhere except the regions that would serve as structural elements.
However the photoresist was not immediately developed after the second exposure.
Instead, the process proceeded with the addition of more layers to the structure until all
parts of the device had been added. Then during the subtractive stage each mold was
removed in photoresist developer except those unexposed regions of photoresist that
became structural elements.
78
5.2.3 Substrate Versatility
The multilevel copper microfabrication process was relatively insensitive to the
choice of substrate. Structures were formed on top of both silicon and Pyrex wafers
with minimal variation of the process steps required between the different substrates.
The conductive silicon wafers needed to be electrically isolated from the copper, which
accomplished by plasma-enhanced chemical vapor deposition (PECVD) of silicon
dioxide or silicon nitride dielectric layers over the surface of the silicon. In instances
where the inductors and transformers were intended to the silicon substrate throughout
testing, reactive ion etching (RIE) was used to selectively remove regions of the
dielectric layer to electrically ground the silicon substrate with the ground components of
the copper layers. In all cases, a thin layer of titanium was sputter-deposited on top of
the silicon dioxide, silicon nitride, or Pyrex to improve the adhesion of the copper parts to
these surfaces.
The dielectric layer was also used in other instances as a sacrificial material that
allowed detachment of multilevel copper parts from the fabrication wafer. As described
in greater detail in Section 8.2, integrated power converter modules were formed by
encapsulating microfabricated inductors and a multilevel routing and interconnect
framework in epoxy. The encapsulated copper modules were then released from a
silicon substrate by etching in concentrated 49% hydrofluoric acid the layer of silicon
dioxide that insulated the two from each other. An etching time of several hours was
required for the hydrofluoric acid to fully undercut the silicon dioxide from beneath the
3 mmĂ 3 mm modules.
5.3 Process Steps
The first steps of the microfabrication process concerned the adhesion and
insulation between the substrate and the multilevel copper structures to be fabricated.
For silicon substrates a dielectric layer of silicon dioxide or silicon nitride was first
deposited over the blank wafer by plasma-enhanced chemical vapor deposition
79
(PECVD). The dielectric layer provided electrical insulation between the copper and
the conductive silicon substrate or in some cases was used as a sacrificial layer to
physically detach copper parts from the wafer after fabrication. The thickness of the
dielectric layer was varied from 200 nm up to 2 ”m depending on the intended purpose.
When the dielectric layer was used as a sacrificial material the thickest deposition was
used. When used only for electrical insulation, openings were formed in the dielectric
layer so that the the ground nodes of the copper were directly in contact with and would
ground the silicon substrate. To form the openings, resist was photolithographically
patterned on top of the dielectric and the exposed dielectric was removed by reactive ion
etching (RIE). The resist that remained after the RIE was stripped in oxygen plasma.
The waferâeither fresh Pyrex or dielectric coated siliconâthen entered the sputter
tool for cleaning and deposition of the starting seed layer. Because the sputter tool had
multiple chambers, the surface of the wafer was able to be cleaned first with a short
bombardment etch of radio-frequency (RF) excited argon ions. While remaining under
vacuum to prevent any contamination or oxidation, the wafer was transferred to another
chamber where a 50 nm thin layer of titanium was sputter deposited across the full
surface of the wafer to provide improved adhesion between the Pyrex or dielectric layer
and the copper structures. The wafer was transferred to a third chamber where a 200 nm
thick copper seed layer was sputter deposited. On subsequent layers, only the RF etch
and copper deposition were used, as titanium was only utilized for the initial deposition
on the wafer.
Except for the first layer that additionally required titanium deposition before copper,
each layer of the multilevel copper structure was added by repetition of a basic set of
steps. The steps were:
1. In-situ argon sputter etch.2. Sputter deposition of 200 nm copper seed layer.3. Coating of AZ 9245 positive tone photoresist and spinning to targeted thickness.4. Heating wafer on hotplate to drive out solvent from photoresist.
80
Table 5-1. Process parameters for passives fabrication at U.S. Army ResearchLaboratory
Step Tool Used DetailsDeposit dielectric LAM 790 SiO2 or SiN by timed deposition.Argon sputter etch Metron 3290 50 W, 40 s.Sputter Ti Metron 3290 300 W, 30 s.Sputter Cu Metron 3290 1.18 kW, 40 s.Spin photoresist SUSS MicroTec ACS200 AZ 9245 photoresist.Softbake Hotplate 95 C.Photoresist exposure SUSS MicroTec MA6 20 mW/cm2.Plasma descum Metroline M4L 200 sccm O2, 400 W, 30 s.Electroplate Cu Dynatronix DuPR 10-3-6 Timed, direct current.Drying bake Hotplate 95 C, 5 min.Skin removal Metroline M4L 200/20 sccm O2/CF4, 250 W, 5 min.
5. Alignment and contacting of mask to wafer and ultraviolet (UV) exposure ofphotoresist.
6. Development of photoresist.7. De-scum etch of residue out from trenches in photoresist mold.8. Optional second UV exposure of photoresist.9. Electrodeposition of copper.10. Heating wafer on hotplate to dry.
The second UV exposure was only used when a sequential layer removal was
required as described in Section 5.1. The tools and parameters used for each of these
steps are listed in Table 5-1. More processing parameters are discussed in Section
5.4 as some were dependent on the choice of layer thickness, which was tested in
thicknesses of 10 ”m and 30 ”m. Cross-section diagrams in Figure 5-5 illustrate how
each step of the additive process stage contributed to the building up of the multilevel
stack. After completion of the additive stage, the process entered the subtractive stage,
during which the molding was removed by either ultrasonic agitation in a solvent or
by the sequential layer removal process. Structures with thin copper layers required
sequential removal of the molding to enable parts of the photoresist mold to be used
as structural elements to prevent parts from snapping together. During the sequential
removal, the following steps were repeated until the entire molded copper structure was
released from the molding:
81
1. Develop photoresist.2. Copper etch.3. Skin removal.
Cross-section diagrams in Figure 5-6 illustrate how each step of the sequential removal
contributed to releasing the copper structure from its mold.
5.4 Special Processing Considerations
5.4.1 Sputtering
Sputter deposition of copper was required in the process to form the conductive
seed layers onto which the thick copper traces of the device would be electroplated. The
only other metal used in this process was a thin layer of titanium deposited at the start
of the process to aid in adhesion of the copper device to the substrate, which was either
Pyrex or nitride- or oxide-coated silicon. The titanium was dc magnetron sputtered at
300 W for 30 s for a thickness of roughly 50 nm over the surface of the wafer. Copper
was then sputtered on top of the titanium adhesion layer to provide the seed for copper
electroplating.
Forming subsequent layers in the process required deposition of copper onto
a surface consisting of both photoresist and electroplated copper. Obtaining good
coverage of this surface by the copper seed presented several challenges: the sputtered
copper did not always adhere well to either the photoresist or the electroplated copper,
and the film often broke along the boundaries between the electroplated copper and the
photoresist.
Adhesion of the sputtered copper film on top of electroplated copper was improved
by argon sputter etching of the electroplated copper surface immediately prior to
sputter deposition (see Section 5.4.4 for discussion). Good adhesion of the sputtered
copper film to photoresist was achieved with high power dc magnetron sputtering at
1.18 kW. In Figure 5-7, a copper trace was peeled back and flipped over, revealing
underlying photoresist posts that remained attached to the trace. The fact that each
photoresist post remained attached to the trace above itârather than to the trace below
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A Sputter deposit Ti and Cu. B Deposit, pattern, and descum photoresist.
C Flood expose photoresist. D Electroplate Cu and dry bake.
E Sputter etch surface and deposit Cu. F Deposit, pattern, and descum photoresist.
G Flood expose photoresist. H Electroplate Cu and dry bake.
I Sputter etch surface and deposit Cu. J Deposit, pattern, and descum photoresist.
K Expose photoresist with pattern. L Electroplate Cu and dry bake.
M Sputter etch surface and deposit Cu. N Deposit, pattern, and descum photoresist.
O Flood expose photoresist. P Electroplate Cu and dry bake.
Figure 5-5. Cross section diagrams of the additive process stage.
83
A Develop photoresist. B Copper etch and O2/CF4 plasma etch.
C Develop photoresist. D Copper etch and O2/CF4 plasma etch.
E Develop photoresist. F Copper etch and O2/CF4 plasma etch.
G Develop photoresist. H Copper etch.
I Titanium etch.
Figure 5-6. Cross section diagrams of the subtractive process stage.
itâindicated that adhesion of the sputtered copper onto the photoresist was better than
that of the photoresist onto the copper.
Sputtering copper at lower powers resulted in delamination of the film from the
photoresist. This problem was evident when photoresist was cured on top of the
sputtered copper film. During solvent evaporation, tension from the resist would pull at
the copper film, detaching it from the photoresist and breaking the film at the boundaries
between the underlying photoresist and electroplated copper. Accurate mask alignment
was not possible due to the shifting film blocking the underlying features. During
84
Figure 5-7. SEM of copper trace peeled back from inductor to reveal photoresist spacerblocks attached to copper. This indicated that adhesion of copper sputteredonto photoresist was better than that of photoresist spun onto copper.
development, the broken copper film would also allow photoresist developer to seep
down around and etch into lower photoresist layers, causing a widening of the mold and
electroplating of copper between traces as shown in Figure 5-8A.
At a sputtering power of 1.18 kW no breaking or shifting of the copper film was
observed and electroplating was well-confined to the molds, yielding good separation
of features such as those shown for comparison in Figure 5-8B. At sputtering powers
greater than 1.18 kW, excessive heating of the wafer caused bubbling of the photoresist.
5.4.2 Photolithography
AZ 9245 positive tone photoresist was used for its ability to form thick layers and
compatibility with the copper electroplating bath. Two separate sets of photolithography
parameters enabled the resist to be spun to a thickness of either 10 ”m or 30 ”m per
layer. In either case, the photolithography steps consisted of the following:
1. Photoresist was dispensed onto wafer and spun to obtain an even coat of uniformthickness. The time, acceleration, and speed of the spin were tailored yield the
85
A Copper deposition between featuresdue to poor seed layer adhesion
B Good isolation of features achieved asa result of improved adhesion
Figure 5-8. SEM images of copper channels. Poor adhesion of copper seed layer tophotoresist resulted in cracks between features through which copper waselectroplated where not desired.
target thickness of 10 ”m or 30 ”m. Instead of applying the thickest layers inmultiple coats, a slow spin speed and short duration were used to obtain thethickest coat in a single spin. The single spin was found to result in the mostuniform coat of surface topography.
2. The wafer with a fresh coat of photoresist was placed on a hotplate for thesoft-bake step to drive the solvent out from and cure the photoresist. Due tothe multilayer nature of this process, which called for further photolithographyand processing on top of already-patterned photoresist layers, a low soft-baketemperature of 95 C was used to avoid deformation of the already-patternedlayers that would occur at temperatures beyond 100 C.
3. Edge-bead removal was performed by spinning the wafer and applying a steadystream of acetone along the edge. The purpose was to remove the thicker beadof photoresist that pooled up around the edge of the wafer during coating to allowflush contact with photomask and to prevent outgassing that would occur in theexcessively thick bead. This step also allowed copper to be plated around the rimof the wafer for improved deposit uniformity (Section 5.4.3).
4. An additional bake on the hotplate drove solvent out from the newly formed edgeduring edge-bead removal. The acetone used for edge-bead removal tended toabsorb into and soften the photoresist around the edge. The edge needed to becured again to prevent the wafer from sticking to the photomask.
5. Rehydration of the photoresist was necessary to restore the water content thathad been baked out of the photoresist during the curing process. The water wasneeded for the photo-reaction that occurred during ultraviolet exposure to make theresist developable. To reduce the time required for rehydration and the sensitivity
86
to ambient humidity conditions, rehydration was accomplished by submerging thewafer in a dish of water.
6. The wafer was aligned to the photomask and contacted with vacuum to pull thewafer flush against the photomask. Ultraviolet (UV) exposure was then timed to theappropriate dose depending on photoresist thickness.
7. Development of photoresist was done by submersion in AZ400K potassiumhydroxide based developer. After development the wafer was rinsed in deionizedwater and blown dry with nitrogen.
8. A de-scum etch in oxygen plasma was required to remove residue out fromtrenches in photoresist mold. The scum was otherwise found to disrupt the initialelectrodeposition of copper in regions, leading to a nonuniform copper fill. Inparticular, most of the residue was found to accumulate at the ends of recessedchannels in the photoresist due to capillary wicking of the liquid developer as thewafer was dried [62].
9. An optional second exposure of the photoresist to UV enabled the layers to besequentially removed in photoresist developer during the subtractive stage ofthe process. This second exposure could optionally be masked so that someregions of the resist mold would remain as part of the final device structure. It wasimportant that the second exposure was performed following the plasma descumstep to avoid heating just-exposed resist. During exposure, diazonaphtoquinonephoto-active-compounds in the positive photoresist decomposed and releasednitrogen gas, which slowly diffused through the resist [63]. If the resist was heatedtoo soon after exposure, the excess nitrogen gas that had not yet diffused outwould expand and cause bubbling and cracking of the resist.
5.4.3 Electroplating
Copper electroplating was carried out in an acid copper sulfate bath. While
most commercially-available copper electroplating bath electrolytes have contained
proprietary concoctions of surfactants and other organic additives to improve various
deposit characteristics, such as surface smoothness and hardness, the addition agents
have also been known to co-deposit with the plated copper and cause embrittlement
or residual stress [64]. Because the inductors and transformers of this work called for
relatively long stretches of suspended copper traces, an electrolyte chemistry was
used without any additive agents in order to minimize the residual stress in the copper
deposit.
87
Table 5-2. Recipe per 1 L acid copper sulfate electroplating bath. Adapted fromRothschild [65].
Step Ingredient QuantityStart Deionized water 500 mLStir in Copper sulfate pentahydrate crystals 60 gAdd Sulfuric acid 120 mLFill Deionized water Up to 1 L total solution
In place of the additive agents, other electroplating parameters were optimized
to yield a uniform deposit. Agitation of the bath electrolyte during plating yielded the
greatest improvement to uniformity when comparing the rates of copper plating in areas
of high versus low feature density. In a still bath without agitation, regions of a wafer
with large areas of exposed copper plated at a significantly slower rate than in regions
with little copper area (mostly masked). Bath agitation was accomplished by pumping
the fluid and attaching the wafer to a horizontally-oscillating holder. The bath electrolyte
itself was also formulated with a low concentration of dissolved copper and a high
concentration of sulfuric acid to increase its throwing power, the ability of the bath to
provide a uniform deposit thickness over an irregular shapes [64]. The recipe for the
copper plating bath was adapted from the work of Rothschild [65] and is listed in Table
5-2.
A 4 mm ring of photoresist was removed around the rim of the wafer to expose
the underlying copper seed. The function of this exclusion zone was two-fold. First, it
allowed for electrical connection from the frontside of the wafer to the negative terminal
of the power supply for electroplating. The second function of the exclusion rim was
as a current baffle to provide uniform electric field strength across the wafer surface.
Because it was also in contact with the electroplating bath, copper was electroplated
onto the seed layer exposed around the perimeter. Having such a large electroplating
area around the wafer edge was found to aid in the uniformity of the deposition rate
amongst features of different dimensions across the wafer surface.
88
The anodes consisted of 0.5 in nuggets of copper with 0.04 â 0.06% phosphorus
content. The quantity of copper anode material was adjusted downward to prevent
copper ion concentration from increasing in the bath over time. Too high of a concentration
of copper ion in the bath presented the formation of wart-like nodules on the copper
surface.
Cantilever structures such as the one depicted in Figure 5-9 were co-fabricated
alongside the inductors and transformers. At up to 1 ”m long and 10 ”m thick, the
cantilevers did not exhibit any perceptible curvature after release, indicating that no
stress gradient was present throughout the thickness of the copper.
A Full 1mm cantilever B Cantilever tip
Figure 5-9. SEM images of 1 mm-long copper cantilever. Minimal residual stress ispresent in electroplated copper structures as evidenced by minimalcurvature of long copper cantilever.
5.4.4 Argon Sputter Etch
After each thick layer of copper was electrodeposited to fill the photoresist molds,
an argon sputter etch was required to clean the copper surface. This etch was required
in order to improve the adhesion between the electroplated copper and the copper seed
layer sputter deposited onto its surface. Figure 5-10 compares images of devices that
were fabricated with (left) and without (right) this argon sputter etch step.
Separation was evident between each of the layers of the devices fabricated
without the argon sputter etch as shown for example in Figure 5-10A. Although some
89
A Without sputter etch B With sputter etch
Figure 5-10. SEM images of devices fabricated with and without argon sputter etchingbetween layer depositions. Separation between layers was evident withoutthe sputter etch and was eliminated using the sputter etch.
layers remained in place (such as the one shown in the figure), many devices exhibited
catastrophic delamination during the final wet processing steps of fabrication, and the
yield was consequently low. In contrast, the devices that received the argon sputter etch
steps exhibited strong adhesion between copper layers. As shown in Figure 5-10B, the
sputter etch was effective in eliminating the separation between layers.
Argon sputter etching was performed in situ immediately prior to sputter deposition
of copper. In this manner, the etch removed the oxidized surface of the electroplated
copper, and the cleaned surface remained under vacuum until after the coated was
completed.
5.4.5 Photoresist Skin Removal
An unintended byproduct of the previously described argon sputter etch was the
alteration of the photoresist surface. The sputtering resulted in the formation of a thin,
impermeable skin on the exposed surface of the photoresist that consequently blocked
the underlying photoresist from being removed in the photoresist developer during
sequential layer removal (Section 5.1.1). In Figure 5-11A, a portion of the blocking skin
removed by physically scratching it away and the rest of the photoresist was etched in
90
acetone. The unbroken skins could be seen spanning trenches between copper traces
at the interfaces between layers.
A Without CF4 plasma etch B With CF4 plasma etch
Figure 5-11. SEM images of copper trenches. Photoresist has been etched byKOH-based developer in each case, but thin surface layers remain betweentrenches without CF4 plasma etch
These photoresist skins could not be removed by O2 plasma ashing alone but were
successfully removed by a plasma etch consisting of both O2 and CF4. Figure 5-11B by
comparison shows how one such trench should appear when the photoresist skins were
removed at each layer by the CF4 plasma etch.
5.4.6 Copper Seed Etch
After all layers were added by electrodeposition through photoresist mods, removal
of the copper seeds at each layer was necessary to electrically isolate electroplated
traces. When it was used to remove the molds, ultrasonic agitation (Section 5.1.2)
in acetone or BAKER PRS-3000 was able to break up all of the seed layers that had
been deposited on top of photoresist. The bottommost copper seed layer, however,
and each of the copper seed layers when sequential layer removal was performed,
needed to be etched away with a copper etchant. Because the seed and the thicker
traces were both composed of copper, the seed etchant also etched the traces. As
shown by the comparison between electroplated copper features before and after
seed layer removal in Figure 5-12, this etching produced noticeable roughening of the
91
copper sidewall profile, which was smoothly defined by the photoresist mold. Without
etch selectivity between seed and trace, the seed removal relied on timing since the
200 nm thick seed would be fully etched much quicker than the 10 ”m thick traces.
Ceric-ammonium-nitrate-based Cyantek CR9 chromium etchant was used to etch the
copper seeds due to its slow etch rate, which allowed easy timing of the etch to minimize
over-etching the electroplated features. Full etching of a seed layer took approximately
1 min with moderate agitation.
A Before copper etch B After copper etch
Figure 5-12. SEM images showing sidewall of copper features before and after copperetch. The sidewall is shown to be much smoother before the copper etchthan afterwards.
92
CHAPTER 6INDUCTOR CHARACTERIZATION
This chapter discusses characterization of the microfabricated inductors under
radio-frequency excitation. An overview of the testing setup provides relevant background
regarding measurement with the vector network analyzer (VNA) tool. The section on
characterization methods details how scattering data measured from the VNA were
converted to impedance characteristics. Measurements are reported first for one-port
inductors fabricated on Pyrex substrates. These results provide a broad view of the
design space in terms of the electrical effect of varying geometry parameters such
as diameters, trace widths, and spacings. Subsequent sections explore the effect of
modifying the interlayer dielectric, switching the substrate to silicon, and changing the
shape from square to circle.
6.1 Equipment and Setup
Characterization of the microinductors at radio frequencies (RF) was accomplished
using a Vector Network Analyzer (VNA). The measurements were made with either
an Agilent E8361A with useable frequency range of 10 MHz â 30 GHz or a Rohde
& Schwarz ZVA/B with a useable frequency range of 300 kHz â 8 GHz. The general
working principle of the VNA was to excite the device under test with a single frequency
signal and to sample the amplitude and phase of the incident, reflected, and transmitted
waves. For the work presented here, the excitation frequency was swept from 10 MHz
up to at least 8 GHz to obtain the full frequency-dependent behavior of the devices up to
and beyond the first resonant frequency of each. The data were recorded as complex
scattering (S) parameters, defined as various ratios of the measured wave vectors [56].
Electrical connection to the inductors and transformers was made by radio-frequency
(RF) probes with ground-signal-ground (GSG) tip footprint configuration and 150 or
200 ”m tip pitch. Fixture compensation was performed with a calibration substrate
having open, short, through, and 50 Ω load standards [66].
93
6.2 Inductor Characterization Methods
The microinductors were designed in both one-port and two-port configurations as
shown in Figure 6-1. In all cases the signal pad was 100 ”m à 100 ”m in area and was
flanked on both sides by ground pads of considerably larger area and spaced 50 ”m
apart.
A One-port B Two-port
Figure 6-1. SEM images depicting inductors with either one- port or two-portconnections.
6.2.1 One-Port Inductor Methods
The ends of an inductor in the one-port configuration were terminated at the signal
pad and at one of the adjacent ground pads. One-port characterization was convenient
in that the inductor impedance was directly reported on the screen of the vector network
analyzer (VNA), but for inductors fabricated on silicon the capacitance through the
substrate between signal and ground terminals was lumped into the measurement. Also,
because the microinductors of this work were asymmetric in that one half of the winding
was physically closer to the substrate than the top half, the one-port measurement was
furthermore sensitive to whether the top or bottom half of the winding was connected to
the signal pad. Because the substrate was held at a ground potential, the capacitance
was greater if the half of the winding closest to the signal pad was located on the
bottom.
94
Inductor data obtained with one-port measurement yielded one complex scattering
value S per frequency point. Each scattering value was converted to an impedance
value, Z , via the relationship,
Z = Z01 + S
1â S , (6â1)
where Z0 was the characteristic impedance of the measurement line; in this case
Z0 = 50 Ω.
6.2.2 Two-Port Inductor Methods
The two-port configuration was specifically utilized to identify and separate out
the effects of capacitive coupling through the substrate. Inductors in this configuration
were connected with the ends terminating at the signal pad of each port. Ground pads
still flanked the signal pads and were connected between the two ports but were not
connected by copper to either of the signal pads. This two-port configuration provided
a richer data set that enabled separation of the impedance through the signal terminals
(i.e. the inductor impedance) from the shunt impedance between the signal and ground
terminals at each port (i.e. the substrate capacitance between the connection pads).
ZS1 ZS2
ZT
Figure 6-2. Two-port inductor impedance network.
The two-port inductor impedances were modeled according to the circuit shown in
Figure 6-2, where ZT was the impedance through the inductor and ZS1 and ZS2 were
the shunt impedances to the substrate at each port. Conversion of the measured S
parameters to ABCD facilitated characterization of the two-port inductors and extraction
of the through and shunt impedances. The ABCD parameters for the circuit network
of Figure 6-2 were found using the property that the ABCD parameter matrices of
95
cascaded network sections could be multiplied together to obtain the ABCD parameters
of the overall circuit. The overall ABCD parameter matrix for the circuit with shunt
impedance ZS1 followed by series impedance ZT followed by shunt impedance ZS2 was
obtained as
A B
C D
=
1 0
1
ZS10
1 ZT
1 0
1 0
1
ZS20
=
1 + ZTZS2
ZT
1
ZS1+ 1
ZS2+ ZTZS1ZS2
1 + ZTZS1
(6â2)
From the ABCD parameters, ZT could therefore be extracted simply as
ZT = B. (6â3)
The shunt impedances ZS2 and ZS1 were then extracted by rearranging the equivalencies
for the A and D parameters, respectively,
A = 1 +ZT
ZS2; ZS2 =
ZT
Aâ 1 =B
Aâ 1 (6â4)
and
D = 1 +ZT
ZS1; ZS1 =
ZT
D â 1 =B
D â 1. (6â5)
The two-port model also enabled simulation of the impedance that would have been
measured if the inductor were excited in a one-port configuration with the other port
shorted to ground. The input impedance looking into port 1 with port 2 shorted to ground
was solved as
Z1 =1
1
ZT+ 1
ZS1
=B
D. (6â6)
Similarly, the input impedance looking into port 2 if port 1 were shorted to ground was
obtained as
Z2 =1
1
ZT+ 1
ZS2
=B
A. (6â7)
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6.2.3 Inductor Characteristics Obtained from Impedance
Inductor impedance values were split into frequency-dependent resistances and
inductances. Resistances represented the real part of the complex impedances,
R = âZ . (6â8)
Inductance was derived from the imaginary part of the complex impedance divided by
the angular frequency,
L =âZ2Ïf
. (6â9)
As discussed in Section 3.1.2, quality factor was calculated as the ratio of the imaginary
to the real part of the impedance,
Q =âZâ Z . (6â10)
The example plots of inductance, resistance, and quality factor in Figure 6-3
illustrates the frequency-dependent characteristics that were obtained by converting
measured scattering values to impedance for a typical inductor. As shown in Figure
6-3A, the inductance remained relatively flat for low frequencies at a value denoted by
Ldc . The inductance was found to decrease slightly from Ldc before rising sharply as the
frequency increased towards the self resonant frequency, SRF , of the inductor. At the
SRF the phase of the impedance wrapped and the âinductanceâ values read negative as
the impedance became capacitive. The plot of resistance in Figure 6-3B similarly shows
that the resistance reached a peak value at the SRF of the inductor. Compared to the
inductance, however, the resistance deviated to a greater extent from its dc value Rdc
prior to the peak at SRF . While the large peaks in inductance and resistance at the SRF
resulted from the effect of shunt capacitance on the series interpretation of impedance
used here, the gradual decrease in inductance and increase in resistance observed in
the region between the peaks at SRF and the flat, low-frequency values were caused by
the generation of eddy currents within the traces leading to current crowding along the
trace edges (Section 3.6.2).
97
6.3 One-Port Inductor Characterization
6.3.1 One-Port Inductors on Pyrex Substrates
One-port inductors were fabricated on Pyrex substrates with varied geometries.
Although photoresist was used to separate the upper and lower winding layers, it
was patterned into small posts to minimize its contribution to the capacitance of the
inductors. These devices were ideal for validation of the modeling and design concepts
that were presented in Chapter 3. The characteristics of several inductors of various
geometries were measured and summarized in Table 6-1. The areas, trace widths,
spacings, and numbers of turns were reported in the table based on the computer-aided
drawings (CAD) of the photomasks used in fabrication. The reported values for Ldc , Rdc ,
SRF , Qmax , and f @Qmax were averaged over the number of known-good inductors. The
yield was reported in the table as the number of known-good inductors out of the total
number of inductors of a given design that were tested. The smaller devices exhibited
greater yieldâ100% of the tested inductors up to 2.4 mm2 functioned properly. Some
larger inductors suffered from shorting between windings, and the characteristics of
those malfunctioning inductors was not recorded. The names listed in the table were
used to refer to all copies of inductors of a specific design.
Several interesting performance trends were revealed by comparing data amongst
different designs. Inductors I1 and I2 were identical in every way except for trace width
and spacingâboth had the same 60 ”m trace pitch, but one had 40 ”m trace width and
20 ”m spacing, while the other had 50 ”m width and 10 ”m spacing. Although the dc
resistance was significantly lesser for the wider-traced inductor, the maximum quality
factor was significantly greater for the narrow-traced inductor. The frequency values
related to resonance (SRF and f @Qmax) were almost equal between the two inductors,
indicating that the capacitance in the device that lead to self-resonance was dominated
by the trace length rather than proximity of adjacent traces.
98
107
108
109
â2
â1
0
1
2x 10
â7
Indu
ctan
ce
Frequency (Hz)
SRF
Ldc
A Inductance with Ldc and SRF
107
108
109
100
102
104
Res
ista
nce
Frequency (Hz)
SRF
Rdc
B Resistance with Rdc and SRF
107
108
109
â20
0
20
40
Qua
lity
Fac
tor
Frequency (Hz) f@Qmax
SRF
Qmax
C Quality factor with Qmax , f @Qmax , and SRF
Figure 6-3. Identification of inductor specifications from plots of inductance, resistance, and quality factor data obtainedfrom VNA.
Table 6-1. Comparison of measured inductor performance. Values were averaged over the number of devices tested.Area Width Spacing # turns # devices Ldc Rdc SRF f @Qmax
Name (mm2) (”m) (”m) per layer tested (nH) (Ω) (MHz) Qmax (MHz)I1 0.28 40 20 3 16/16 14.8 0.73 4290 33.0 1740I2 0.27 50 10 3 16/16 14.4 0.55 4260 27.5 1760I3 1.02 50 10 5 4/4 90.2 1.87 922 20.0 395I4 0.97 50 5 6 4/4 108 2.13 865 15.5 376I5 2.40 50 10 5 4/4 198 3.40 479 21.2 207I6 2.40 50 10 8 3/4 327 4.77 330 17.3 148I7 4.12 50 10 10 2/4 676 8.25 176 15.8 81I8 4.33 100 10 6 3/4 226 2.86 293 15.8 131I9 6.65 60 10 10 3/4 894 9.93 111 13.9 51
99
Table 6-2. Comparison of model-predicted to measured inductor performance.Analytical FastHenry Measured Analytical FastHenry Measured
Name Ldc (nH) Ldc (nH) Ldc (nH) Rdc (Ω) Rdc (Ω) Rdc (Ω)I1 14.3 14.1 14.8 0.70 0.69 0.73I2 13.1 13.8 14.4 0.56 0.55 0.55I3 89.9 89.5 90.2 1.89 1.87 1.87I4 105 108 108 2.08 2.06 2.13I5 214 205 198 3.26 3.27 3.40I6 344 343 327 4.55 4.52 4.77I7 754 747 676 7.59 7.54 8.25I8 246 251 226 2.29 2.24 2.86I9 1056 1046 894 8.31 8.24 9.93
0 200 400 6000.5
0.6
0.7
0.8
0.9
1
Current (mA)
Res
istn
ace
(Ω)
A Inductor I2 (0.5 mm Ă 0.5 mm)
0 200 400 6002
3
4
5
Current (mA)
Res
istn
ace
(Ω)
B Inductor I3 (1.0 mm Ă 1.0 mm)
0 200 400 6002.5
3
3.5
4
4.5
Current (mA)
Res
istn
ace
(Ω)
C Inductor I5 (1.5 mm Ă 1.5 mm)
Figure 6-4. Measured resistance of different-sized inductors as a function of applied dc current. Inductors tested up toonset of thermal runaway.
100
6.3.1.1 Comparison to model predictions
The low frequency inductances Ldc and resistances Rdc measured from the
inductors were compared to those values calculated from the analytical expressions
used in their design (Section 3.4) and were also compared to FastHenry simulations
(Section 3.5.2). DC resistance was calculated using a copper resistivity of 3.3 ”Ω · cm,
a value that was obtained by measuring resistance test structures that were co-fabricated
alongside the inductors. The measured, calculated, and simulated values are listed
in Table 6-2. The closest agreement between the values was found for the smaller
inductors up to about 200 nH. The larger inductors consistently measured lower
inductances and higher resistances than calculated or simulated.
6.3.1.2 Current rating
While saturation of a ferromagnetic core often limits the upper current capability of
an inductor, the air-core microinductors tested here were limited by resistive heating.
The current rating of the microinductors was tested by running successively greater
currents through the coils until the point at which excessive heating led to thermal
runaway.
Thermal runaway occurred when a stable operating current could not be maintained.
Because the rate of heat generation in the device was proportional to its electrical
resistance and the resistance of the copper also increased with temperature, this
positive feedback resulted in an unstable condition at high currents. At this point heat
generation and resistance increased without bounds until the device burnt up.
Three inductor designs of different sizes were tested for thermal runaway to
estimate their current rating: I2, I3, and I5. The devices were fabricated on a 100 mm
diameter, 500 ”m-thick Pyrex substrate and were tested while remaining attached to
the whole wafer. The wafer was placed on a large stainless steel chuck held at room
temperature, which was approximately 25 F. The resistance of each inductor at direct
current (dc) was plotted in Figure 6-4 as a function of the applied current. Inductor
101
I2 experienced thermal runaway at 600 mA, I3 at 470 mA, and I5 at 450 mA. Prior to
runaway, the photoresist between traces was seen to melt, and the copper windings of
each inductor could be seen to change color as the copper oxidized. The dc current at
which the copper of each inductor noticeably changed color was 550 mA for I2, 350 mA
for I3, and 450 mA for I5. The preceding data however were particular to the specific
setup and the actual maximum current would depend on the heat transfer characteristics
of a given application.
6.3.1.3 Interwinding capacitance
To test the effect of an interlayer dielectric on interwinding capacitance, a batch of
inductors were fabricated with the same layouts as those listed in Table 6-1 but, instead
of patterning the resist into support posts, these were fabricated with a continuous
layer of photoresist between the upper and lower winding layers. The images in Figure
6-5 illustrate the physical difference between an inductor with patterned resist support
posts and one with an interlayer of continuous photoresist. Two designs, I1 and I6, were
selected to highlight the effect of the interlayer photoresist on the measured impedance
of a small and a large inductor, respectively. Comparing the measured impedances as
plotted in Figure 6-6 for two inductors of design I1, the patterning of the photoresist into
support posts increased the self resonant frequency (SRF) from 3.77 GHz to 4.20 GHz,
an improvement of 11%. For the impedances of the two larger inductors of design I6 as
plotted in Figure 6-7, patterning the photoresist into support posts increased the SRF
from 265 MHz to 326 MHz, an increase of 23%. As a result of the increased SRF, the
measured quality factor also increased from 16.0 to 17.3. Comparing the impedances of
other designs bore similar results, in which larger inductors with more turns exhibited a
greater improvement from minimizing the interlayer dielectric through patterning of the
photoresist support posts.
102
A Patterned resist posts
B Continuous resist layer
Figure 6-5. Scanning electron micrograph (SEM) images of one inductor with patternedphotoresist support posts between upper and lower winding layers and onewith a continuous layer of photoresist between windings.
103
107
108
109
1010
101
102
103
104
Indu
ctan
ce (
nH)
Frequency (Hz)
Unpatterned layerPatterned posts
A Inductance
107
108
109
1010
100
102
104
Res
ista
nce
(Ω)
Frequency (Hz)
Unpatterned layerPatterned posts
B Resistance
107
108
109
1010
0
10
20
30
40
Qua
lity
Fac
tor
Frequency (Hz)
Unpatterned layerPatterned posts
C Quality Factor
Figure 6-6. Comparison of interlayer dielectric effect on impedance for a small inductor (design I1, outer diameterD = 500 ”m).
107
108
109
1010
101
102
103
104
Indu
ctan
ce (
nH)
Frequency (Hz)
Unpatterned layerPatterned posts
A Inductance
107
108
109
1010
100
102
104
Res
ista
nce
(Ω)
Frequency (Hz)
Unpatterned layerPatterned posts
B Resistance
107
108
109
1010
0
10
20
30
40
Qua
lity
Fac
tor
Frequency (Hz)
Unpatterned layerPatterned posts
C Quality Factor
Figure 6-7. Comparison of interlayer dielectric effect on impedance for a large inductor (design I6, outer diameterD = 1.5 mm).
104
6.3.2 One-Port Inductors on Silicon Substrates
Several iterations of inductor designs were also fabricated on silicon substrates.
As detailed in Section 3.6.1 the measured impedances of the inductors were heavily
impacted by capacitive coupling of the inductor through the substrate. Compared
to those on Pyrex substrates, all inductors fabricated on silicon exhibited lower
self-resonant frequencies (SRF ) and resonances that were highly damped by the
resistance of the substrate. The effect was dependent on the thickness of the insulating
dielectric layer between silicon and copper and on the resistivity of the substrate.
Because the capacitance through the substrate was lumped into the measured
impedance of the one-port inductors, the results that looked at substrate effects
were measured with two-port inductors in Section 6.4. Two sets of experiments were
conducted, however, with one-port inductors fabricated on silicon substrates to highlight
the effect of copper layer thickness and inductor shape on measured impedance.
6.3.2.1 Copper layer thickness: 10 ”m vs. 30 ”m
Two inductor designs (small and large) were each implemented in a version with
10 ”m thick layers of copper and in another version with 30 ”m thick layers of copper.
The smaller of the two inductor designs had an outer diameter D = 500 ”m, trace width
w = 30 ”m, spacing between traces s = 10 ”m, and n = 3 turns per layer on each
of the two winding layers. The larger had an outer diameter D = 1000 ”m, trace width
w = 30 ”m, spacing between traces s = 10 ”m, and n = 5 turns per layer on each of the
two winding layers. The vertical gap height between the upper and lower winding layers
of each inductor was equal to the thickness of each of the winding layers of that inductor.
The impedances were plotted for the smaller and larger designs in both thicknesses
in Figure 6-8 and 6-9, respectively. The measured performance parameters obtained
from each were listed in Table 6-3 for comparison. The thicker inductors of both designs
were shown to have greatly reduced low frequency resistances, resulting in greater
quality factors up to 100 MHz. The resistances of the thicker traces also showed
105
Table 6-3. Measured performance parameters of two inductor designs, eachimplemented in versions with 10 ”m and 30 ”m thick copper layers.
Design Layer Nominal Nominal Maximum Frequency forsize thickness inductance resistance quality factor maxmimum quality
Small 10 ”m 21 nH 2.0 Ω 3.9 116 MHzSmall 30 ”m 17 nH 0.25 Ω 8.7 60 MHzLarge 10 ”m 125 nH 3.9 Ω 5.1 40 MHzLarge 30 ”m 110 nH 0.85 Ω 12 28 MHz
steeper increases with frequency due to increased eddy current losses. As a result,
the frequencies at which the maximum quality factors were measured for the thicker
inductors was lower than for the thinner versions. The thicker inductors yielded slightly
lower inductances as well from reduced mutual coupling between layers as a result of
the increased vertical gap height compared to the thinner versions. The reduction was
greater between those of the smaller design since the difference in vertical gap height
was greater in proportion to its diameter.
6.3.2.2 Inductor shape: square vs. circular spirals
Another set of inductor designs was implemented in small and large diameters with
square and circular spiral layouts. All of the inductors were constructed with 30 ”m thick
copper layers, but the outer diameters were varied between the square and circular
layouts so that the larger and smaller copies of each had roughly matching inductances.
The geometric parameters are listed in Table 6-4 with the circular layouts having larger
outer diameters to offset their smaller areas.
Measurement of the impedances of each inductor revealed only minor differences
resulting from the shape of both the smaller and the larger designs as plotted in
Figures 6-8 and 6-9. The performance characteristics were extracted from this data
and listed Table 6-5. Overall, the inductance-to-resistance ratios of the circular-shaped
inductors of both sizes were improved by approximately 10%. The improvement was
also associated with a 6â8% improvement in the maximum quality factors measured for
the circular-shaped inductors.
106
Table 6-4. Geometric parameters of large and small inductors in square- andcircular-shaped spiral layouts. All were implemented with 30 ”m thick copperlayers.
Size Shape Outer diameter Trace width Trace spacing Turns per layerSmall Square 540 ”m 20 ”m 12 ”m 5Small Circular 585 ”m 20 ”m 12 ”m 5Large Square 960 ”m 32 ”m 16 ”m 6Large Circular 1015 ”m 32 ”m 16 ”m 6
Table 6-5. Measured performance parameters of small- and large-sized inductors withsquare- and circular-shaped spiral layouts.
Design Nominal Nominal Maximum Frequency forsize Shape inductance resistance quality factor maxmimum quality
Small Square 42 nH 0.60 Ω 10.8 88 MHzSmall Circular 45 nH 0.59 Ω 11.4 60 MHzLarge Square 117 nH 0.97 Ω 10.7 30 MHzLarge Circular 117 nH 0.88 Ω 11.6 30 MHz
107
107
108
109
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
10 ”m thick layers30 ”m thick layers
A Inductance
107
108
109
10â1
100
101
102
103
Res
ista
nce
(Ω)
Frequency (Hz)
10 ”m thick layers30 ”m thick layers
B Resistance
107
108
109
0
5
10
15
Qua
lity
Fac
tor
Frequency (Hz)
10 ”m thick layers30 ”m thick layers
C Quality Factor
Figure 6-8. Comparison of layer thicknesses for small (outer diameter D = 500 ”m) one-port inductor on silicon substrate.
107
108
109
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
10 ”m thick layers30 ”m thick layers
A Inductance
107
108
109
10â1
100
101
102
103
Res
ista
nce
(Ω)
Frequency (Hz)
10 ”m thick layers30 ”m thick layers
B Resistance
107
108
109
0
5
10
15
Qua
lity
Fac
tor
Frequency (Hz)
10 ”m thick layers30 ”m thick layers
C Quality Factor
Figure 6-9. Comparison of layer thicknesses for large (outer diameter D = 1000 ”m) one-port inductor on silicon substrate.
108
107
108
109
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
SquareCircle
A Inductance
107
108
109
10â1
100
101
102
103
Res
ista
nce
(Ω)
Frequency (Hz)
SquareCircle
B Resistance
107
108
109
0
5
10
15
Qua
lity
Fac
tor
Frequency (Hz)
SquareCircle
C Quality Factor
Figure 6-10. Comparison of shape of small inductor.
107
108
109
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
SquareCircle
A Inductance
107
108
109
10â1
100
101
102
103
Res
ista
nce
(Ω)
Frequency (Hz)
SquareCircle
B Resistance
107
108
109
0
5
10
15
Qua
lity
Fac
tor
Frequency (Hz)
SquareCircle
C Quality Factor
Figure 6-11. Comparison of shape of large inductor.
109
6.4 Two-Port Inductor Characterization on Silicon Substra tes
6.4.1 Capacitive Coupling through the Substrate
Compared to inductors fabricated on insulating substrates such as Pyrex, the
measurement of inductors fabricated on silicon was severely affected by capacitive
coupling of windings through the substrate. As discussed in Section 3.6.1 the effects
of this included significant reductions in self-resonance accompanied by significant
increases in the effective resistances through the inductors. Capacitive coupling
through the substrate was strongest when points of maximum potential difference were
positioned in close proximity to each other and to the substrate. Because the maximum
potential difference occurs between the end terminals of a properly functioning inductor,
the observed inductor characteristics were highly dependent on the manner in which the
measuring probe connections were made to the end terminals.
For characterization at high frequencies (> 10 MHz) the ends of the microfabricated
inductors were terminated at pads that were designed specifically to correspond to
standard radio-frequency (RF) probe tips in ground-signal-ground (GSG) configurations.
With a thin dielectric layer of silicon dioxide providing electrical isolation between
the pads and the conductive silicon substrate, capacitors were inadvertently formed
between the pads and the conductive substrate as illustrated in Figure 6-12.
The resistance through the substrate between the tightly-spaced adjacent ground
and signal pads of the one port inductors could be estimated as the resistance between
two points on the surface of an infinite conductive slab, calculated as
Rs =Ï
2Ïsp, (6â11)
with Ï being the bulk resistivity of the slab and s the lateral separation between the
points. From the above equation the resistance between two pads separated by sp =
50 ”m was calculated at approximately Rs = 300 Ω on a Ï = 10 Ω · cm silicon wafer.
In GSG configuration, the two parallel paths between the signal pad and the two
110
Cu Pad Cu Pad
Conductive Substrate
Probe Tip Probe Tip
Dielectric Layer
Figure 6-12. Diagram illustrating capacitive coupling through substrate between inductormeasurement pads.
ground pads to either side would reduce the overall substrate resistance in half to about
Rs = 150 Ω.
The inductors in this section were fabricated with a 2 ”m insulating layer of
plasma-enhanced chemical vapor deposited (PECVD) silicon dioxide between the
electroplated copper and the silicon wafer. Some had openings in the oxide for electrical
connection of the ground pads to the silicon substrate while others had a continuous
oxide layer. In either case, because the area of the ground pad was much larger,
capacitance between pads was largely determined by the size of the signal pad, which
was fixed in lateral area at 100 ”m à 100 ”m. The capacitance of the oxide layer
between the signal pad and the substrate was estimated assuming a standard parallel
plate capacitance
Cs =ǫrǫ0A
t, (6â12)
where Ç«r is the relative permittivity of the oxide layer, A is the lateral area of the pad,
and t is the thickness of the oxide layer. Assuming the PECVD silicon dioxide to have a
111
relative permittivity of Ç«r = 3.5, the capacitance between the signal pad and the silicon
was estimated at 0.15 pF.
A two-port inductor was fabricated with 30 ”m thick copper layers on a Ï =
10 Ω · cm silicon wafer. The inductor consisted of two winding layers in a circular
spiral configuration with n = 6 turns per layer, D = 940 ”m outer diameter, w = 36 ”m
trace width, and s = 15 ”m spacing between traces. The structure of the inductor
was depicted in Figure 6-1B with each of the two ports located on opposite sides
of the inductor. One of the ports, referred to as Port 1, was connected to the upper
winding layer, while the other, Port 2, was connected to the lower winding layer. The
shunt impedances between each of the ports and ground were extracted from the
measurement data according to Equations 6â4 and 6â5.
Plots of the equivalent series resistances and capacitances as functions of
frequency revealed significant differences between the shunt impedances at each port
as shown in Figure 6-13. The equivalent series capacitance at Port 2, Cs2 was greater
at a value of about 1.4 pF due to the large area of the lower winding layer to which it
was directly connected. By comparison, the equivalent series capacitance at Port 1,
Cs1, was roughly 0.7 pF and more closely represented only the capacitance between the
signal pad and the silicon substrate. The measured value of Cs1 was greater than the
estimated value of 0.15 pF, which could have resulted from deviations in the thickness
of the silicon dioxide layer or the relative permittivity. The equivalent series resistance
(ESR) of the shunt impedance at Port 2 was less than that at Port 1, Rc2 = 50 Ω vs.
Rc1 = 115 Ω, again due to the larger area of the lower winding layer that was directly
connected to Port 2. While the measured value of ESR at Port 1 was slightly less than
the estimated value of 150 Ω, this result showed that Equation 6â11 provided a simple
method of obtaining a good rough estimate.
Equations 6â6 and 6â7 were also used to calculate (from the two-port measured
data) the impedance of the inductor that would be seen at each port if the opposite port
112
had been shorted to ground. The frequency-dependent inductances, resistances, and
quality factors were plotted in Figure 6-17 for the two cases. In shorting the greater
shunt capacitance of Port 2 to ground, the one-port impedance looking into Port 1
exhibited an increased self-resonant frequency (SRF ) of 875 MHz compared to an
SRF of 554 MHz when looking into Port 2 with Port 1 shorted. The maximum quality
factor was also greater at a value of 14.6 when looking into Port 1 compared to 13.3
when looking into Port 2. These results highlighted the importance of considering all
connections to the inductors when measuring on a conductive substrate such as silicon.
6.4.2 Winding Losses
As shown in Section 6.3.2.1 by the comparison of identical inductor designs
implemented with either 10 ”m or 30 ”m thick copper layers, increases in the thicknesses
of the copper windings led to more pronounced increases in series resistance at lower
frequencies. With the increased volume of copper crossed with magnetic fields in the
inductors with 30 ”m thick traces, an attempt was made to mitigate losses due to eddy
current generation by splitting the windings into several parallel filamented traces.
The concept of filamented traces stemmed the use of Litz wires in high frequency
transformers, which feature many small parallel wires that have been bunched into one.
Filamented traces have been proposed to benefit the high frequency resistance of coils
by creating gaps across which eddy currents should not be able to âflowâ [67]. However,
experiments in this work provided evidence that simple parallel filaments exhibit nearly
identical impedance at high frequencies (10 MHzâ 10 GHz).
Two inductors were fabricated on a high resistivity (> 10000 Ω · cm) silicon wafer
with 30 ”m thick copper layers and identical geometries: two winding layers in circular
spiral configurations with n = 6 turns per layer, D = 940 ”m outer diameter, w = 36 ”m
trace width, and s = 15 ”m spacing between traces. However, as shown in Figure 6-15,
while one had solid traces like those of all other inductors presented in this work, the
other inductor featured traces that were filamented with slits. Shown in greater detail in
113
Figure 6-16, the filamented traces contained sets of two parallel 3 ”m-wide slits running
along the trace length. Copper crossbars bridged the slits every 10 to improve the
structural integrity of the coil.
The measured impedances were found to be almost indistinguishable between the
inductor with filamented traces the standard one with solid traces. Figure 6-17 compares
plots of the frequency dependent inductances, resistances, and quality factors of the
impedances through each inductor, which were extracted according to Equation 6â3 to
minimize effects due to the substrate. Due to the loss of cross-sectional area through
the traces, the low-frequency resistance of the inductor with filamented traces was
about 10% greater at 0.90 Ω vs. 0.82 Ω with solid traces. Plotted in Figure 6-18 is the
change to the measured resistance in implementing filamented traces as a percentage
of the resistance with solid traces. At about 200 MHz the resistances between the two
inductors crossed over, beyond which point the filamented traces measured up to 10%
lower resistance around 1 GHz.
114
107
108
109
1010
10â1
100
101
102
103
Cap
acita
nce
(pF
)
Frequency (Hz)
C
s2
Cs1
A Shunt Capacitance
107
108
109
1010
100
105
Res
ista
nce
(Ω)
Frequency (Hz)
R
c2
Rc1
B Equivalent Series Resistance of shuntcapacitances
Figure 6-13. Plots of shunt capacitances (Cs1 and Cs2) and equivalent series resistances (Rc1 and Rc2) of shuntcapacitances vs. frequency at Ports 1 and 2 of inductor.
107
108
109
1010
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
L
2
L1
A Inductance
107
108
109
1010
100
102
104
Res
ista
nce
(Ω)
Frequency (Hz)
R
2
R1
B Resistance
107
108
109
1010
0
5
10
15
Qua
lity
Fac
tor
Frequency (Hz)
Q
2
Q1
C Quality Factor
Figure 6-14. Plots of impedance vs. frequency for two-port inductor looking in to Port 1 (L1, R1, Q1), and looking in to Port2 (L2, R2, Q2). In each case the opposite port was shorted to ground.
115
A Inductor with solid traces B Inductor with filamented traces
Figure 6-15. SEM images depicting inductors with solid and filamented traces.
A Solid traces B Filamented traces
Figure 6-16. SEM images zoomed closer in on solid and filamented traces.
116
107
108
109
1010
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
SolidFilamented
A Inductance
107
108
109
1010
100
102
104
Res
ista
nce
(Ω)
Frequency (Hz)
SolidFilamented
B Resistance
107
108
109
1010
0
5
10
15
20
25
Qua
lity
Fac
tor
Frequency (Hz)
SolidFilamented
C Quality Factor
Figure 6-17. Plots of impedance vs. frequency for two-port inductors with filamented and with solid traces.
107
108
109
1010
â20
â10
0
10
20
Cha
nge
in r
esis
tanc
e (
% )
Frequency (Hz)
Figure 6-18. Difference between resistances through inductor with filamented vs. solid traces plotted as a percent of thesolid trace resistance.
117
6.5 Summary of Inductor Characterization
The preceding chapter presented and compared the measured characteristics of a
variety of inductors to highlight the electrical effects resulting from design decisions.
âą The inductances and resistances measured from the inductors at low frequenciesmatched well with the values calculated from the analytical expressions used intheir design.
⹠Several inductors with 10 ”m thick copper winding layers were subjected to highcurrent levels and were found to sustain up to about 500 mA before thermalrunaway caused the windings to burn up.
âą The bulk removal of photoresist from between the upper and lower winding layerswas found to increase the self-resonant frequencies of inductors by about 10â20%.
⹠Increasing the thickness of each copper winding layer from 10 ”m to 30 ”m yieldedinductors and transformers that had significantly improved direct current (dc)resistances with only slightly decreased inductances. However, the benefit ofthe thicker layers at dc was lost at frequencies greater than about 100 MHz asthe resistances of the thicker windings increased more rapidly with increasingfrequency due to increased eddy current losses in the copper.
âą Changing the shape of the inductors from square to circular provided minorimprovements of about 10% in inductance-to-resistance ratios.
âą The characterization of inductors fabricated on silicon substrates showedthat capacitive coupling to the substrate had a strong effect on the measuredperformance. In particular, higher self-resonant frequencies and quality factorswere measured by grounding the terminal connected to the lower winding layerand applying the signal at the terminal connected to the upper winding layer.
âą Splitting the inductor windings into parallel filamented windings had almost noeffect on the measured impedance of the inductor.
118
CHAPTER 7TRANSFORMER CHARACTERIZATION
This chapter discusses the methods and results of characterizing the microfabricated
transformers under radio-frequency excitation. A description of the equipment and setup
outlines the vector network analyzer tool as it was used to characterize the two-port
microtransformers. Conversion of the measured scattering parameters to impedance
parameters is then discussed as a route for interpretation of the data in terms that
were relevant to power converters. The load-dependence of the transformer efficiency
and voltage gain is addressed with appropriate mathematical tools to quantify the
dependence. The results of characterizing three microfabricated transformers is then
presented. The first two transformers were implemented with 10 ”m thick copper layers
with square spiral layouts and turns ratios of 1 : 1 and 1 : 3.5. The last transformer
was an updated 1 : 1 transformer with circular spiral coils and an improved design
implemented in 30 ”m thick copper. The performance characteristics are compared
amongst the microtransformers to highlight the measurable electrical effects associated
with the various design options.
7.1 Equipment and Setup
An Agilent E8361A Vector Network Analyzer (VNA) was used for two-port
measurement of the transformers. The VNA excited the transformer under test with
a frequency signal on one port and sampled the amplitude and phase of the incident,
reflected, and transmitted waves on both ports. Both ports were alternately excited
to fully characterize the transformer in both directions. For the work presented
here, the excitation frequency was swept from 10 MHzâ8 GHz to obtain the full
frequency-dependent behavior of the devices up to and beyond the first resonant
frequency of each. The data were recorded as complex scattering (S) parameters,
defined as various ratios of the measured wave vectors [56].
119
Electrical connection to the inductors and transformers was made by radio-frequency
(RF) probes with ground-signal-ground (GSG) tip configuration and 150 or 200 ”m tip
pitch. Fixture compensation was performed with a calibration substrate having open,
short, thru, and 50 Ω load standards [66].
7.2 Impedance Parameters
Two-port measurement of the transformers with the Vector Network Analyzer (VNA)
yielded a 2Ă 2 matrix of complex scattering parameters for each frequency point,
S11 S12
S21 S22
. (7â1)
While scattering parameters have proven to be useful in a wide variety of radio-frequency
(RF) applications such as communications systems, impedance parameters were
more appropriate for comparison with other power transformers and for extracting
performance characteristics such as coupling coefficients and turns-ratios that were
affected by design decisions.
The scattering values were converted to impedance values via the following
relationships,
Z11 = Z0(1 + S11) (1â S22) + S12S21(1â S11) (1â S22)â S12S21
, (7â2)
Z12 = Z02S12
(1â S11) (1â S22)â S12S21, (7â3)
Z21 = Z02S21
(1â S11) (1â S22)â S12S21, (7â4)
Z22 = Z0(1â S11) (1 + S22) + S12S21(1â S11) (1â S22)â S12S21
. (7â5)
The impedance parameters corresponded to the elements of the circuit diagram
drawn in Figure 7-1. For the transformers measured in this work, Z11 represented the
120
+-
+- Z21I1Z12I2
Z22Z11I1 I2
Figure 7-1. Circuit representation of two-port impedance parameters.
impedance of the primary coil, Z22 represented that of the secondary coil, and Z12 and
Z21 represented the coupling between primary and secondary coils.
The complex impedance values were then split into real and imaginary parts, and
the frequency-dependent resistances and inductances were extracted in the same
manner as for the inductors (Section 6.2.3). Frequency-dependent resistances were
reported as the real part of the complex impedances,
Rxx = âZxx , (7â6)
where the subscripts of the resistance followed from the corresponding impedance
parameters. Frequency-dependent inductance was calculated as the imaginary part of
the complex impedance divided by the angular frequency,
Lxx =âZxx2Ïf
. (7â7)
Extraction of the nominal inductance Lxx,dc , resistance Rxx,dc , and coupling
coefficients k of the transformers was based on an assumed low-frequency model
of a transformer with imperfectly coupled inductors and series resistances. The circuit
diagram for this low-frequency model was drawn in Figure 7-2. This model represented
the behavior of the transformers in the low frequency range for which the inductance and
resistance values remained constant. In all measured cases, the mutual inductances in
the forward and reverse directions, L12,dc and L21,dc , were almost identically equalâas
were R12,dc and R21,dcâindicating that the coupling between coils was the same
121
regardless of whether the transfer was from primary to secondary or in reverse. For
this reason, the mutual inductances L12,dc and L21,dc were reported as a single value Lm.
The coupling coefficient k was calculated from the nominal inductances,
k =Lm
â
L11,dcL22,dc. (7â8)
The resistances, R12,dc and R21,dc , of the mutual impedances were omitted from the
model as depicted in Figure 7-2 as these values were negligibly small since the
transformers had no magnetic cores.
L11,dc
R11,dc Lm R22,dc
L22,dc
Figure 7-2. Low frequency transformer model consisting of imperfectly coupled inductorswith series resistance.
7.3 Load-Dependent Efficiency and Voltage Gain
Although the quality factors of the primary and secondary coil could be calculated
from the measured impedances and would provide some insight into the maximum
transformer efficiency (see Section 4.2.2), the efficiency of power transfer through the
transformer was highly dependent on the load impedance. Since the vector network
analyzer (VNA) was calibrated to report scattering data in relation to 50 Ω characteristic
impedance, the efficiency and voltage gain were calculated directly from the scattering
parameter data. The efficiency, i.e. the power delivered to the load as a percent of
the power delivered into the transformer, was calculated for the 50 Ω characteristic
impedance of the VNA by
ηZ0 =|S21|2
1â |S11|2, (7â9)
122
and the voltage gain was calculated as
AZ0 =
âŁ
âŁ
âŁ
âŁ
S21
1 + S11
âŁ
âŁ
âŁ
âŁ
. (7â10)
Determination of the transformer efficiency and voltage gain under other loading
conditions was estimated via the method described in Section 4.4, in which conversion
of the scattering parameters to ABCD parameters enabled simulation of the transformer
performance given an arbitrary load. The values for efficiency and voltage gain were
calculated from the measured data and arbitrary load impedances ZL using Equations
4â21 and 4â22, respectively. Repeating the equations here for convenience, the
efficiency was calculated by
η =âZL
â
(AZL + B) (CZL + D) , (7â11)
and voltage gain was calculated by
Av =
âŁ
âŁ
âŁ
âŁ
ZL
AZL + B
âŁ
âŁ
âŁ
âŁ
. (7â12)
By sweeping the complex load impedance ZL, surfaces were obtained that provided
visual clues about the realms of impedance that would result in high efficiency or
voltage gain at a given fixed frequency. Each frequency point had a different set of
efficiency/voltage gain surfaces. By contrast, the maximum efficiency introduced in
Section 4.2 provided the value of the peak efficiency at each given frequency regardless
of the load impedance. The complex load impedance at each frequency point that would
result in maximum efficiency was referred to as the matched load, which was calculated
by solving for ZL in the quadratic equation given in Equation 4â29,
(
AC + AC)
ZL2+
(
BC â BC + AD â AD)
ZL â(
BD + BD)
= 0, (7â13)
where the overline above parameters denoted complex conjugates. The matched load
impedance was then fed back into Equations 7â11 and 7â12 to obtain the maximum
123
efficiency and corresponding voltage gain under matched load conditions, which was
identically equal to the maximum efficiency as calculated by Equation 4â1.
7.4 Characterization of Transformers with 10 ”m Thick Layers
Two transformers with 10 ”m thick copper layers were tested on Pyrex substrates: a
1 : 1 isolation transformer and a 1 : 3.5 step-up transformer, both of which had identical
50 nH primary coils. The secondary coil of the 1 : 1 transformer was designed as a
mirror image of the primary coil with the goal of providing direct current (dc) isolation
between primary and secondary with unity gain. The secondary coil of the 1 : 3.5
transformer was composed of nine additional turns on both upper and lower winding
layers that were nested within the area cleared by the primary coil. The scanning
electron micrograph (SEM) images in Figure 7-3 compare the structures of the two
transformers, showing similar layout but with more turns inside the 1 : 3.5 transformer, all
of which belonged to the secondary coil.
The layout of both transformers began with the 1 : 1 transformer, which was
designed with interleaved primary and secondary coils with 1.5 mm outer diameter,
30 ”m wide traces, 50 ”m space between traces of the same coil, 10 ”m space between
adjacent coils, 10 ”m vertical space between upper and lower winding layers, and 2
turns of each coil per layer. The secondary coil of the 1 : 3.5 transformer was extended
with an additional 9 turns per layer in the inner region of the transformer with 10 ”m
space between turns.
The frequency-dependent inductances and resistances were plotted in Figures 7-4
and 7-5 for the 1 : 1 and 1 : 3.5 transformers, respectively. For the 1 : 1 transformer,
the inductances (L11 and L22) and resistances (R11 and R22) were essentially equal
between the primary and secondary by design. The mutual inductadisnces (L12 and
L21) would have been equal to L11 and L22 if coupling were perfect between primary
and secondary but in practice were less due to imperfect coupling. For the 1 : 3.5
transformer, with its secondary winding containing many more turns, the secondary
124
A 1 : 1 transformer B 1 : 3.5 transformer
Figure 7-3. SEM images of 1 : 1 and 1 : 3.5 microtransformers. The structures of eachare similar except that the 1 : 3.5 transformer contains nine extra turnsnested within its area.
inductance L22 and resistance R22 were both much greater than the primary inductance
L11 and resistance R11. In both cases, the coupled resistances R12 and R21 were trivially
small at low frequencies and fell within the noise of the measurement, indicating that
core loss was practically nonexistent as there was no magnetic core. The coupled
resistances appeared to rise with frequency only due to capacitive coupling between the
coils affecting the phase of the coupling impedance.
7.4.1 Extraction of Nominal Inductances and Resistances
The nominal, low-frequency values for inductances and resistances were extracted
from the measured data and were listed in Table 7-1 for comparison. Also included are
data that were extracted from an improved 1 : 1 transformer with 30 ”m layers that is
discussed in Section 7.5. The primary coils of the 1 : 1 and the 1 : 3.5 transformers
proved to be identical both physically and electrically. The measurements bore out this
fact as the primary inductances L11,dc and resistances R11,dc were essentially equal
across both designs. The inductances and resistances of the secondary coil of the
1 : 1 transformer also matched that of the primary by design. The 1 : 3.5 transformer,
with its nested secondary windings, exhibited greatly increased secondary inductance
125
107
108
109
1010
101
102
103
Frequency (Hz)
Indu
ctan
ce (
nH)
107
108
109
1010
10â2
10â1
100
101
102
103
104
Frequency (Hz)
Res
ista
nce
(Ω)
L11
, L22
L12
, L21
R11
, R22
R12
, R21
Figure 7-4. Plots of frequency-dependent inductance and resistance of 1 : 1 transformerwith 10 ”m thick layers.
Table 7-1. Comparison of transformer circuit parameters.Turns Layer Primary Secondary Mutualratio thickness Area L11,dc R11,dc L22,dc R22,dc Lm k
1 : 1 10 ”m 2.4 mm2 47 nH 2.1 Ω 47 nH 2.1 Ω 41 nH 0.871 : 3.5 10 ”m 2.4 mm2 47 nH 2.1 Ω 496 nH 9.0 Ω 96 nH 0.631 : 1 30 ”m 1.08 mm2 45 nH 0.5 Ω 44 nH 0.5 Ω 41 nH 0.92
L22,dc compared to that of the 1 : 1 transformer at the expense of greater secondary dc
resistance R22,dc as well. Additionally, the coupling coefficient was significantly better
between the interleaved windings of the 1 : 1 transformer compared to that of the nested
windings of the 1 : 3.5.
126
107
108
109
1010
101
102
103
104
Frequency (Hz)
Indu
ctan
ce (
nH)
107
108
109
1010
10â2
10â1
100
101
102
103
104
Frequency (Hz)
Res
ista
nce
(Ω)
L12
, L21
L22
L11
R11
R22
R12
, R21
Figure 7-5. Plots of frequency-dependent inductance and resistance of 1 : 3.5transformer with 10 ”m thick layers
7.4.2 Load-Dependent Performance of 1 : 1 Transformer
The efficiency of the 1 : 1 transformer was plotted in Figure 7-6, both for the
as-measured case with 50 Ω loading and for the case of maximum efficiency with
matched loads at each frequency point. The peak efficiency measured with 50 Ω loading
was 84% at 350 MHz, while the maximum estimated efficiency with a matched load was
found to peak at 930 MHz with 92%. By definition, the maximum efficiency as estimated
with matched loads was greater over all frequency points than as measured with a 50 Ω
load. However, the efficiencies of the two cases most closely matched in values around
127
the peak values of both. This suggested that the value of the matched load at these
frequencies approached 50 Ω.
107
108
109
1010
0
20
40
60
80
100
Frequency (Hz)
Effi
cien
cy %
Matched Loads
50 Ω Load
Figure 7-6. Efficiency of 1 : 1 transformer for both 50 Ω and conjugate matched loads.
107
108
109
1010
0
0.2
0.4
0.6
0.8
1
Frequency (Hz)
Vol
tage
Gai
n (V
/V)
50 Ω Load
Matched Loads
Figure 7-7. Voltage gain of 1 : 1 transformer for both 50 Ω and conjugate matched loads.
The voltage gain corresponding to the same loading conditions at each frequency
was plotted in Figure 7-7. As measured with 50 Ω loading, the voltage gain was
approximately 0.8 V/V at frequencies up to 100 MHz, beyond which point the voltage
128
gain decreased with increasing frequency. With matched loads, by comparison, the
voltage gain was lower at frequencies < 45 MHz than the 50 Ω case but increased to a
peak value of 0.94 V/V at 500 MHz. In either loading case, the peak voltage gain was
found to occur at frequencies similar to those at which the peak efficiencies occurred.
107
108
109
1010
100
101
102
103
Frequency (Hz)
Mag
nitu
de o
f Loa
d Im
peda
nce
|ZL| (
Ω)
107
108
109
1010â90
â45
0
45
90
Ang
le o
f Loa
d Im
peda
nce
â Z
L (D
egre
es)
Figure 7-8. Magnitude and phase of matched load impedance for 1 : 1 transformer.
The calculated impedance of the matched load for each frequency point was plotted
in Figure 7-8 in terms of its magnitude and phase. As indicated by the phase remaining
at a negatively value of about â45 up to almost 1 GHz, the matched load impedance
had equal components of capacitance and resistance over most of the usable frequency
range. This could have been implemented as a load resistance placed in series or in
parallel with a capacitor, with values depending on the frequency to equate with the
matched load impedance.
129
0 200 400 600 800 1000 â1000â500
0500
10000
20
40
60
80
100
XL (Ω)
RL (Ω)
Effi
cien
cy (
%)
A Efficiency
0 200 400 600 800 1000 â1000â500
0500
10000.6
0.8
1
1.2
1.4
1.6
XL (Ω)
RL (Ω)
Vol
tage
Gai
n (V
/V)
B Voltage Gain
Figure 7-9. Efficiency and voltage gain of 1 : 1 transformer (10 ”m thick winding layers)plotted as functions of a complex load at 100 MHz fixed frequency.
130
By sweeping the complex load impedance for a given fixed frequency, surfaces were
obtained for the efficiency and voltage gain of the 1 : 1 transformer such as plotted in
Figure 7-9 for 100 MHz. The surface plot in Figure 7-9A showed that peak efficiency of
the 1 : 1 transformer at 100 MHz would be obtained for impedances with real resistances
less than 100 Ω and a slight capacitive component. The surface plot in Figure 7-9B
showed that the voltage gain at 100 MHz was nearly flat at 0.88 V/V over most values
of impedance, except in the region of nearly zero resistance, around which very slightly
inductive load impedances resulted in drastically reduced voltage gain and very slight
capacitive load impedances resulted in increased voltage gains.
7.4.3 Load-Dependent Performance of 1 : 3.5 Transformer
The efficiency of the 1 : 3.5 transformer was plotted in Figure 7-10, both for
the as-measured case with 50 Ω loading and for the case of maximum efficiency
with matched loads at each frequency point. The peak efficiency of 35% at 55 MHz
measured with 50 Ω loading was much lower than for the 1 : 1 transformer. However
the estimated maximum efficiency with a matched load was found to peak up to 78%
at 150 MHz. In contrast to the 1 : 1 transformer, the measured efficiency of the 1 : 3.5
transformer with 50 Ω deviated to greater extents from the maximum efficiency with
matched loads as the frequency increased away from 10 MHz. This suggested that the
value of the matched load was close to 50 Ω at 10 MHz but progressively deviated from
this value.
The voltage gain corresponding to the same loading conditions at each frequency
was plotted in Figure 7-11. A similar result was found for the voltage gain, where the
voltage gain calculated for matched loads deviated to a larger extent from that measured
with 50 Ω loading in contrast to the result with the 1 : 1 transformer. As measured with
50 Ω loading, the voltage gain was approximately 1.3 V/V only up to 15 MHz, beyond
which point the voltage gain quickly decreased with increasing frequency. With matched
loads, however, the voltage gain started low at low frequencies and increased to 3.1 V/V
131
107
108
109
1010
0
20
40
60
80
100
Frequency (Hz)
Effi
cien
cy %
Matched Loads
50 Ω Load
Figure 7-10. Efficiency of 1 : 3.5 transformer for both 50 Ω and conjugate matched loads.
107
108
109
1010
0
1
2
3
4
Frequency (Hz)
Vol
tage
Gai
n (V
/V)
Matched Loads
50 Ω Load
Figure 7-11. Voltage gain of 1 : 3.5 transformer for both 50 Ω and conjugate matchedloads.
132
at 100 MHz. In the matched load case, the peak voltage gain was found to occur at
frequencies similar to those at which the peak efficiencies occurred, whereas the peak
efficiency and voltage gain did not occur at the same frequencies for the 50 Ω load.
107
108
109
1010
101
102
103
104
Frequency (Hz)
Mag
nitu
de o
f Loa
d Im
peda
nce
|ZL| (
Ω)
107
108
109
1010â90
â45
0
45
90
Ang
le o
f Loa
d Im
peda
nce
â Z
L (D
egre
es)
Figure 7-12. Magnitude and phase of matched load impedance for 1 : 3.5 transformerwith 10 ”m thick layers.
The calculated impedance of the matched load for each frequency point was plotted
in Figure 7-12 in terms of its magnitude and phase. As indicated by the phase remaining
at a negatively value of nearly â65 up to 100 MHz, the matched load impedance was
more capacitive than for the 1 : 1 transformer. The results for the 1 : 3.5 transformer
showed in summary that a strong value capacitance in the load would be an essential
component for reaching high efficiencies and voltage gains.
By sweeping the complex load impedance for a given fixed frequency, surfaces were
obtained for the efficiency and voltage gain of the 1 : 3.5 transformer such as plotted in
133
0 200 400 600 800 1000 â1000â500
0500
10000
20
40
60
80
100
XL (Ω)
RL (Ω)
Effi
cien
cy (
%)
A Efficiency
0 200 400 600 800 1000 â1000â500
0500
10000
2
4
6
8
10
12
14
XL (Ω)
RL (Ω)
Vol
tage
Gai
n (V
/V)
B Voltage Gain
Figure 7-13. Efficiency and voltage gain of 1 : 3.5 transformer (10 ”m thick windinglayers) plotted as functions of a complex load at 100 MHz fixed frequency.
134
Figure 7-13 for 100 MHz. The surface plot in Figure 7-13A showed peak efficiencies at
100 MHz would be obtained from the 1 : 3.5 transformer for a wide range of impedances
with real resistances of 100â400 Ω and a strong capacitive reactance of 100â500 Ω. The
surface plot in Figure 7-13B showed that a voltage gain of 2 V/V could be obtained for
a wide range of impedances at 100 MHz. In the region of nearly zero resistance, loads
with capacitance of about 7.5 pF were shown to result in voltage gains of almost 14 V/V.
7.5 Characterization of Transformer with 30 ”m Thick Layers
In response to the relatively high series resistance through the coils of the
transformers presented in the previous section, an improved 1 : 1 transformer with
30 ”m thick copper windings was fabricated on a Pyrex substrate. As seen in the
scanning electron micrograph image of the transformer in Figure 7-14, the layout also
featured interleaved circular shaped spiral coils for improved inductance to resistance
ratio. Because the purpose of this design was to maximize performance of the 1 : 1
transformer without comparison to a higher turns-ratio design, a greater fill fraction was
used than for the transformer with 10 ”m thick windings, which led to higher inductance
density and better coupling. Both primary and secondary coils were laid out with the
same geometry: circular-shaped spirals with 1.1 mm outer diameter, 32 ”m trace width,
64 ”m spacing between traces of the same coil, 16 ”m spacing between adjacent coils,
30 ”m vertical gap between the upper and lower winding layers, and 4 turns of each coil
per layer.
The frequency-dependent inductances and resistances were plotted in Figure 7-15.
The agreement between the inductances L11 and L22 and between the resistances R11
and R22 verified the designed goal of the primary and secondary coils to be in all ways
equal to each other. The mutual inductances L12 and L21 dropped slightly below L11
and L22 due to imperfect coupling. The coupled resistances R12 and R21 were very low
at low frequencies, indicating the absence of core loss as there was no magnetic core,
135
Figure 7-14. SEM image of 1 : 1 microtransformer featuring 30 ”m thick copper layersand circular spiral layout. The primary and secondary coils are interleaved.
and rose with frequency only due to capacitive coupling between the coils affecting the
phase of the coupling impedance.
Nominal low-frequency parameters were extracted from the impedance data and
are reported in Table 7-1 for comparison with the transformers of Section 7.4, which
were implemented with 10 ”m thick layers. The primary and secondary inductances
(L11,dc and L22,dc ) were very similar to those of the previous 1 : 1 transformer with 10 ”m
thick layers. This thicker 1 : 1 transformer with 30 ”m layers, however, featured a 4Ă
improvement in resistances of the coils down to 0.5 Ω. The redesigned transformer
also utilized an area of 1.08 mm2, less than half that of the previous result owing to the
increased turn count (4 vs. 2). The increased utilization of the area also resulted in an
improved coupling coefficient of k = 0.92, up from the previous k = 0.87.
The efficiency of the thicker 1 : 1 transformer was plotted in Figure 7-16, both
for the as-measured case with 50 Ω loading and for the case of maximum efficiency
with matched loads at each frequency point. The peak efficiency of 90% at 333 MHz
136
107
108
109
1010
101
102
Frequency (Hz)
Indu
ctan
ce (
nH)
107
108
109
1010
10â2
10â1
100
101
102
103
Frequency (Hz)
Res
ista
nce
(Ω)
L12
, L21
R11
, R22
R12
, R21
L11
, L22
Figure 7-15. Plots of frequency-dependent inductance and resistance of 1 : 1transformer with 30 ”m thick layers.
measured with 50 Ω loading was very close to the peak efficiency of 91% with matched
loads. Compared to Figure 7-6 for the previous 1 : 1 transformer with 10 ”m thick
layers, the measured efficiencies with a 50 Ω load of the thicker transformer more
closely approached the matched load efficiency at peak values but deviated to a greater
extent at lower frequencies. The matched load efficiency of the redesigned transformer
was much improved at these lower frequencies, reaching 70% efficiency at 10 MHz as
compared to 20% in the previous generation.
The voltage gain corresponding to the same loading conditions at each frequency
was plotted in Figure 7-16. As shown in the plot, there was a high degree of overlap
137
107
108
109
1010
0
20
40
60
80
100
Frequency (Hz)
Effi
cien
cy %
Matched Loads
50 Ω Load
Figure 7-16. Efficiency of 1 : 1 transformer (30 ”m thick winding layers) as a function offrequency for both 50 Ω and conjugate matched loads.
107
108
109
1010
0
0.2
0.4
0.6
0.8
1
Frequency (Hz)
Vol
tage
Gai
n (V
/V)
Matched Loads
50 Ω Load
Figure 7-17. Voltage gain of 1 : 1 transformer (30 ”m thick winding layers) as a functionof frequency for both 50 Ω and conjugate matched loads.
138
between the voltage gains for the 50 Ω load and for the matched load. As measured
with 50 Ω loading, the voltage gain was approximately 0.90 V/V up to 180 MHz. With
matched loads, however, the voltage gain increased up to a value of 0.94 V/V at
160 MHz. Both for the 50 Ω load and for the matched loads, the voltage gain and
efficiency were each maintained at values near their peaks throughout the frequency
range from 100â400 MHz.
107
108
109
1010
100
101
102
103
Frequency (Hz)
Mag
nitu
de o
f Loa
d Im
peda
nce
|ZL| (
Ω)
107
108
109
1010â90
â45
0
45
90
Ang
le o
f Loa
d Im
peda
nce
â Z
L (D
egre
es)
Figure 7-18. Magnitude and phase of matched load impedance for 1 : 1 transformer with30 ”m thick layers.
The calculated impedance of the matched load for each frequency point was plotted
in Figure 7-18 in terms of its magnitude and phase. Like the 1 : 1 transformer with 10 ”m
thick layers, the phase remained at a value of â45 up to 1 GHz, similarly indicating that
the matched load impedance had equal components of capacitance and resistance over
most of the usable frequency range. Throughout the frequency range up to 450 MHz the
139
magnitude of the matched load impedance for the thicker redesigned transformer was
roughly half that of the transformer with 10 ”m thick layers.
By sweeping the complex load impedance for a given fixed frequency, surfaces
were obtained for the efficiency and voltage gain of the 1 : 1 transformer with 30 ”m
thick layers such as plotted in Figure 7-19 for 100 MHz. The surface plot in Figure 7-19A
showed that at 100 MHz peak efficiency would be obtained for impedances with real
resistances less than 100 Ω and a slight capacitive component. The surface plot in
Figure 7-9B showed that the voltage gain at 100 MHz was nearly flat at 0.93 V/V over
most values of impedance, except in the region of nearly zero resistance, around which
very slightly inductive load impedances resulted in drastically reduced voltage gain and
very slight capacitive load impedances resulted in increased voltage gains.
7.6 Summary of Transformer Characterization
The preceding chapter presented and compared the measured characteristics of
two inductors fabricated with 10 ”m thick copper layers with turns ratios of 1 : 1 and
1 : 3.5 and one inductor fabricated with 30 ”m thick copper layers with a turns ratio of
1 : 1.
⹠The two transformers with 10 ”m both had the identical primary coils, but thetransformer with 1 : 3.5 turns ratio had extra turns of the secondary coil nestedinto the inner area cleared by the transformer. Mutual magnetic coupling wasconsequently less for the 1 : 3.5 transformer at k = 0.63 compared to k = 0.87 forthe 1 : 1 transformer.
⹠The efficiencies and voltage gains of the transformers were shown to be highlydependent on the load. Greater efficiencies and voltage gains were found to beachievable when the loads had capacitive components. The degree of desiredcapacitance was greater for the 1 : 3.5 transformer than for the 1 : 1 transformers.As a result, the 1 : 1 transformers exhibited better efficiencies and voltage gainsthan the 1 : 3.5 transformer with 50 Ω loading as measured with the vector networkanalyzer.
140
0 200 400 600 800 1000 â1000â500
0500
10000
20
40
60
80
100
XL (Ω)
RL (Ω)
Effi
cien
cy (
%)
A Efficiency
0 200 400 600 800 1000 â1000â500
0500
1000
0.8
1
1.2
1.4
1.6
XL (Ω)
RL (Ω)
Vol
tage
Gai
n (V
/V)
B Voltage Gain
Figure 7-19. Efficiency and voltage gain of 1 : 1 transformer (30 ”m thick winding layers)plotted as functions of a complex load at 100 MHz fixed frequency.
141
CHAPTER 8PACKAGING AND TESTING WITH CIRCUITS
This chapter discusses the packaging of the microfabricated components and
their testing within power converter circuits. Two distinct tests are described. The
first utilized wire bonds to connect a microfabricated inductor onto a printed circuit
board (PCB) to be tested with a prototype 100 MHz hybrid boost converter circuit
implemented in Complimentary Metal Oxide Semiconductor (CMOS). The second
test involved microfabrication of an inductor alongside a routing circuit for connection
to a commercially-available ball grid array (BGA) boost converter and surface-mount
capacitors. In this second test, the substrate on which the inductor and copper
framework were fabricated was completely removed, resulting in a converter module
with minimal packaging overhead.
8.1 Microinductor Wire Bonded to Very High Frequency Boost C onverter
For preliminary testing with a very high frequency (VHF) power converter, a
processed Pyrex wafer was diced to form a separate chip containing a microfabricated
inductor. The chip was then affixed to a printed circuit board (PCB) with tape and the
terminal ends of the microinductor were electrically connected to the pads on the PCB
with gold wire bonds. The attached chip, depicted in Figure 8-1, was then encapsulated
in epoxy for mechanical protection.
8.1.1 About the Microinductor
The inductor utilized for this test had an outer diameter D = 520 ”m, winding
trace width w = 40 ”m, spacing between traces s = 20 ”m, two winding layers, each
with thickness t = 10 ”m, and n = 3 winding turns per layer. The impedance of
this inductor was measured with a vector network analyzer (VNA) in its as-fabricated
state before wire bonding and was then measured with an impedance analyzer after
attachment to the PCB and after wire bonding. The measurements with the VNA
were taken by probing directly to the copper pads at the terminals of the inductor and
142
represented the impedance through only the microfabricated copper inductor. A nominal
inductance of 14nH and resistance of 0.8 Ω were so measured with the VNA. The
probes of the impedance analyzer however were landed on the tin PCB pads, and so
the measurement included the impedances through the wire bonds in series with the
inductor. As plotted in Figure 8-2, the wire bonds added approximately 7 nH to the
inductance through the device as measured at the PCB pads and also contributed an
additional 0.2 Ω to the resistance.
Figure 8-1. Microinductor wire bonded to a PCB for testing with 100 MHz CMOS hybridboost converter.
8.1.2 About the Converter and Test Results
The hybrid boost converter consisted of a single switched-inductor boost stage
followed by two switched capacitor stages. It was fabricated in a 130 nm 1.2 V CMOS
process and operated at 100 MHz. Details of the converter implementation were
presented by Xue et al. [68]. With the fabricated microinductor connected in the
switched-inductor stage, the converter achieved a conversion ratio of 6 from a 1.2 V
source with up to 37% efficiency [69]. The measured converter efficiency was plotted
in Figure 8-3 as a function of load current for conversion ratios of 6 (Vout = 7 V) and
143
104
106
108
100
101
102
Frequency (Hz)
Indu
ctan
ce (
nH)
Impedance Analyzer
Network Analyzer
A Inductance
104
106
108
10â1
100
101
Frequency (Hz)
Res
ista
nce
(Ω)
Impedance Analyzer Network Analyzer
B Resistance
104
106
108
10â2
100
102
Frequency (Hz)
Qua
lity
Fac
tor
Impedance Analyzer
Network Analyzer
C Quality Factor
Figure 8-2. Plots of impedance vs. frequency for microfabricated inductor used with100 MHz hybrid boost converter. Data measured with network analyzerbefore wire bonding to PCB and measured with impedance analyzer afterwire bonding to PCB.
144
8 (Vout = 10 V) [69]. For comparison, the measured efficiency was also plotted for
the converter when using a commercially-available 43 nH surface-mount inductor.
Although the values of inductance between the two did not match, the overall efficiency
was very similar at load currents less than 1 mA between the converter using the
microinductor and that using the surface-mount inductor. At load currents greater than
1 mA, the efficiencies between the two began to diverge, with the microfabricated
inductor resulting in greater loss, due likely to its greater series resistance.
0%
5%
10%
15%
20%
25%
30%
35%
40%
0 0.5 1 1.5 2 2.5 3
fsw=50MHz, Vout=7V
fsw=50MHz, Vout=10V
fsw=45MHz, Vout=7V
fsw=45MHz, Vout=10V
Microfabricated
inductor L=25nH
Surface-mount
inductor L=43nH
Load Current (mA)
Eff
icie
nc
y
Figure 8-3. Measured efficiencies of converter as a function of load current with 1.2 Vinput source and 7 V and 10 V output voltage. Plots compare efficiencies ofconverter using microfabricated inductor to that using a surface-mountinductor. Adapted from [69].
8.2 Testing with Commercial Surface-Mount Converter
Due to the experimental nature of the very high frequency (VHF) converters,
subsequent testing of the microinductors was done using a commercially-available
converter: the Texas Instruments TPS61240 step-up converter with fixed 5 V output. In
addition to the inductor, the converter chip also required two surface-mount capacitors,
one each at the input and output nodes for filtering. To connect the microinductor,
converter chip, and capacitors a packaging method was devised to utilize the same
145
multilevel copper process to form a routing and interconnect framework surrounding the
inductors under fabrication. The multilevel copper, including both inductors and routing,
was then encapsulated and detached from the substrate, resulting in a flexible film with
intricate, embedded copper traces. The converter and capacitors were then attached to
the copper to form the completed test module.
8.2.1 About the Texas Instruments TPS61240 Converter
Featuring a switching frequency of up to 4.5 MHz, the TPS61240 was selected
because it featured the fastest switching frequency amongst boost converters that were
commercially-available at the time of this publication. As a result of the high switching
frequency, the datasheet for the converter called for an external inductor with a value of
only 1 ”H, which, while high for microinductors, was considerably less than that required
for many other converters. The switching frequency of the TPS61240 varied at run time
depending on the load current. At light loads, the converter operated in Pulse Frequency
Modulation (PFM) mode. In PFM mode, the converter switched the inductor with a train
of several pulses only as necessary to maintain an output greater than an internally-set
threshold voltage. When the output current was too great to be supported by PFM
mode, the converter automatically switched to Pulse Width Modulation (PWM) mode.
The converter chip was obtained in a die-sized ball grid array (DSBGA) package with six
solder bumps arranged on its underside with 0.4 mm pitch.
8.2.2 Module Design and Processing
The test platform for the converter consisted of a microinductor and routing that
were fabricated on a silicon wafer using the multilevel copper process detailed in
Chapter 5 with three layers of copper, each 30 ”m thick. The layout illustrated in Figure
8-4A shows the outline of the module formed in copper. Pads were also formed in
the copper for connection to the six solder bumps of the converter chip and to the
ends of the two surface-mount capacitors. The microindutor consisted of two stacked
square-shaped spiral windings with 992 ”m outer diameter, 32 ”m trace width, 20 ”m
146
spacing between traces, and 6 turns per layer. The scanning electron micrograph (SEM)
image in Figure 8-4B depicts the copper structure of the module after the molding
process. Although the manufacturerâs datasheet for the TPS61240 converter advised to
use an inductor with a minimum inductance of 1 ”H [70] the microinductor was designed
for a value of 130 nH out of concerns over the high series resistance through greater
valued microinductors.
A CAD drawing B SEM of fabricated copper
Figure 8-4. Copper layout of converter module as drawn in Computer-Aided Design(CAD) software and as fabricated on a silicon wafer.
The electroplated copper structures on the wafer surface were then coated with
Brewer Science A2-22 resist. This resist was selected for its chemical resistance to
hydrofluoric acid, which was used to separate the copper framework from the silicon
fabrication substrate. Prior to electroplating copper, the silicon wafer was first coated
by plasma-enhanced chemical vapor deposition (PECVD) of a 2 ”m thick layer of
silicon dioxide. Then a layer of titanium, which had served the purpose of improving
the adhesion of copper to the silicon dioxide, was sputter-deposited to an increased
thickness of 300nm. The silicon dioxide and titanium constituted a sacrificial layer that
was etched away in 49% hydrofluoric acid to detach the encapsulated copper from the
147
silicon substrate. Figure 8-5 depicts an example of an embedded copper framework that
was detached from a wafer.
Figure 8-5. Photograph of microfabricated copper framework encapsulated in epoxy andreleased from substrate by sacrificial layer etch.
After detachment, the bottommost layer of the multilevel copper was directly
accessible on the underside of the module, enabling electrical connection of the external
components to the copper. For stability while connecting to components and while
probing, the embedded copper film was temporarily affixed bottom-side-up with a drop of
silicone to an aluminum nitride chip. Attachment of the components was accomplished
by depositing solder paste onto the pads of the copper framework where the converter
chip and two filtering capacitors were manually positioned. The solder in the paste was
then reflowed on a hotplate set to 210 C to fix the components in place.
Figure 8-6 depicts the final converter module as it was tested with the TPS61240
converter chip and two 4.7 ”F surface mount capacitors soldered onto pads of the
embedded copper framework. As seen in the photographs in Figure 8-6, the surface
148
A Top view B Side view
Figure 8-6. Photographs of functional converter module with controller and capacitorsmounted onto multilayered copper framework.
Table 8-1. Component sizes in functional converter module.Component Lateral area Thickness VolumeTPS61240 converter 1.26 à 0.86 = 1.08 mm2 625 ”m 0.67 mm3
Filtering capacitors (each) 1 à 0.5 = 0.5 mm2 500 ”m 0.25 mm3
Microinductor 1.04 à 0.99 = 1.03 mm2 90 ”m 0.09 mm3
Total 3 à 3 = 9 mm2 700 ”m 1.98 mm3
mount components were several times thicker than the copper framework. The footprint
of the module dominated by the three pads implemented in the copper framework that
were connected to the input, output, and ground nodes of the converter. While the
inductor also had a relatively large footprint at roughly 1 mm2, an inventory of the sizes
of the various components (listed in Table 8-1) revealed that, owing to its thinness, the
inductor comprised only 4.5% of the total volume of the converter module.
8.2.3 Converter Module Testing
Before the converter chip and capacitors were connected to the module, the
microinductor (embedded in ProTek A2-22 resist and detached from the silicon
substrate) was first characterized using a Rohde & Schwarz ZVA/B vector network
analyzer (VNA) to extract its impedance with frequency swept from 1 MHzâ1 GHz. The
149
inductance, resistance, and quality factor of the inductor were plotted as functions of
frequency in Figure 8-7. The measurements showed an inductance of 124 nH and a
resistance of 0.88 Ω at low frequencies (< 2.5 MHz), and peak quality factor of 12.4 at
177 MHz. A quality factor of 3.2 was measured at 4 MHz.
With the TPS61240 converter chip and the two 4.7 ”F capacitors soldered onto the
module, needle probes were used to make electrical connection to the input, output, and
ground pads implemented in the copper framework. Two Keithley 2400 SourceMeters
were used in the test setup: one at the input acted as the source to regulate the input
voltage Vin and to measure the input currents Iin, and one at the output acted as the
load to regulate the output current at set values Iout and to measure the resulting output
voltages Vout . Input and output powers were calculated from the set and measured
voltages and currents reported by each of the SourceMeters. Efficiency ηconv was
calculated as the ratio of the output power Pout to the input power Pin,
ηconv =Pout
Pin=Vout Iout
VinIin. (8â1)
An additional high impedance probe connected to a LeCroy oscilloscope was used to
measure the voltage waveforms across various nodes in the circuit.
The measured converter efficiency ηconv was plotted in Figure 8-8 as a function of
output current for several values of input voltage. In every case the output voltage was
consistently regulated at a value near Vout = 5.05 V. The peak measured efficiency of
62.4% was obtained for an input voltage Vin = 4 V and an output current Iout = 5 mA.
The maximum measured power output was 152 mW at 58.2% efficiency with an input
voltage Vin = 4 V and an output current Iout = 30 mA. As seen in Figure 8-8, the
overall converter efficiency decreased considerably with decreasing input voltage (i.e.
increasing conversion ratio) but remained comparatively consistent across the range of
output currents. At higher output currents than those plotted in Figure 8-8 the converter
150
106
107
108
109
101
102
103
Indu
ctan
ce (
nH)
Frequency (Hz)
A Inductance
106
107
108
109
100
102
104
Res
ista
nce
(Ω)
Frequency (Hz)
B Resistance
106
107
108
109
0
5
10
15
Qua
lity
Fac
tor
Frequency (Hz)
C Quality Factor
Figure 8-7. Plots of impedance vs. frequency for microfabricated inductor used inconverter module with TPS61240 converter. Data measured with VNA afterinductor was embedded in ProTek A2-22 resist and detached from siliconsubstrate.
151
0 10 20 3030
40
50
60
70
Output current (mA)
Effi
cien
cy (
%)
Vin
=3.5V
Vin
=4.0V
Vin
=3.0V
Figure 8-8. Measured efficiency vs. output current of converter module with outputvoltage regulated at 5.05 V.
exhibited severe ripple in the output voltage, which indicated control loop instability as
the converter transitioned from the PFM mode of operation to PWM.
+âVin
L
Cout
+ VL â
Cin
+
Vout
â
Figure 8-9. Boost converter circuit diagram with marked voltages corresponding toreported measured waveforms.
Measurement of the voltage waveform across the inductor, VL as marked on
the circuit diagram in Figure 8-9, provided insight into the trends in efficiency across
operating points. As in Figure 8-10, a comparison of the inductor voltage waveforms
for different input voltages revealed a similar series of pulses in each case. The duty
cycle, the fraction of each period during which voltage was applied across the inductor,
increased with increasing conversion ratio. A pulse width of 67 ns was measured with
152
0 0.5 1 1.5â6
â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
(V
)
A Vin = 5 V
0 0.5 1 1.5â6
â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
(V
)
B Vin = 4 V
0 0.5 1 1.5â6
â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
(V
)
C Vin = 3 V
Figure 8-10. Voltage waveforms measured across the inductor in the converter modulefor several different values of input voltages.
153
Vin = 4 V, while a width of 124 ns was measured with Vin = 3 V. The longer duration
of applied voltage across the inductor resulted in reduced efficiency as there was more
time for the current through the inductor to reach its peak value, at which point no further
energy would have been stored magnetically but rather would have been dissipated
through the resistance of the coil. The current iL through a semi-ideal inductor with
inductance L and series resistance R in response to a step voltage input vin can be
represented as a function of time t by the expression,
iL (t) =vin
R
(
1â eâRL t)
. (8â2)
From the above expression, the time taken for current through an inductor to reach its
peak value is determined by the ratio R/L, with greater R and lower L contributing to
a shorter time taken to reach peak current. This helps to explain why the drop-off in
efficiency at higher conversion ratios was more drastic with the greater R/L ratio of the
microinductor than was portrayed in the datasheet with a 1 ”H surface-mount inductor
with series resistance 80 mΩ [70].
Whereas increasing the conversion ratio increased the pulse duty cycle, increasing
the output current increased only the frequency at which the series of pulses were
issued. As can be seen in comparing Figures 8-11A and 8-11C, the pulse series were
nearly identical regardless of output current. However, sampling over a longer period of
time as in Figures 8-11B and 8-11D showed that the series of pulses were issued with
greater frequency at greater output currents. The pulse frequency was also seen in the
ripple of the output voltage as in Figure 8-12, with the ripple remaining relatively equal in
magnitude across various load currents but increasing in frequency with increasing load
current.
8.3 Summary of Inductor Packaging and Testing within Conver ter Circuits
The two tests presented in this chapter demonstrated the viability of microfabricated
inductors to be used in next-generation very-high-frequency switched-mode power
154
0 0.5 1 1.5â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
VL (
V)
A Load current Iout = 10 mA
0 5 10 15 20â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
VL (
V)
B Load current Iout = 10 mA
0 0.5 1 1.5â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
VL (
V)
C Load current Iout = 30 mA
0 5 10 15 20â4
â2
0
2
4
6
8
Time (”s)
Indu
ctor
Vol
tage
VL (
V)
D Load current Iout = 30 mA
Figure 8-11. Measured voltage waveforms across the inductor for an input voltageVin = 4.0 V and output currents of Iout = 10 mA and Iout = 30 mA.Waveforms at right show single series of pulses for each load current.Longer time sampled on plots at right show multiple series of pulses.
0 20 40 60 80 1004.9
4.95
5
5.05
5.1
5.15
5.2
Time (”s)
Out
put V
olta
ge (
V)
A Load current Iout = 1 mA
0 20 40 60 80 1004.9
4.95
5
5.05
5.1
5.15
5.2
Time (”s)
Out
put V
olta
ge (
V)
B Load current Iout = 5 mA
Figure 8-12. Measured voltage waveforms at output for different load currents with inputvoltage Vin = 3.0 V.
155
converters and to enable new technologies for integrating all components with minimal
packaging overhead:
âą A 14 nH microinductor was attached to a printed circuit board (PCB) usingwire bonds and tested within a 100 MHz boost converter implemented inComplementary Metal Oxide Semiconductor (CMOS). A maximum efficiencyof 37% was obtained with a conversion ratio of 6.
âą A microinductor was fabricated with 3Ă thicker copper layers to deliver 124 nH withseries resistance similar to that of the 14 nH inductor in the previous test â an 8Ăimprovement in the inductance-to-resistance ratio. The thicker copper also enableda packaging solution whereby the microinductor and a copper routing frameworkwere embedded in resist and the fabrication substrate was removed. The inductorwas tested with a surface-mount converter and capacitors soldered onto theembedded copper. The surface-mount components together accounted for 13Ăgreater volume than that of the microinductor. A maximum efficiency of 62% wasobtained with a conversion ratio of 1.26. Accounting for the total volume of allconverter components, a maximum power density of 76 mW/mm3 was recordedfor the overall system.
156
CHAPTER 9CONCLUSION
This dissertation documented the realization of microscale air-core inductors and
transformers with high inductance densities and high efficiency for next-generation
miniaturized power converters with switching frequencies on the order of 100 MHz.
Fabrication of the components was enabled by an advanced microfabrication process
that was devised specifically to address limitations that had so far prevented air-core
microinductors from being integrated with power converters.
This chapter highlights the accomplishment of the effort to date and then outlines
several ways in which future work can build on this foundation to enable new capabilities.
9.1 Summary of Work
The inductors and transformers of this work filled the void in high quality microscale
inductive components for power converters in the very high frequency (VHF) range.
While microscale components based on magnetic films had already provided high
quality at frequencies < 10 MHz and air-core inductive components have been used
in communications applications at frequencies > 1 GHz, the multilayered thick-film
microfabricated inductors and transformers demonstrated excellent performance in
the frequencies spanning the gap between these pre-existing groups. Comparing
results obtained from the new inductors to those of prior magnetic film and air-core
examples as in Figure 9-1, the newly developed components have been shown to exhibit
excellent inductance densities and quality factors in the VHF frequency range that had
not previously been addressed by microscale inductors. The results from the multilayer
thick-film microtransformers have been similarly outstanding when compared to previous
examples as in Figure 9-2.
The research work has resulted in several major accomplishments:
âą A methodology was established for designing microinductors and microtransformerswith an emphasis on high density and high efficiency in power conversionapplications.
157
âą The design methods were shown to accurately predict the values of inductanceand resistance of a variety of components with stacked windings in sizes from0.25â2.5 mm2 and inductances from 15â350 nH.
⹠A new microfabrication process was devised that enabled the multilayer constructionof three-dimensional, high-density, freestanding copper structures with layerthicknesses from 10 ”m up to 30 ”m.
âą Air-core inductors were fabricated in the multilayer process with measuredinductance densities up to 170 nH/mm2 and quality factors as high as 33.
âą Air-core transformers were fabricated with inductance densities up to 325 nH/mm2
in a configuration for voltage gain of 3.5 with up to 78% efficiency.
âą Microfabricated inductors were tested within functional power converter circuits:a prototype step-up converter with a switching frequency of 100 MHz yielded aconversion ratio of 6 at up to 37% efficiency using a 14 nH microinductor; and acommercial surface-mount step-up converter with a maximum switching frequencyof 4 MHz yielded a conversion ratio of 1.26 at up to 62% efficiency using a 124 nHmicroinductor.
âą A substrate detachment process was devised to form a miniaturized powerconverter module with an embeded microfabricated inductor and interconnectstructure to which a commercial surface-mount converter and capacitors wereattached and tested. The power converter module produced a maximum outputpower of 152 mW from a package occupying in total less than < 2 mm3.
9.2 Lessons Learned
In addition to the major accomplishments listed above, this research also yielded
important findings that should shape any future efforts to improve microscale air-core
power inductors and transformers:
⹠Increasing the thickness of each copper winding layer from 10 ”m to 30 ”m yieldedinductors and transformers that had significantly improved direct current (dc)resistances with only slightly decreased inductances. However, the benefit ofthe thicker layers at dc was lost at frequencies greater than about 100 MHz asthe resistances of the thicker windings increased more rapidly with increasingfrequency due to increased eddy current losses in the copper. Measurements werecompared between inductors of different thicknesses in Section 6.3.2.1.
âą The bulk removal of dielectric material (e.g. photoresist) from between theupper and lower winding layers of stacked inductors increased the self-resonantfrequencies by about 10â20%.
158
Ahn, NiFe
Yamaguchi, FeAlO
Sato, FeCoBN
Song, FeZrBAg
Fukuda, NiZn
Wang, NiFe Viala, FeHfN
Flynn, NiFe
Orlando, NiFe
Lee, CoTaZr
Park, Air
Young, Air
Choi, Air
Weon, Air Yoon, Air
I2 I1
I3
I4
I5 I6 I7
I9
1
10
100
1 10 100 1000 10000
Pe
ak
Qu
ality
Fa
cto
r
Frequency for Peak Quality Factor (MHz)
Figure 9-1. Measured results of microfabricated inductors presented in this work(orange) plotted in terms of peak quality factor and the frequency at whichthe peak quality factor was obtained. Results are compared to reviewedmagnetic-film (blue) and air-core (green) inductors. Bubble size isproportional to inductance density.[8â22]
Yamaguchi, Air
Laney, Air
Zolfaghari, Air
Ng, Air Aly, Air
Mino, CoZrRe
Kurata, CoFeSiB
Yamaguchi, CoNbZr
Mino, CoZrRe
Xu, NiFe
Sullivan, NiFe
Sullivan, NiFe
Brunet, NiFe
Park, NiFe
Rassel, NiFe
Yun, NiFe
Wang, NiFe
Meyer, 1:1
Meyer, 1:3.5
0%
20%
40%
60%
80%
100%
1 10 100 1000 10000
Eff
icie
nc
y
Frequency for Maximum Efficiency
Figure 9-2. Measured results of microfabricated transformers presented in this work(orange) plotted in terms of maximum efficiency and the frequency at whichmaximum efficiency was obtained. Results are compared to reviewedmagnetic-film (blue) and air-core (green) transformers. Bubble size isproportional to voltage gain.[23â40]
159
âą Changing the shape of the microinductors from square to circular resulted in onlyminor improvements in inductance-to-resistance ratios on the order of 10%.
âą Segmenting the thick traces of an inductor horizontally into several paralleltraces of thinner widths was found to yield an almost immeasurable change tothe impedance of the inductor. The concept of filamented traces, motivated bythe stranded Litz wires found in larger scale high-frequency transformers, wasineffective in reducing the eddy currents in the windings. In order to reduce theeddy currents induced by the proximity effect between adjacent conductors, thewindings would have to be crossed in manners that increase the orthogonality ofadjacent current paths, as is achieved in Litz wires by twisting or braiding individualstrands to reduce bundle-level effects.
âą The characterization of inductors fabricated on silicon substrates demonstratedthe strong influence of capacitive coupling on the measured performancecharacteristics. Increased substrate resistance was found to dampen the resonantbehavior of the inductors and to decrease the peak quality factor.
9.3 Future Work
Building off the success presented in Chapter 8.2 in embedding and detaching
microfabricated copper inductors and interconnects from silicon wafers, the multilevel
copper process could enable a new platform for embedding the three-dimensional (3D)
inductors and transformers side-by-side with heterogeneous components all within a
high-density package.
The envisioned packaging process would consist of the following steps, which are
illustrated in Figure 9-3:
1. Fabrication of thick copper inductor, transformer, and routing framework on top ofan oxide-coated silicon substrate.
2. Population of the framework with active circuits and surface-mount componentssnapped into copper sockets.
3. Filling and coating of the framework and components with an epoxy-based pottingcompound.
4. Release of the filled package from the silicon substrate by etching the oxide outfrom between the composite and the substrate.
In this way the thick 3D inductors and transformers would placed side-by-side with
the active circuits, rather than on top as has been the case with monolithic integration or
160
A Copper framework on silicon.
B Components placed into sockets.
C Package filled with potting compound.
D Package released by sacrificial etch. E Underside showing input/output pads.
Figure 9-3. Illustrations of package assembly process.
161
chip stacking (3D integration). This configuration is advantageous for avoiding capacitive
and inductive coupling of the passives with the conductive substrates of the active
circuits.
One unique feature of this packaging technology would be the ability to form the
copper into sockets that would allow tiny components to be snap-fit into place using
with deformable copper to provide electrical conncection. This ability was motivated by
the fact that the state-of-the-art surface-mount component size as of this writing, metric
0402 (imperial 01005), with a nominal footprint of 0.4 mmĂ 0.2 mm, had dimensions of a
similar order as the thickness of the electroplated copper stack. These tiny components
have been difficult to use in industry due to misalignment and the tomb-stoning that
can occur from imbalances between the wetting characteristics at the terminals of the
component [71â74]. While the film-type surface-mount inductors of this size still have
too great of resistance (e.g., up to 8 Ω for a 68 nH inductor with a 0.6 mm à 0.3 mm
footprint [75]), the more-energy-dense surface-mount capacitors would be well-suited for
high-frequency power converters.
As a test of this concept, a power package framework was fabricated in three layers
of copper, each 30 ”m thick, that consisted of the high-density multilayer inductors
and transformers that have been discussed throughout this work along with sockets to
accept metric 0402-sized resistors and capacitors. Two such sockets are depicted in
the scanning electron micrograph (SEM) image of Figure 9-4A. In the topmost copper
layer, 20 ”m-long 10 ”m-wide teeth protruded into the socket area as depicted in Figure
9-4B. The teeth served several purposes. The first was to account for deviations in
the exact sizes of the components resulting from imperfect manufacturing tolerances.
The second purpose was to physically secure and electrically contact the component
after placement. By securing the component in place, a solder reflow could then be
performed to ensure durable contact without the possibility of the component shifting or
tomb-stoning during the reflow.
162
A Two 0402 sockets B Close-up of teeth
Figure 9-4. Scanning electron micrograph (SEM) images of metric 0402-sized coppersockets and a close-up of the copper teeth that protrude into the socket areato contact the surface-mount component.
By sizing the socket larger than the largest size expected of a component and sizing
the teeth longer than the deviation in expected component sizes, the teeth could deform
to contact a component over the entire range of sizes tolerated in its specification.
Figure 9-7 shows how the copper teeth deformed and buried into the tin contact of a
surface-mount component that was pressed to fit. The concept of deformable copper
teeth could be extended to form contacts with vertically-oriented chips.
A Horizontal deformation B Vertical deformation
Figure 9-5. Scanning electron micrograph (SEM) images of the deformable copper teethcontacting the tin pad of a surface-mount component.
163
Figure 9-6. SEM image depicting a surface-mount resistor and capacitor mounted intosockets alongside microfabricated high-density inductors.
Finally, Figure 9-6 shows a surface-mount resistor and capacitor placed into sockets
alongside a bank of four copper microinductors. To demonstrate that electrical contact
was made to these components, the impedance was measured with an Agilent HP
4294a impedance analyzer by landing probes on the copper sockets to either side of the
components. The resistance of a 47 Ω resistor and the measured capacitance of a 47 pF
capacitor were measured after each had been socketed. The measurements, plotted in
Figure 9-7 matched the expected values of these components. The sharp deviations at
the higher frequencies were the result of resonance in the measurement cables.
Forming sockets to embed surface-mount components within high-density packages
is only one example of how the versatility of the multilayer thick film copper process in
producing fine-featured 3D conductive parts could enable new capabilities across a wide
range of applications.
164
104
106
45
46
47
48
49
50
Frequency (Hz)
Res
ista
nce
(Ω)
A Resistor
104
106
42
43
44
45
46
47
Frequency (Hz)
Cap
acita
nce
(pF
)
B Capacitor
Figure 9-7. Measured resistance of 47 Ω resistor and capacitance of 47 pF capacitorafter each had been socketed.
165
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BIOGRAPHICAL SKETCH
Christopher David Meyer was born October 23, 1983 in Ft. Lauderdale, Florida
to Patricia and Donald Meyer. He grew up in Coral Springs, Florida, not far from his
birthplace, and graduated from Coral Springs High School in 2002. He attended the
University of Florida (UF), where he earned the Bachelor of Science degree cum laude
in electrical engineering with a minor in German in 2006 and the Master of Science
degree in electrical engineering with a minor in mechanical engineering in 2009.
Inspired by a graduate course on Micro-Electromechanical Systems (MEMS),
Chris began his doctoral research with contributions to the development of thin-film
thermoelectric power generators. While continuing his research on power components,
Chris spent several years on internship at the U.S. Army Research Laboratory (ARL)
in Adelphi, MD. At ARL he developed the microfabrication process that enabled the
power components presented in this dissertation. Upon graduation with the Doctor of
Philosophy degree, Chris will join ARL full-time as an electronics engineer.
In November 2011 Chris married Jennifer nee Thompson, whom he had met as an
undergraduate student at UF.
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