may 9, 2002 triumf canada1 a new e experiment at psi for the muegamma collaboration stefan ritt...

May 9, 2002 TRIUMF Canada 1

A new e experiment at PSI

For the MUEGAMMA collaborationStefan Ritt

(Paul Scherrer Institute, Switzerland)

•Motivation

•Experimental Technique

•New Electronics

•Current status

•Motivation

•Experimental Technique

•New Electronics

•Current status


Physics Motivation

• Minimal SM: Conservation of Baryons (proton decay) and Lepton Flavour (+ e+

• Super Symmetry (SUSY) theories generically predict LFV

• Processes like + e+ are not “contaminated” by SM processes and therefore very clean

• Discovered oscillations are expected to enhance LFV rate

• The search for + e+ is therefore a promising field to find physics beyond the SM

• Minimal SM: Conservation of Baryons (proton decay) and Lepton Flavour (+ e+

• Super Symmetry (SUSY) theories generically predict LFV

• Processes like + e+ are not “contaminated” by SM processes and therefore very clean

• Discovered oscillations are expected to enhance LFV rate

• The search for + e+ is therefore a promising field to find physics beyond the SM


Prediction from SUSY SU(5)

This experiment 2)

1)

1) J. Hisano et al., hep-ph/97113482) MEGA collaboration, hep-ex/9905013

• Based on observation of atmospheric neutrino anomaly

• BR(+ e+ ) 10-14

• BR(± ± ) 10-9

• Conversion( e) 10-16

• Based on observation of atmospheric neutrino anomaly

• BR(+ e+ ) 10-14

• BR(± ± ) 10-9

• Conversion( e) 10-16


10

J ust so

(GeV)M R2

141312101010

bound

Experimental

-1-2-3 11010

MSW small angle

MSW large anglesmall mass

J ust so

MSW large angle

sin 22

m

2(e

V )2

e

)

Br(

10

10

10

10

10

10

10

10

-3

-4

-5

-6

-7

-8

-9

-10

10

-11

10

10

10

10

10

10

-10

-11

-12

-13

-14

-15

MSW

larg

e an

gle

MSW

small a

ngle

~ larg

e an

gle sm

all m

ass

Connection with oscillations1)

J. Hisano and D. Nomura, Phys. Rev. D59 (1999) 116005

This experiment

favored!


Previous + e+ Experiments

Place YearUpper limit

Author

SIN (PSI), Switzerland

1977 < 1.0 10-9 A. Van der Schaaf et al.

TRIUMF, Canada

1977 < 3.6 10-9 P. Depommier et al.

LANL, USA 1979< 1.7 10-

10 W.W. Kinnison et al.

LANL, USA 1986< 4.9 10-

11 R.D. Bolton et al.

LANL, USA 1999< 1.2 10-

11

MEGA Collab., M.L. Brooks et al.

PSI~2005

~ 10-14 This Experiment

Search for Lepton-Flavour

Violation:

Search for Lepton-Flavour

Violation:


MEG Collaboration

Institute Country Main Resp. Head Scientists Students

ICEPP, Univ. of Tokyo Japan LXe Calorimeter T. Mori 12 2

Waseda University Japan Cryogenics T. Doke 5 2

INFN, Pisa Italye+ counter, trigger, M.C.

C. Bemporad 4 3

IPNS, KEK, Tsukuba JapanSupercoducting Solenoid

A. Maki 5 -

PSI SwitzerlandDrift Chamber, Beamline, DAQ

S. Ritt 4 -

BINP, Novosibirsk RussiaLXe Tests and Purification

B. Khazin 4 -

Nagoya University Japan Cryogenics K. Masuda 1 -

35 7


Time Table

1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

Planning R & D Assembly Data Taking

now

“large prototype”


Experimental MethodExperimental Method


Detector Overview

1m

e+

Liq. Xe Scintilla tionDetector

Drift Chamber

Liq. Xe Scintilla tionDetector

e+

Tim ing Counter

Stopping TargetThin S uperconducting Coil

M uon Beam

Drift Chamber

• Stopped beam of 108 s-1, 100% duty factor

• Liquid Xe calorimeter for detection

• Solenoidal magnetic spectrometer with gradient field

• Radial drift chambers for e+

momentum determination

• Timing counter for e+

• Stopped beam of 108 s-1, 100% duty factor

• Liquid Xe calorimeter for detection

• Solenoidal magnetic spectrometer with gradient field

• Radial drift chambers for e+

momentum determination

• Timing counter for e+

Ee = 52.8 MeV

Kinematics e= 180°

Eg = 52.8 MeV

e


Signal and Background• + e+ signal very clear

– E = Ee+ = 52.8 MeV

– e+ = 180°

– e+ and in time

• Background– Radiative + decays– Accidental overlap

• Detector Requirements– Excellent energy resolution– Excellent timing resolution– Good angular resolution

e

e

e

e

e

e

e


e Signature

eEe,E = 52.8MeV

eEe,E < 52.8MeV

0.9

0.92

0.94

0.96

0.98

1

1.02

0.9 0.92 0.94 0.96 0.98 1 1.02X

Y

10 14 Decays in Acceptance

X = Ee/52.8MeV

Y =

E/

52.8

MeV


Sensitivity and Background RateN 1108

T 2.2 107 s (~50 weeks)

/4 0.09

e 0.95

0.7

sel 0.8

FWHM

Ee 0.7%

E 1.4%

e 12 mrad

te 150 ps

BR(e) = (N • T • /4 • e • • sel )-1 = 0.94 10-14

Prompt Background Bpr 10-17

Accidental Background Bacc Ee • te • (E)2 • (e)2 5 10-15

Aimed resolutions:


Comparison with previous experiments

Exp./Lab

Ee/Ee %FWHM

E/E %FWHM

te (ns)

e (mrad)

Inst. Stop rate (s-1)

Duty cycle (%)

SIN (PSI) 8.7 9.3 1.4 - (4..6) x 105 100

TRIUMF 10 8.7 6.7 - 2 x 105 100

LANL 8.8 8 1.9 37 2.4 x 105 6.4

Crystal Box

8 8 1.3 87 4 x 105 (6..9)

MEGA 1.2 4.5 1.6 17 2.5 x 108 (6..7)

PSI 0.7 1.4 0.15 12 108 100


Paul Scherrer Institute

ExperimentalHall


Experimental Hall


E5 Beam Line

e

U-versionE52

Z-versionE51

AST

First Degrader

Beam transport

ASC

Detector

solenoid

• 108 /s on 55 mm2

• Neutron background measured in 1998• Two Beam tests in 2002

• 108 /s on 55 mm2

• Neutron background measured in 1998• Two Beam tests in 2002


Detector

1m

e+

Liq. Xe Scin tilla tionDetector

Drift Cham ber

Liq. Xe Scin tilla tionDetector

e+

Tim ing Counter

Stopping TargetThin S uperconducting Coil

M uon Beam

Drift Cham ber


LXe Calorimeter

• ~800l liquid Xe (3t)

• ~800 PMTs immersed in LXe

• Only scintillation light detected

• Fast response (45 ns decay time)

• High light output (70% of NaI(Tl))1)

• High uniformity compared with segmented calorimeters

• High channel occupancy will be accommodated by special trigger scheme

• ~800l liquid Xe (3t)

• ~800 PMTs immersed in LXe

• Only scintillation light detected

• Fast response (45 ns decay time)

• High light output (70% of NaI(Tl))1)

• High uniformity compared with segmented calorimeters

• High channel occupancy will be accommodated by special trigger scheme

Liq. Xe

H.V.

Vacuum

for thermal insulation

Al Honeycombwindow

PMT

Refrigerator

Cooling pipe

Signals

fillerPlastic

1.5m

1) T. Doke and K. Masuda, NIM A 420 (1999) 62


Response

3 cm

Liq. Xe

Liq. Xe

14 cm

(a)

(b)

05 10 15

2025

3035

0

10

20

30

40

50

0

2000

4000

6000

8000

10000

05

1015 20 25

3035

0

10

20

30

40

50

0

200

400

600

800

1000

1200

1400

1600

1800

52.8 MeV

52.8 MeV

• Signal is distributed over many PMTs in most cases

• Weighted mean of PMTs on the front face x ~ 4mm FWHM

• Broadness of distribution z ~ 16mm FWHM

• Timing resolution t ~ 100ps FWHM

• Energy resolution ~ 1.4% FWHMdepends on light attenuation in LXe

• Signal is distributed over many PMTs in most cases

• Weighted mean of PMTs on the front face x ~ 4mm FWHM

• Broadness of distribution z ~ 16mm FWHM

• Timing resolution t ~ 100ps FWHM

• Energy resolution ~ 1.4% FWHMdepends on light attenuation in LXe

x

z


Calorimeter Prototypes

• 32 PMTs, 2.3 l LXe• Tested with radioactive sources

51Cr, 137Cs, 54Mn, 88Y• Extrapolated resolutions at 52.8 MeV

in agreement with quoted numbers

“Small” “Large”

Measure resolutions with 40 MeV photon

beam at ETL, Tsukuba, Japan


Large Prototype• Currently largest

LXe detector in the world (224 PMTs, 150l),

• Contains all critical parts of final detector


Status of Large Prototype

• Two beam tests, many -source and cosmic runs in Tsukuba, Japan

• Light attenuation much too high (~10x)• Cause: ~3ppm of Water in Lxe • Cleaning with “hot” Xe-gas before filling

currently under investigation• Preliminary results in June ‘02

• Two beam tests, many -source and cosmic runs in Tsukuba, Japan

• Light attenuation much too high (~10x)• Cause: ~3ppm of Water in Lxe • Cleaning with “hot” Xe-gas before filling

currently under investigation• Preliminary results in June ‘02


Positron SpectrometerHomogeneous Field

e+ from +e+e+ from +e+

Gradient Field(COnstant-Bending-RAdius)

Ultra-Thin (~3g/cm2)superconducting solenoidwith 1.2 T field

Ultra-Thin (~3g/cm2)superconducting solenoidwith 1.2 T field


Drift Chamber

• 16 radial chambers with 20 wires each• Staggered cells measure both position and time• He – C2H6 gas to reduce multiple scattering• Vernier pattern to determine z coordinate

• 16 radial chambers with 20 wires each• Staggered cells measure both position and time• He – C2H6 gas to reduce multiple scattering• Vernier pattern to determine z coordinate


Prototype Test at PSI

• 0, 0.6, 0.8, 1T field

• 3 tilting angles

• Chamber ok, electronics needs improvement

• 0, 0.6, 0.8, 1T field

• 3 tilting angles

• Chamber ok, electronics needs improvement


Positron timing counter

z

(t )z L

(t )R

L(t )

Rz(t )

e+

e+

e+

Impact Point

1m

• Aimed resolution ~100ps FWHM

• Tests with cosmic confirmed 100ps FWHM

• Aimed resolution ~100ps FWHM

• Tests with cosmic confirmed 100ps FWHM

e+

Timing Counter

Stopping TargetThin Superconducting Coil

Muon Beam

Drift Chamber

http://meg.psi.ch/ subprojects/tcount/

http://meg.psi.ch/ subprojects/tcount/


Trigger ElectronicsTrigger Electronics


Trigger Requirements

Beam rate 108 s-1

Fast LXe energy sum > 45MeV2103 s-1

interaction point e+ hit point in timing counter time correlation – e+ 200 s-

1

angular corrlation – e+ 20 s-1

Beam rate 108 s-1

Fast LXe energy sum > 45MeV2103 s-1

interaction point e+ hit point in timing counter time correlation – e+ 200 s-

1

angular corrlation – e+ 20 s-1

Ee = 52.8 MeV

Kinematics e= 180°

Eg = 52.8 MeV

e

M.C.

• Total ~800 PMTs

• Common noise contributes significantly to analog sum

• AC coupling Baseline drift

• How to evaluate of shower center?

• Total ~800 PMTs

• Common noise contributes significantly to analog sum

• AC coupling Baseline drift

• How to evaluate of shower center?


Digital TriggerType1

8 channels8 channels

clck, clear

VMEInterface(Cypress)

3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit


3.3V 2.5VFADC

LVDS

FPGA

SRAM

FADC

FADC

FADC

FADC

FADC

FADC

FADC

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

48 bits output

100MHz 10bit

• All PMTs in trigger• Board hierarchy with LVDS interconnect• Use FPGA with double capacity

• All PMTs in trigger• Board hierarchy with LVDS interconnect• Use FPGA with double capacity


3.3V 2.5V

LVDS

FPGA

SRAM

LVDS

LVDS

LVDS

FPGA

FPGA

FPGA

SRAM

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

Type2

LVDS

LVDS


Baseline Subtraction

Lat

ch

Lat

ch

Lat

ch

Lat

ch

Lat

ch

BaselineSubtractionL

atch

10 bit

100 MHz Clock

-+

<thr

+

-

BaselineRegister

Uses ~120 out of 5000 logic cells

8 channels/FPGA use 20% of chip

Uses ~120 out of 5000 logic cells

8 channels/FPGA use 20% of chip

Baselinesubtracted

signal LUT10x10

Calibrated and

linearized signal


QT Algorithmoriginal

waveform

smoothed anddifferentiated (Difference Of

Samples)Threshold in DOS

Region for pedestal

evaluation

integration area

t

• Inspired by H1 Fast Track Trigger (A. Schöning)

• Hit region defined when Difference of Samples is above threshold

• Integration of original signal in hit region

• Pedestal evaluated in region before hit

• Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time

• Inspired by H1 Fast Track Trigger (A. Schöning)

• Hit region defined when Difference of Samples is above threshold

• Integration of original signal in hit region

• Pedestal evaluated in region before hit

• Time interpolated using maximum value and two neighbor values in LUT 1ns resolution for 10ns sampling time

10ns


Trigger latency

BS

BS

BS

BS

Max

Max

Max

.

.

.

T[ns] 0 50 100 110 120..200 220 230

>45MeV

e+

AND

10 stages = 1024 chn

. . .

ADC

ADC

ADC

ADC

.

.

.

Inter-board communication: 120nsTotal: 350ns (simulated)

~600 chn. / 10 bitAt 100 MHz

75 GB/sprocessing powerIn 2 VME crates

~600 chn. / 10 bitAt 100 MHz

75 GB/sprocessing powerIn 2 VME crates


Prototype board

ADCSignal-

Generator DACFPGA


DAQ ElectronicsDAQ Electronics


DAQ Requirementsn

E[MeV]50 51 52

e

t

PMTsum

e

e

e

51.5 MeV

0.511 MeV

• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)

• Timely separated ’s need waveform digitizing > 300 MHz

• If waveform digitizing gives timing <100ps, no TDCs are needed

• ’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)

• Timely separated ’s need waveform digitizing > 300 MHz

• If waveform digitizing gives timing <100ps, no TDCs are needed

~100ns

e


Domino Sampling Chip

C. Brönnimann et al., NIM A420 (1999) 264

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout• < 100ps accuracy

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout• < 100ps accuracy


Domino Ring Sampler (DRS)

input

• Free running domino wave, stopped with trigger

• Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution

• 1024 bins 150ns waveform + 350ns delay

• Free running domino wave, stopped with trigger

• Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution

• 1024 bins 150ns waveform + 350ns delay


DRS Prototype4mm

1mm

.

.

.

.

.

•0.25m Process (“CERN is using”)

•768 cells•Wafer back

July ‘02


Domino Simulation “Analog Extracted”

• 16 cells

• All paracitics included

• Domino speed: 1.5-2.2 GHz

• 16 cells

• All paracitics included

• Domino speed: 1.5-2.2 GHz


DAQ Board• 9 channels 1024 bins / 40 MHz = 230 s acceptable dead

time• Zero suppression in FPGA• QT Algorithm in FPGA (store waveform if multi-hit)• Costs per channel: ~25$ (board) + 6$ (chip)

• 9 channels 1024 bins / 40 MHz = 230 s acceptable dead time

• Zero suppression in FPGA• QT Algorithm in FPGA (store waveform if multi-hit)• Costs per channel: ~25$ (board) + 6$ (chip)


3.3V 2.5V8 channel

DRS

TriggerInput

Board inter-connect

FPGA

FPGA

SRAM

SRAM

SRAM

SRAM

FADC

8 channelDRS

8 channelDRS

FADC

8 channelDRS

Trigger BUS(2nd level tr.)

8 in

puts

triggergate

FADC

3 state switches

FPGA

SRAMshift register

40 MHz 12 bit

domino wave


DAQ Topology

PMT

FADCFPGA

triggergate

2GHz

40MHz

DC TriggerBoard

triggergate

100MHz

DSC

TriggerBoard

CPU

CPU

•LXe•e+ counter

•wires•strips

Waveformor QT readout

DAQ board

Waveformor QT readout

2nd level trigger


“Redefinition” of DAQ

Conventional New

AC coupling Baseline subtraction

Const. Fract. Discriminator

DOS – Zero crossing

ADC Numerical Integration

TDCBin interpolation (LUT)

Waveform Fitting

Scaler (250 MHz) Scaler (50 MHz)

Oscilloscope Waveform sampling

400 US$ / channel 50 US$ / channel

TDCDisc.

ADC

Scaler

Scope

FADC

FPGA

SRAM

DRS ~GHz

100 MHz


Cryogenics Design


Slow ControlHV

PC

RS

232

12345

Temperature, pressure, …

GP

IB

Valves

??? 15° C

heater

PLC

12:30 12.3

12:45 17.2

13:20 15.2

14:10 17.3

15:20 16.2

18:30 21.3

19:20 18.2

19:45 19.2

MIDASDAQ

Eth

ern

et

Terminal Server


Slow Control BusHV

Temperature, pressure, … Valves

heater

MIDASDAQ


Field Bus Solutions• CAN, Profibus, LON

available• Node with ADC >100$• Interoperatibility not

guaranteed• Protocol overhead• Local CPU? User

programmable?• How to integrate in HV?

(CAEN use CAENET)

• CAN, Profibus, LON available

• Node with ADC >100$• Interoperatibility not

guaranteed• Protocol overhead• Local CPU? User

programmable?• How to integrate in HV?

(CAEN use CAENET)


Generic node

• ADuC812 / C8051Fxxx Micro controllers with 8x12 bit ADC, 2x12 bit DAC, digital IO

• RS485 bus over flat ribbon cable

• Powered through bus• Costs ~30$• Piggy back board

• ADuC812 / C8051Fxxx Micro controllers with 8x12 bit ADC, 2x12 bit DAC, digital IO

• RS485 bus over flat ribbon cable

• Powered through bus• Costs ~30$• Piggy back board

B

RxD

9

INT

A

7

54

21

9

1

8

1 5

TC

KT

DI

TM

ST

DO

2

+3

V

4

A5 A4

1 1

P0.

2

TxD

1

P0.

4

B

+ 3V

-12V

+ 3V

6

0

3

2 2

1 6 2

1

+3

V

DG

ND

+1

2V

8

P 0

11.0

59 M

Hz

AG

ND

+3V

I/O _2

1 0

I/O _1

D E

A

RES

5V

in in

g nd g nd

/RS TP3 .4

+5VD G N D

J1

7

4

1

J1

+ 3V

J3

LED

+ 5V

0 6

+3

V

+3

V

2 2

SCS 200

A7 A6

J2

9

A2 A1

2J4

P0.

3

D I

R OR E

g nd

V c c

MAX1483

RE

SE

T

+ 5V

C 4 2 ,2uF

n c

in in

g nd

g ndn c

1 o ut

n c

8in

g nd

78L03

+ 12V

C 7 2 ,2uF

P 1

+5V

D G N D

56

23

0

P 2

4K

7R

2

1

AG

ND

-12

V

AV

+ AG

ND

1 2 .10 .2001

S C S 200

R .S CH M ID T

A0

1 o ut 8n c

C 6 2 ,2uF

RE

SE

T

C1

22

,2u

F

C9

27p

F

C 10 2 ,2uF

79L12V R 3

78L12

V R 1

J2

A3

C 3 2 ,2uF

V R 2C 2 2 ,2uF

C 1 2 ,2uF

+ 15V

-15v

4K 7R 1

Pau l-Scherrer-InstitutCH-5432 Villigen / PSI

C 112 ,2uF

C8

27p

F

C 5 2 ,2uF

17

AV

+

20

/RS

T6

2V

DD

23

P3

.35

9P

1.7

26

P3

.05

6P

0.7

29

TD

O5

3P

2.3

32

P1

.55

0P

0.5

1 6AV +

1 3A IN 6

1 0A IN 3

7A IN 0

4C P 0 +

1C P 1 -

3 3 P 2 .0

3 6 P 1 .2

3 9 P 0 .0

4 2 P 0 .1

4 5 P 3 .7

4 8 P 0 .3

19

XTA

L2

18

XTA

L1

1 5A G N D

1 2A IN 5

9A IN 2

6V R E F R

5A G N D

8A IN 1

11A IN 4

1 4A IN 7

63

DA

C1

64

DA

C0

3C P 0 -

2C P 1 +

22

TC

K

25

P3

.1

28

TD

I

31

VD

D

24

P3

.2

27

P2

.1

30

DG

ND

60

P1

.6

57

P3

.5

54

P2

.2

51

P2

.5

55

P0

.6

58

P3

.4

52

P2

.4

3 4 P 1 .4

3 7 P 1 .1

4 0 V D D

4 3 P 2 .7

3 5 P 1 .3

3 8 P 1 .0

4 1 D G N D

4 6 P 3 .6

4 7 P 0 .2

4 4 P 2 .6

21

TM

S6

1D

GN

D

49

P0

.4

6051F000

U 1

www.cygnal.comwww.cygnal.com


2 Versions

• Generic node with signal conditioning• Sub-master with power supply and PC

connection (Parallel Port, USB planned)• Integration on sensors, in crates• RS232 node with protocol translator

BUS OrientedBUS Oriented

Crate OrientedCrate Oriented

• 19” crate with custom backplane• Generic node as piggy-back• Cards for analog IO / digital IO / °C / 220V• crate connects to parallel port (USB)


Midas Slow Control Bus

• 256 nodes, 65536 nodes with one level of repeaters• Bus length ~500m opto-isolated• Boards for voltage, current, thermo couples, TTL IO, 220V

output• Readout speed: 0.3s for 1000 channels• C library, command-line utility, Midas driver, LabView driver• Nodes are “self-documenting”• Configuration parameters in EEPROM on node• Node CPU can operate autonomously for interlock and

regulation (PID) tasks (C programmable)• Nodes can be reprogrammed over network

http://midas.psi.ch/mscb

• 256 nodes, 65536 nodes with one level of repeaters• Bus length ~500m opto-isolated• Boards for voltage, current, thermo couples, TTL IO, 220V

output• Readout speed: 0.3s for 1000 channels• C library, command-line utility, Midas driver, LabView driver• Nodes are “self-documenting”• Configuration parameters in EEPROM on node• Node CPU can operate autonomously for interlock and

regulation (PID) tasks (C programmable)• Nodes can be reprogrammed over network

http://midas.psi.ch/mscb


Vin

Vout

• • • 12 times • • •

DAC

2400V

0-2400V

ADC

• Cheap and stable (<0.3V) HV system

• Regulate global external voltage

• Use series of opto-couplers

• Compensate non-linearities of opto-couplers by regulation loop

• ADC and DAC from slow control node

• Cheap and stable (<0.3V) HV system

• Regulate global external voltage

• Use series of opto-couplers

• Compensate non-linearities of opto-couplers by regulation loop

• ADC and DAC from slow control node

HV System Design


High Voltage System

C node

Op

to-c

ou

ple

rs

External HV


HV performance

• Regulates common HV source• 0-2400V, ~1mA• DAC 16bit, ADC 14bit• Current trip ~10s • Self-calibration with two high

accuracy reference voltages• Accuracy <0.3V absolute• Boards with 12 channels, crates with

192 channels• 30$/channel (+ext. HV)

• Regulates common HV source• 0-2400V, ~1mA• DAC 16bit, ADC 14bit• Current trip ~10s • Self-calibration with two high

accuracy reference voltages• Accuracy <0.3V absolute• Boards with 12 channels, crates with

192 channels• 30$/channel (+ext. HV)

Prototype


Conclusions

• Decision about feasibility of LXe calorimeter soon• Innovative electronics useful for other experiments

– FPGA-based trigger with 100MHz FADC– 2 GHz cheap waveform sampling– New slow control system MSCB

• Physics runs expected in 2005

• Decision about feasibility of LXe calorimeter soon• Innovative electronics useful for other experiments

– FPGA-based trigger with 100MHz FADC– 2 GHz cheap waveform sampling– New slow control system MSCB

• Physics runs expected in 2005

http://meg.psi.chhttp://meg.psi.ch

may 9, 2002 triumf canada1 a new e experiment at psi for the muegamma collaboration stefan ritt...

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