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Department of

Engineering Technology

LSN 12

Shift Registers

ECT 224 Digital Computer Fundamentals

ECT 224 Digital Computer [email protected]

LSN 12 – Shift Registers

• Digital circuits with data storage and data movement

functions

• Storage capacity is the total number of bits of digital

data a register can retain

– Each stage (flip-flop) can store one bit



• Shifting capability of a register allows for the

movement of data between stages of a register at a

clock edge


LSN 12 – Serial-In / Serial-Out Registers

• Data input serially right most bit first

• Uses a sequence of flip-flops to provide serial data

storage and shifting

– Connect in series where output of one flip-flop stage

connects to the input of the next flip-flop stage



• Example:

– Determine outputs

for a given input

waveform if initially

reset



• Common logic block symbol for serial I/O shift

register

– SRG = Shift ReGister


LSN 12 – Serial-In / Parallel-Out Registers

• The output of each stage is available simultaneously

on parallel output lines


LSN 12 – Serial-In / Parallel-Out Registers

• Example:

– Determine outputs for a given input waveform


LSN 12 – Parallel-In / Serial-Out Registers

• Data entered simultaneously to all stages on parallel

input lines

– SHIFT/LOAD input line

• When LOW, parallel inputs are loaded to the input of each stage

and stored on next active clock edge

• When HIGH, data is allowed to shift between stages and to the

output

_______

G1, G2, G3 disabled

G4, G5, G6 enabled

G1, G2, G3 enabled

G4, G5, G6 disabled


LSN 12 – Parallel-In / Serial-Out Registers

• Example:

– Determine output for a given input sequence and based

upon the state of the SHIFT/LOAD line_______


LSN 12 – Bidirectional Shift Register

• Data is able to be shifted to the right or left depending

upon gating logic

– RIGHT/LEFT input line______


LSN 12 – Bidirectional Shift Register

• Example:

– Assuming that

• Q0 = 1, Q1 = 1, Q2 = 0, and Q3 = 1

• Input line is LOW


LSN 12 – Shift Register Applications

• Time delay

– Serial in / serial out

• Delay = n ( 1/fclk)

– Example:

• Determine the time delay for a 4-bit serial to parallel shift register

between the input signal and each output signal

Number of stages

Clock period


LSN 12 – Shift Register Applications

• Parallel-to-serial / serial-to-parallel data conversion

– Universal Asynchronous Receiver Transmitter (UART)

• Data transmitted from microprocessor based systems in parallel

form

• Often must communicate with external devices expecting data in

serial form

– UARTs contain a parallel-to-serial converter and a serial-to-parallel

converter


LSN 12 – Shift Register Counters

• Shift register with feedback from serial output to

serial input

– Specified sequence of states

• Johnson Counter

– Uses the compliment of the output as the feedback term

– Produces a modulus of 2n, where n is the number of sages

Clock Pulse Q0 Q1 Q2 Q3

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1



– Ring Counter

• The shift register output is used as the feedback term

• Load a sequence of bits into the counter and the sequence is shifted

one place around the “ring” at each clock edge

Clock Pulse Q0 Q1 Q2 Q3 Q4

0 1 0 0 0 0

1 0 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

4 0 0 0 0 1


LSN 12 – Homework

• Reading

– Chapter 9.1 – 9.7

• Assignment – HW13

– Chapter 9, problems 5, 10, 13, 21

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