chapter 9: shift registers

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1 1 Chapter 9: Shift Registers 樹德科技大學 資訊工程系 Shi-Huang Chen Fall 2010 2 樹德科技大學 資訊工程學系 Dept. of CSIE, Shu-Te University Outline Basic Shift Register Functions Serial In/Serial Out Shift Registers Serial In/Parallel Out Shift Registers Parallel In/Serial Out Shift Registers Parallel In/Parallel Out Shift Registers Bi-directional Shift Registers Shift Register Counters Shift Register Applications

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Page 1: Chapter 9: Shift Registers

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Chapter 9: Shift Registers

樹德科技大學 資訊工程系

Shi-Huang Chen

Fall 2010

2

樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Outline

Basic Shift Register FunctionsSerial In/Serial Out Shift Registers Serial In/Parallel Out Shift Registers Parallel In/Serial Out Shift Registers Parallel In/Parallel Out Shift RegistersBi-directional Shift RegistersShift Register Counters Shift Register Applications

Page 2: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Basic Shift Register Functions

Data StorageData MovementD flip-flops are use to store and move data

The flip-flop as a storage element

4

樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Basic Shift Register Functions

Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.)

Data in Data in

Data in

Data in

Data in

Data out Data out Data out

Data out Data out

Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out

Parallel in/parallel outSerial in/parallel out Rotate right Rotate left

Page 3: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Shift registers are available in IC form or can be constructed from discrete flip-flops as is shown here with a five-bit serial-in serial-out register.

C

FF0

CLK

C

FF1

C

FF2

C

FF4

D0 D1 D2 D4

Serialdataoutput

Serialdatainput

C

FF3

D3 Q4Q0 Q1 Q2 Q3

Each clock pulse will move an input bit to the next flip-flop. For example, a 1 is shown as it moves across.

1 1 1 1 1 1

CLKCLKCLKCLKCLK

6

樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Four bits (1010) being entered serially into the register (1).

Page 4: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Four bits (1010) being entered serially into the register (2).

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Four bits (1010) being entered serially into the register (3).

Page 5: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Four bits (1010) being serially shifted out of the register and replaced by all zeros (1)

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Four bits (1010) being serially shifted out of the register and replaced by all zeros (2)

Page 6: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Four bits (1010) being serially shifted out of the register and replaced by all zeros (3)

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Serial Out Shift Registers

Logic symbol for an 8-bit serial in/serial out shift register.

Page 7: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Parallel Out Shift Registers

An application of shift registers is conversion of serial data to parallel form.For example, assume the binary number 1011 is loaded sequentially, one bit at each clock pulse.

C

FF0

CLK

C

FF1

C

FF2

D0 D1 D2

Serialdatainput

C

FF3

D3Q0 Q1 Q2 Q31

C

FF0

CLK

C

FF1

C

FF2

D0 D1 D2

Serialdatainput

C

FF3

D3Q0 Q1 Q2 Q30 1

C

FF0

CLK

C

FF1

C

FF2

D0 D1 D2

Serialdatainput

C

FF3

D3Q0 Q1 Q2 Q31 0 1

C

FF0

CLK

C

FF1

C

FF2

D0 D1 D2

Serialdatainput

C

FF3

D3Q0 Q1 Q2 Q31 1 0 1

C

FF0

CLK

C

FF1

C

FF2

D0 D1 D2

Serialdatainput

C

FF3

D3Q0 Q1 Q2 Q31X 1 0 1

C

FF0

CLK

C

FF1

C

FF2

D0 D1 D2

Serialdatainput

C

FF3

D3Q0 Q1 Q2 Q31X 1 0 1

CLKCLKCLKCLK

After 4 clock pulses, the data is available at the parallel output.

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial In/Parallel Out Shift Registers

The register contains 0110 after four clock pulses.

Page 8: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

The 74HC164 8-bit serial in/parallel out shift register

Serial In/Parallel Out Shift Registers

(1)

(2)

(9)

(8)

S

C C C C

R

S S S S

C C C C

S S S

(3) (4) (5) (6) (10) (11) (12) (13)

R R R R R R R

CLK

Q0 Q1 Q2 Q3

CLR

Q4 Q5 Q6 Q7

Serial inputs

AB

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Parallel In/ Serial Out Shift Register

Shift registers can be used to convert parallel data to serial form. A logic diagram for this type of register is shown:

C

D

G2

C

D

G5

C

D

G3G6

C

D

G4G7G1

FF0 FF1 FF2 FF3

D0 D1 D2 D3

Q0 Q1 Q2 Q3

SHIFT/LOAD

CLK

Serial data out

Page 9: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Parallel In/ Serial Out Shift Register

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Parallel In/ Serial Out Shift Register

The 74HC165 8-bit parallel load shift register.

Page 10: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Parallel In/ Parallel Out Shift Register

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Parallel In/ Parallel Out Shift Register

The 74HC195 4-bit parallel access shift register.

Page 11: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Bidirectional Shift Registers

Data can be shifted leftData can be shifted rightA parallel load maybe possible74HC194 is an bidirectional universal shift register

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Bidirectional Shift Registers

Four-bit bidirectional shift register (1)

Page 12: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Bidirectional Shift Registers

Four-bit bidirectional shift register (2)

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Bidirectional Shift Registers

The 74HC194 4-bit bidirectional universal shift register.

Page 13: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Sample timing diagram for a 74HC194 shift register.

Bidirectional Shift Registers

Paralleldata

inputs

Shift right

Modecontrolinputs

Paralleloutputs

Clear Load

Shift left Inhibit

Clear

CLR

S1

SR SER

SL SER

D0

D1

D2

D3

Q0

Q1

Q2

Q3

S0

CLK

Serialdata

inputs

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Shift Register Counter

Shift registers can form useful counters by recirculatinga pattern of 0’s and 1’s. Two important shift register counters are the Johnson counter and the ring counter.

C

Q0

FF0

CLK

C

Q1

FF1

C

FF2

C

Q3

FF3

D0 D1 D2 D3Q2

Q3 Q3

The Johnson counter can be made with a series of D flip-flops

C

Q0

FF0

CLK

C

Q1

FF1

C

FF2

C

Q3

FF3

J 0 J 1 J 2 J 3Q2

Q0 Q1K0 K1 K2 K3Q2 Q3Q

Q

3

3… or with a series of J-K flip flops. Here Q3 and Q3are fed back to the J and Kinputs with a “twist”.

Page 14: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Johnson Counter

The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages).

The first five counts for a 4-bit Johnson counter that is initially cleared are: CLK Q0 Q1 Q2 Q3

0 0 0 01 0 0 01 1 0 01 1 1 01 1 1 10 1 1 1 0 0 1 1 0 0 0 1

01234567What are the remaining 3 states?

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Johnson Counter

Page 15: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Johnson Counter

Four-bit Johnson counter.

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Johnson Counter

5-bit Johnson counter

Page 16: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Ring Counter

The ring counter can also be implemented with either D flip-flops or J-K flip-flops.

Here is a 4-bit ring counter constructed from a series of D flip-flops. Notice the feedback.

Like the Johnson counter, it can also be implemented with J-K flip flops.

C

Q0

FF0

CLK

C

Q1

FF1

C

FF2

C

Q3

FF3

D0 D1 D2 D3Q2Q3

C

Q0

FF0

CLK

C

Q1

FF1

C

FF2

C

Q3

FF3

J 0 J 1 J 2 J 3Q2

Q0 Q1K0 K1 K2 K3Q2 Q3Q

Q

3

3

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Ring Counter

A 10-bit ring counter.

Page 17: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Ring Counter

A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring counter with a single 1.

1 2 3 4 7 8 9 105 6CLK

Q0

Q1

Q3

Q4

Q2

Q5

Q6

Q7

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Ring Counter

Page 18: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Shift Register Application

Time DelaySerial-to-Parallel Data ConverterUniversal Asynchronous Receiver Transmitter (UART)Keyboard Encoder

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Time Delay

Shift registers can be used to delay a digital signal by a predetermined amount.

Q7

Q7

AB

Data out

CLK40 MHz

Data in

CLK

Data in

Data outtd

C

SRG 8

An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?

The delay for each clock is 1/40 MHz = 25 ns

The total delay is 8 x 25 ns = 200 ns

25 ns

= 200 ns

Page 19: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Serial-to-Parallel Data Converter

Simplified logic diagram of a serial-to-parallel converter.

38

樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Universal Asynchronous Receiver Transmitter

Page 20: Chapter 9: Shift Registers

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Universal Asynchronous Receiver Transmitter

A UART (Universal Asynchronous Receiver Transmitter) is a serial-to-parallel converter and a parallel to serial converter.

UARTs are commonly used in small systems where one device must communicate with another. Parallel data is converted to asynchronous serial form and transmitted. The serial data format is:

D7 D6 D5 D4 D3 D2 D1 D0t

Start

Bit (0)Stop Bits (1)

Data bus

Serial data inSerial data out

CLK CLK

Receiverdata register

Transmitterdata register

Buffers

Transmittershift register

Receivershift register

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樹德科技大學 資訊工程學系Dept. of CSIE, Shu-Te University

Keyboard Encoder

Q0 Q1 Q2 Q3 Q4 Q5

D0 D1 D2 D3 D4 D5

Q5 Q6 Q7Q4Q1 Q2 Q3

D4 D5 D6 D7D1 D2 D3

Q

COLUMN encoder74HC147

1 2 3 4 5 6 7 8

1 2 4

ROW encoder74HC147

1 2 3 4 5 6 7 8

1 2 4

Key code register74HC174

QC

Clock inhibit

+V

One-shots To ROM

Switch closure

Q

D0

Q0

JK

C

SRG 474HC195

JK

C

SRG 474HC195CLK

(5 kHz)

Power on LOADSH/LD +VCC

Ring counter

CC

The keyboard encoder is an example of where a ring counter is used in a small system to encode a key press.