LNA-ESD CO-DESIGN FOR FULLY INTEGRATED CMOS WIRELESS RECEIVERS

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING ANDCOMPUTER SCIENCE

ANALOG CIRCUITS AND SIGNAL PROCESSINGConsulting Editor: Mohammed Ismail. Ohio State University

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LNA-ESD CO-DESIGN FOR

FULLY INTEGRATED CMOS

WIRELESS RECEIVERS

by

Paul Leroux

KU Leuven,

Belgium

and

Michiel Steyaert

KU Leuven,

Belgium

A C.I.P. Catalogue record for this book is available from the Library of Congress.

Published by Springer,

P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

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© 2005 Springer

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Printed in the Netherlands.

ISBN-10 1-4020-3190-4 (HB) Springer Dordrecht, Berlin, Heidelberg, New York

ISBN-13 978-1-4020-3190-8 (HB) Springer Dordrecht, Berlin, Heidelberg, New York

ISBN-13 978-1-4020-3191-5 (e-book) Springer Dordrecht, Berlin, Heidelberg, New York

ISBN-10 1-4020-3191-2 (e-book) Springer Dordrecht, Berlin, Heidelberg, New York

Contents

Abstract

List of Symbols and Abbreviations

1 Introduction 11.1 The Growth of the Wireless Communication Market . . . . . . . . . . . . . . . . 11.2 Evolution to CMOS RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 CMOS, RF and ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.4 Outline of this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Low-Noise Amplifiers in CMOS Wireless Receivers 92.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.2 Some Important RF Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Quality Factor of Reactive Elements and Series-Parallel Transformation . 92.2.2 SNR and Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2.3 Impedance Matching, Power Matching, Noise Matching . . . . . . . . . 122.2.4 Transducer Power Gain, Operating Power Gain and Available Power Gain 132.2.5 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 The Deep Sub-Micron MOS Transistor at Radio Frequencies . . . . . . . . . . . 172.3.1 MOS Model for Hand Calculations . . . . . . . . . . . . . . . . . . . . 172.3.2 Linearity of the short-channel MOS transistor . . . . . . . . . . . . . . . 182.3.3 Non-Quasi Static Model . . . . . . . . . . . . . . . . . . . . . . . . . . 192.3.4 Extended MOS Model for Simulation . . . . . . . . . . . . . . . . . . . 21

2.4 The Origin of Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.4.1 Resistor Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.4.2 Thermal Noise in MOS transistors . . . . . . . . . . . . . . . . . . . . . 22

2.4.2.1 Classical MOS Channel Noise . . . . . . . . . . . . . . . . . 222.4.2.2 Induced Gate Noise . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.3 1/f Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.4 Shot Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.5 The LNA in the Receiver Chain . . . . . . . . . . . . . . . . . . . . . . . . . . 252.5.1 Cascading Non-Ideal Building Blocks . . . . . . . . . . . . . . . . . . . 25

2.5.1.1 Noise in a Cascade . . . . . . . . . . . . . . . . . . . . . . . . 25

ix

xi

CONTENTS

2.5.1.2 IIV3 of a Cascade . . . . . . . . . . . . . . . . . . . . . . . . 262.5.2 Wireless Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . 272.5.3 LNA Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5.3.1 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.5.3.2 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.5.3.3 Voltage Gain or Power Gain . . . . . . . . . . . . . . . . . . . 292.5.3.4 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . 312.5.3.5 Reverse Isolation . . . . . . . . . . . . . . . . . . . . . . . . 312.5.3.6 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.5.3.7 Single-ended vs. Differential . . . . . . . . . . . . . . . . . . 32

2.6 Topologies for Low-Noise Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 332.6.1 The Inductively Degenerated Common Source LNA . . . . . . . . . . . 33

2.6.1.1 From Basic Common-Source Amplifier to Inductively Degen-erated Common-Source LNA . . . . . . . . . . . . . . . . . . 33

2.6.1.2 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.6.1.3 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.6.1.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.6.2 The Common-Gate LNA . . . . . . . . . . . . . . . . . . . . . . . . . . 432.6.2.1 Input Matching . . . . . . . . . . . . . . . . . . . . . . . . . 442.6.2.2 Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.6.2.3 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.6.2.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

2.6.3 Shunt-Feedback Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 482.6.4 Image Reject LNA’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.6.5 Highly Linear Feedforward LNA . . . . . . . . . . . . . . . . . . . . . 512.6.6 The Noise-Cancelling Wide-band LNA . . . . . . . . . . . . . . . . . . 522.6.7 Current Reuse LNA with Interstage Resonance . . . . . . . . . . . . . . 522.6.8 Transformer Feedback LNA . . . . . . . . . . . . . . . . . . . . . . . . 53

2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3 ESD Protection in CMOS 553.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.2 ESD Tests and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.2.1 Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.2.2 Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.2.3 Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.2.4 Transmission Line Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.3 ESD-Protection in CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.3.1 ESD-Protection Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.3.1.1 Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.3.1.2 Grounded-Gate NMOS . . . . . . . . . . . . . . . . . . . . . 633.3.1.3 Gate-Coupled NMOS . . . . . . . . . . . . . . . . . . . . . . 663.3.1.4 Silicon-Controlled Rectifier . . . . . . . . . . . . . . . . . . . 66

vi

CONTENTS

3.3.2 ESD-Protection Topologies . . . . . . . . . . . . . . . . . . . . . . . . 683.3.2.1 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.3.2.2 Power Supply Clamping . . . . . . . . . . . . . . . . . . . . . 69

3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4 Detailed Study of the Common-Source LNA with Inductive Degeneration 734.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.2 The Non-Quasi Static Gate Resistance . . . . . . . . . . . . . . . . . . . . . . . 73

4.2.1 Influence of rg,NQS on ZinZZ , GT and IIP3 . . . . . . . . . . . . . . . . . . 744.2.2 Influence of rg,NQS on the Noise Figure . . . . . . . . . . . . . . . . . . 75

4.3 Parasitic Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.3.1 Impact of CpCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3.1.1 Influence of CpCC on Input Matching . . . . . . . . . . . . . . . 804.3.1.2 Influence of CpCC on Power Gain, Noise Figure and IIP3 . . . . . 82

4.3.2 Impact of CpCC Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . 854.3.3 Impact of the Finite Q of CpCC . . . . . . . . . . . . . . . . . . . . . . . . 88

4.4 Miller Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894.5 Optimization of the Cascode Transistor . . . . . . . . . . . . . . . . . . . . . . 914.6 Output Capacitance Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . 924.7 Impact of a Non-Zero S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954.8 Output Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.8.1 Load Impedance Constraints . . . . . . . . . . . . . . . . . . . . . . . . 964.8.2 Output Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.9 LNA Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004.10 Layout Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.10.1 RF Bonding Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.10.2 On-Chip Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.10.2.1 Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024.10.2.2 Patterned Ground Shields . . . . . . . . . . . . . . . . . . . . 103

4.10.3 The Amplifying Transistor . . . . . . . . . . . . . . . . . . . . . . . . . 1044.10.4 The Cascode Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.11 The Common-Gate LNA Revisited . . . . . . . . . . . . . . . . . . . . . . . . . 1054.12 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

5 RF-ESD Co-Design for CMOS LNA’s 1115.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115.2 ESD-protection within an L-Type Matching Network . . . . . . . . . . . . . . . 112

5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125.2.2 General Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.2.3 Design and Layout of the ESD Protection Diodes . . . . . . . . . . . . . 1155.2.4 Non-Linearity of Input ESD Protection Diodes . . . . . . . . . . . . . . 1165.2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5.3 ESD-Protection within a Π-Type Matching Network . . . . . . . . . . . . . . . . 119

vii

CONTENTS

5.4 Inductive ESD-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235.5 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265.6 Other ESD-Protection Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.6.1 Distributed ESD-Protection . . . . . . . . . . . . . . . . . . . . . . . . 1285.6.2 ESD-Protection with T-Coils . . . . . . . . . . . . . . . . . . . . . . . . 130

5.7 ESD-Protection for the Common-Gate LNA . . . . . . . . . . . . . . . . . . . . 1305.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6 Integrated CMOS Low-Noise Amplifiers 1336.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336.2 A 0.8 dB NF ESD-Protected 9 mW CMOS LNA . . . . . . . . . . . . . . . . . 133

6.2.1 The GPS Power Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336.2.2 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346.2.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.2.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396.2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416.2.6 Discussion and Comparison . . . . . . . . . . . . . . . . . . . . . . . . 1446.2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

6.3 A 1.3 dB NF CMOS LNA for GPS with 3 kV HBM ESD-Protection . . . . . . . 1476.3.1 The Complete GPS Receiver Front-End . . . . . . . . . . . . . . . . . . 147

6.3.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 1476.3.1.2 Low-Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . 1486.3.1.3 Quadrature, Direct Digital Downconversion . . . . . . . . . . 1486.3.1.4 PLL Frequency Synthesizer . . . . . . . . . . . . . . . . . . . 149

6.3.2 The Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 1506.3.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.4 A 5 GHz LNA with Inductive ESD-Protection Exceeding 3 kV HBM . . . . . . . 1596.4.1 5 GHz Wireless LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1596.4.2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606.4.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656.4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

7 Conclusions 171

A Fundamentals of Two-Port Noise Theory 173

Index 175

viii

Abstract

Only a few —maybe ten or fifteen— years ago, the need for telecommunication of the aver-age citizen was limited to the ’ordinary’ telephone line. The world of telecommunication, asit develops today, is characterized by a vast expansion of applications. In the recent past, therequired bandwidth was limited to 4 kHz, allowing a reasonably intelligible conversation overthe phone. Today, applications range from email, real-time audio and video to online gamingetc.; the required bandwidth is several orders of magnitude higher. Moreover, the user wantsthe freedom to access these applications anywhere and at any time. This increased mobility isthe main driving force for the wireless communication market and explains the evolution of thesimple cell phones, five years ago, to the portable multimedia devices, they are turning into now.

These developments naturally import an ever growing quest for increased bandwidth andmobility which can only be enabled by an equally rapid technological evolution: the functionalityof the chip-sets sustaining these applications has to grow accordingly. This compression offunctionality is the main driving force behind current integration research and explains the risingpopularity of CMOS. As the ubiquitous digital technology, CMOS is the explicit candidate forintegrating both RF front-end, analog baseband and the digital back-end on a single die.

The presented work fits well within this CMOS integration framework. The book is con-ceived as a tutorial on the design of CMOS low-noise amplifiers under ESD-protection con-straints. It starts with an introduction on RF terminology. Concepts like quality factors, match-ing, noise figure, IIP3, power gain etc. are clarified. Based on a study of receiver architectures,the main LNA requirements are derived and different LNA topologies are introduced.

After a review of ESD-protection requirements in CMOS, the common-source LNA withinductive degeneration is introduced. A thorough theoretical investigation exposes the RF per-formance degradation induced by the classical ESD-protection. A rigorous design optimizationprocedure within the bounds of the ESD constraints, is described. Two alternative RF-ESD co-design procedures are proposed which are able to improve the RF performance for designs atfrequencies close to and beyond 5 GHz.

These theoretical discussions are illustrated with several implementations. Two designs, de-scribed in this work, target the very demanding GPS application. The circuits operate at 1.23 GHzand 1.57 GHz respectively and achieve noise figures in the range of 1 dB. The latter amplifierwas integrated within a complete CMOS GPS receiver front-end. A third amplifier, discussed inthis book, is compatible with the IEEE802.11a and HIPERLAN standard and operates at 5 GHz.The circuit is fully protected against ESD exceeding the industrial requirements. The attainednoise figure is 3.5 dB.

List of Symbols and Abbreviations

Symbols

Physical

k Boltzmann’s constant (1.38 × 10−23 J/K)q Elementary charge (1.60 × 10−19 C)

Definitions

α Inverse of nαgd, αdb, etc. Ratio between the device capacitances and Cgs

αind Series resistance per inductanceβ Current gain of a bipolar transistorγ Excess noise factorεox Permittivity of the gate oxideΓ Reflection coefficientδ Parameter modelling the gate noise currentΘ Parameters modelling the mobility degradationκ Elmore constant of the channelΛ Parameter modelling the channel length modulationµ Mobilityµs Two-port stability parameterξx Relative contribution of CxCCΦ(ω) Phase turnτ Time constantω0 Operating pulsationωc Pole related to the cascode nodeωT Unity current gain pulsation

AD Area of a diodeBW Bandwidthc Gate noise - drain noise correlation coefficient

List of Symbols and Abbreviations

CbpCC Capacitance of a bonding padCESDC Parasitic capacitance of the ESD deviceCJ Junction capacitance per unit areaCgsC , CgdC , etc. Device capacitancesCoxCC Gate oxide capacitance per unit areaCpCC Parasitic parallel input capacitanceen Equivalent input noise voltagef0ff Operating frequencyF Noise factorFbufFF Noise contribution of the output bufferFcFF Noise contribution of the cascode transistorfCLKff Clock frequencyFdFF Noise contribution of the classical drain noise currentFESDF Noise contribution of the ESD inductorFgFF Noise contribution of the correlated part of the gate noise currentFLF Noise contribution of the equivalent load resistanceFminFF Minimum noise factor, corresponding to a noise matchFoptFF Optimum noise factor within the matching constraintfrefff Reference frequencyfTff Unity current gain frequencygd0 Drain-source conductance at zero VDSVVgds Output conductance of a MOS transistorgm Transconductance of a MOS transistorgmb Bulk transconductanceGT Transducer power gainGu Conductance associated with the uncorrelated part of inic Part of in that is correlated to en

ICP1 Input referred 1 dB compression pointIDSI Drain currentIIP3 Input referred third-order intermodulation intercept powerIIV3 Input referred third-order intermodulation intercept voltageIM3 Third-order intermodulation ratioin Equivalent input noise currentind Drain noise currenting Non-quasi static gate noise currentISI Diode or BJT saturation currentItII 1 Snapback currentItII 2 Second breakdown currentiu Part of in that is uncorrelated to en

IV3 Third-order intermodulation intercept voltage amplitudeKnKK , KpKK Transconductance parameter of a NMOS, PMOS transistorL,W Channel length and width of a MOS transistorLd Drain or load inductance

xii

Leff Effective channel length of a MOS transistorLESD ESD protection inductanceLg Gate inductanceLg,eq Equivalent gate inductanceLg,p Equivalent parallel gate inductanceLmin Minimum channel length of a MOS transistorLs Source inductanceM Miller amplification factor (= vc

vgs)

MJM Exponent for modelling the voltage dependent junction capacitancen Factor modelling the bulk effectNF Noise figureNFsys System noise figurePavPP Available powerPav,nPP Available noise power of the sourcePav,sPP Available signal power of the sourcePDP Perimeter of a diodePDCP DC power consumptionPinPP Input powerPn,eqPP Equivalent input referred noise powerPoutPP Output powerQ Quality factor of a networkQin Input quality factor, passive input voltage amplification: vgs

vs

QLNA Quality factor of the LNA: f0ff3 dB BW

R� Sheet resistanceRbal Drain ballasting resistancerds Output resistance of a MOS transistorRf Feedback resistanceRg Resistance of the gate fingersrg,NQS Non-quasi static gate resistanceRin Input resistanceRL Equivalent load resistanceRn Resistance associated with the equivalent input noise voltage en

RpR Equivalent parallel resistance of a passive elementRS Source resistanceRS,eq Equivalent source resistance, as seen by the transistorRS,opt Optimal source resistance for optimal noise performanceRS,p Equivalent parallel source resistanceRT Termination resistanceS21, S12 Forward and reverse gainS11, S22 Input and output reflectionT Absolute temperaturetox Thickness of the gate oxide

xiii

List of Symbols and Abbreviations

VbdVV Breakdown voltageVbiVV Built-in voltage of a junctionvds, vgs Small signal drain to source and gate to source voltagesVDS,satVV Drain to source saturation voltageVGSTVV DC Gate-source over-drive voltage, i.e. VGSVV − VTVVvs Source voltageVTVV Threshold voltage of a MOS transistorVtVV 1 Snapback voltageVtVV 2 Second breakdown voltageYcYY Correlation admittance (ratio between ic and en)YoptYY Source admittance corresponding to a noise matchYsYY Source admittanceZcZZ Characteristic impedanceZinZZ Input impedanceZSZ Source impedanceZS,eqZ Equivalent source impedance

Abbreviations

A/D Analog to DigitalADC Analog to Digital ConverterAGC Automatic Gain ControlBiCMOS Bipolar Complementary Metal Oxide SemiconductorBJT Bipolar Junction TransistorBPF Band-Pass FilterCDM Charged Device ModelCDMA Code Division Multiple AccessCG Common-GateCLK Clock signalCMFB Common Mode FeedbackCMOS Complementary Metal Oxide SemiconductorCS Common-SourceDR Dynamic RangeDSP Digital Signal ProcessorDSSS Direct-Sequence Spread SpectrumESD Electro-Static DischargeFCC Federal Communications CommissionFOM Figure Of MeritGCNMOS Gate-Coupled NMOSGGNMOS Grounded-Gate NMOSGPS Global Positioning System

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GSM Global System for Mobile CommunicationsHBM Human Body ModelHF High FrequencyHPF High-Pass FilterIC Integrated CircuitIF Intermediate FrequencyIMFDR Intermodulation-Free Dynamic RangeIMRR Image Rejection RatioI/O Input/OutputLAN Local Area NetworkLF Low FrequencyLNA Low-Noise AmplifierLO Local OscillatorLPF Low-Pass FilterMCM Multi-Chip ModuleMIM Metal Insulator MetalMM Machine ModelNMOS n-channel MOSFETNQS Non-Quasi StaticOFDM Orthogonal Frequency-Division MultiplexingOPAMP Operational AmplifierOSR Oversampling RatioPAE Power Added EfficiencyPCB Printed Circuit BoardPD Phase-DetectorPFD Phase-Frequency DetectorPLL Phase Locked LoopPMOS p-channel MOSFETPSD Power Spectral DensityRF Radio FrequencySAW Surface Acoustic WaveSCR Silicon-Controlled RectifierSNDR Signal-to-Noise-and-Distortion RatioSNR Signal-to-Noise RatioSOI Silicon On InsulatorTIA TransImpedance AmplifierTLP Transmission Line PulseUMTS Universal Mobile Telecommunications SystemUWB Ultra-Wide-BandVCO Voltage-Controlled OscillatorVGA Variable-Gain AmplifierWLAN Wireless Local Area Network

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