lecture 13 cmos logic - university of california,...
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EE1411
EECS141 1Lecture #13
EE141EE141--Fall 2007Fall 2007Digital Integrated Digital Integrated CircuitsCircuits
Lecture 13Lecture 13CMOS LogicCMOS Logic
EE1412
EECS141 2Lecture #13
AnnouncementsAnnouncementsHardware lab this weekHW#6 out this Thurs.
EE1413
EECS141 3Lecture #13
Class MaterialClass Material
Last lectureWire models
Today’s lectureCMOS logic gates
Reading (Chapter 6)
EE1414
EECS141 4Lecture #13
CMOS LogicCMOS Logic
EE1415
EECS141 5Lecture #13
Combinational vs. Sequential LogicCombinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
CombinationalLogicCircuit
OutInCombinational
LogicCircuit
OutIn
State
EE1416
EECS141 6Lecture #13
Static CMOS GatesStatic CMOS GatesAt every point in time (except during the switchingtransients) each gate output is connected to eitherVDD or VSS via a low resistive path.
The outputs of the gates assume at all times the valueof the Boolean function implemented by the circuit(ignoring, once again, the transient effects during switching periods).
This is in contrast to the dynamic circuit style, whichrelies on temporary storage of signal values on thecapacitance of high-impedance circuit nodes.
EE1417
EECS141 7Lecture #13
Static Complementary CMOSStatic Complementary CMOSVDD
F(In1,In2,…InN)
In1In2
InN
In1In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networksPUN and PDN functions are complementary
……
EE1418
EECS141 8Lecture #13
NMOS Transistors NMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
Y = X if A AND B
Y = X if A OR B
Transistor ↔ switch controlled by its gate signalNMOS switch closes when switch control input is high
NMOS transistors pass a “strong” 0 but a “weak” 1
A B
X Y
X Y
A
B
AND
OR
EE1419
EECS141 9Lecture #13
PMOS Transistors PMOS Transistors in Series/Parallel Connectionin Series/Parallel Connection
PMOS switch closes when switch control is low
PMOS transistors pass a “strong” 1 but a “weak” 0
X Y
A B
A
BX Y
NOR
NAND
Y = X if A AND B = A + B
Y = X if A OR B = AB
EE14110
EECS141 10Lecture #13
Threshold DropsThreshold DropsVDD
VDD → 0PDN
0 → VDD
CL
CL
PUN
VDD
0 → VDD - VTn
CL
VDD
VDD
VDD → |VTp|
CL
S
D S
D
VGS
S
SD
D
VGS
EE14111
EECS141 11Lecture #13
Complementary CMOS Logic StyleComplementary CMOS Logic StylePUP is the dual to PDN(can be shown using DeMorgan’s Theorems)
Static CMOS gates are always inverting
A + B = AB
AB = A + B
AND = NAND + INV
EE14112
EECS141 12Lecture #13
Example Gate: NANDExample Gate: NAND
PDN: G = AB ⇒ Conduction to GNDPUN: F = A + B = AB ⇒ Conduction to VDD
G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)
EE14113
EECS141 13Lecture #13
Example Gate: NORExample Gate: NOR
EE14114
EECS141 14Lecture #13
Complex CMOS GateComplex CMOS Gate
OUT = D + A • (B + C)
DA
B C
D
AB
C
EE14115
EECS141 15Lecture #13
Constructing a Complex GateConstructing a Complex Gate
C
(a) pull-down network
SN1 SN4
SN2
SN3D
FF
A
DB
C
D
F
A
B
C
(b) Deriving the pull-up networkhierarchically by identifyingsub-nets
D
A
A
B
C
VDD VDD
B
(c) complete gate
EE14116
EECS141 16Lecture #13
Another ExampleAnother Example
Y = A+BC
EE14117
EECS141 17Lecture #13
Cell DesignCell Design
Standard CellsGeneral purpose logicUsed to synthesize RTL/HDLSame height, varying width
Datapath CellsFor regular, structured designs (arithmetic)Includes some wiring in the cell
EE14118
EECS141 18Lecture #13
Standard Cell Layout Methodology Standard Cell Layout Methodology ––1980s1980s
signals
Routingchannel
VDD
GND
EE14119
EECS141 19Lecture #13
Standard Cell Layout Methodology Standard Cell Layout Methodology ––1990s 1990s -- TodayToday
M2
No routingchannels VDD
GNDM3
VDD
GND
Mirrored Cell
Mirrored Cell
EE14120
EECS141 20Lecture #13
Standard CellsStandard Cells
Cell boundary
N WellCell height 12 metal tracksMetal track is approx. 3λ + 3λPitch = repetitive distance between objects
Cell height is “12 Mn pitch”
2λ
Rails ~10λ
InOut
VDD
GND
EE14121
EECS141 21Lecture #13
Standard CellsStandard Cells
InOut
VDD
GND
In Out
VDD
GND
With silicideddiffusion
With minimaldiffusionrouting
OutIn
VDD
M2
M1
EE14122
EECS141 22Lecture #13
Standard CellsStandard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
EE14123
EECS141 23Lecture #13
Stick DiagramsStick DiagramsContains no dimensionsRepresents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
EE14124
EECS141 24Lecture #13
Stick DiagramsStick Diagrams
C
A B
X = C • (A + B)
B
AC
i j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph
j
EE14125
EECS141 25Lecture #13
Two Versions of C Two Versions of C •• (A + B)(A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
EE14126
EECS141 26Lecture #13
Consistent Euler PathConsistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
EE14127
EECS141 27Lecture #13
OAI22 Logic GraphOAI22 Logic Graph
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
EE14128
EECS141 28Lecture #13
Example: x = Example: x = ab+cdab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}b
EE14129
EECS141 29Lecture #13
MultiMulti--Fingered TransistorsFingered TransistorsOne finger Two fingers (folded)
Less diffusion capacitance
EE14130
EECS141 30Lecture #13
CMOS PropertiesCMOS PropertiesFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the relative device sizes; ratiolessAlways a path to Vdd or Gnd in steady state; low output impedanceExtremely high input resistance; nearly zero steady-state input currentNo direct path steady state between power and ground; no static power dissipationPropagation delay function of load capacitance and resistance of transistors
EE14131
EECS141 31Lecture #13
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CMOS logic - properties