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Layout Design II Lecture 6 18-322 Fall 2003

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Page 1: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Layout Design II

Lecture 618-322 Fall 2003

Page 2: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Roadmap

Today: Layout Verification & “design in the large”Next week:

Transistor sizingWires

Homework 1: Due TodayHomework 2: Out Today, Due Sept 18Lab 2: This weekLab 3: Warning! Work hard, keep working

Page 3: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Today’s Overview

Handout: Virtuoso

Design VerificationDRC: Design Rule CheckLVS: Layout versus Schematic

Design in the large…How do designers design ICs NOW

Page 4: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Outline

• Reasoning• Design Rule Checker (DRC)• Extractions• Layout vs. Schematic (LVS)• SPICE Simulations

Page 5: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Reasoning

• Manufacturing is expensive– Mask Set Cost – $$$ millions– Fab turn-around time is couple of months

• Make sure the timing requirements are met• Process requirements are satisfied in the

layout • The layout implements correct functionality

Page 6: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Design Rule Checker (DRC)

• Each process has a set of design constraints– Space rules– Width rules– Overlap/Extension rules– Area/Density rules

• Design must be free from these errors in order to successfully manufacture an IC

• DRC tool is used to identify process violations present in the layout

Page 7: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Layout

Page 8: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Layout

Page 9: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

DRC Window

Page 10: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Layout After DRC Run

Page 11: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Layout After DRC Run

Page 12: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Error Messages Windows

Page 13: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Fix the Layout

NEWOLD

Page 14: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Extractions

• Polygons Devices Step– Find FETs– Calculate capacitances for FETs/wires– Calculate resistances for FETs/wires

Page 15: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Starting

Page 16: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Extract Options

SPICE OptionsLVS Options

Page 17: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

Layout vs. Schematic (LVS)

• Does your layout match the schematic• Does not perform functional checking• In order to ensure schematic functionality at

layout level, the LVS cannot generate any errors

Page 18: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

LVS Example

Page 19: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

LVS Example

Page 20: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated
Page 21: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated
Page 22: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

The net-lists failed to matchLike matching is enabled.Using terminal names as correspondence points.Net-list summary for extracted view

count6 nets3 terminals3 pmos3 nmos

Net-list summary for schematic count

7 nets5 terminals3 pmos3 nmos

Page 23: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

The net-lists failed to match.

layout schematicinstances

un-matched 2 2rewired 0 0size errors 0 0pruned 0 0active 6 6total 6 6

netsun-matched 2 3merged 0 0pruned 0 0active 6 7total 6 7

terminals

Page 24: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

devbad.out:I /M1? Device does not cross-match.I /M2? Device does not cross-match.

netbad.out:N /net20? Net does not cross-match. It has 4 connections.N /gnd!? Net does not cross-match. It has 4 connections.N /net24? Net does not cross-match. It has 2 connections.

Page 25: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

LVS Example

Page 26: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

LVS Example

Page 27: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

That’s how we verify in 322Simulate (Spice/Verilog)Compare (LVS)Make sure it could be fabbed (DRC)

“Full-custom design”Useful in 1980sStill used in some portions of highest performance chips

Microprocessors

Page 28: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Design Productivity “Crisis”

Transistors/chip [k]1,000,000 10,000,000

1800 Staff Yrs.

800 Staff Yrs.100,000 1,000,000

10,000 100,000

1,000 10,000

1000

** *

Transistors/Staff-No.100

1092 94 96 98 2000 02 04 06 08 Year

SEMATECH

Page 29: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

ASIC Design Abstractions

Designer Productivity is THE big problemIn 1978, people could draw transistors, now there are 100s of millions per chip…New abstractions necessary:

Masks LayoutDesign

Design R

ules

????/

Current ASICs

Cell L

ibrariesStd CellDesign ????

18-322

Page 30: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Standard Cell Design Process

Design Entry and Simulation» Schematics» Verilog / VHDL

Logic Synthesis» Input: Verilog/VHDL and Cell Library» Estimated Timing» Simulation

Timing Analysis» Determine worst-case clock speed

Formal Verification» Check equivalence of Gates and Specification

Design Hand-off

Page 31: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Standard Cell Design ProcessFloorplanning

» Localize major functions of the chip» Consider global timing» Partition design

Placement» Find locations for all circuits» Consider detail timing» Assure proximity of critical nets

Global Routing» Resolve congestion» Localize nets» Give critical nets best paths

Detail Routing» Locate shortest paths» Create net geometry» Route critical nets first

Tape-out to manufacturing

Page 32: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Anatomy of a Standard CellnWell Contact

Metal 2 Pitch

Substrate Contact

NwellVDD Rail

Signal Pins(metal 2)

GND Rail

Cell Width

Page 33: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Standard Cell Rows

Shared VDD Shared Well

Shared GND

Page 34: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Standard Cell “Rules”

Rails and wells route by abutment:Same width, spacing, metal layerGo to cell boundarySubstrate or well contacts underneath

Any other cell could abutAll design rules enforced 50% to Boundary

Page 35: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Standard Cell Libraries> 100 cells of different types

LogicDFFs: Set/Reset polarity, scan variations“Filler” w/ Capacitors

Library variationsLow power, low leakageHigh performance“Robust”Data path oriented

Page 36: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

D Flip Flop: Standard Cell

Page 37: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 38: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 39: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 40: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 41: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 42: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 43: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Page 44: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

History of Design AutomationPeriodic increases in abstraction to increase productivityPeriodic increases in abstraction to increase productivity

The next quantum step in productivity ????The next quantum step in productivity ????

Results(Design Productivity)

1978

1985

1992

1999

Transistor Entry

a

b

s

q0

1

d

clk Schematic Entry

Synthesis

What’s next?

Effort (EDA tools effort)

Page 45: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Productivity Gap: Core-based Design

“Core-based” DesignIP-based Design

DSP core(bought) “Soft cores”

Synthesizable HDLTest-vectorsRedesign in new process

“Hard cores”Complete LayoutScale to new process

Kbrd cntrl

RF

Dsply cntrl

Internal IP

System-on-a-Chip(SoC) New Class of Companies:

IP-providers

Page 46: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

Core-based Design Challenges

Interfacing:How to get these blocks talking?Standard Busses:

But then why have it on-chip?Debug:

How to see embedded signalsTesting:

How to test individual cores?Liability/Support:

What if there’s a bug in one of the cores?Who will PAY!

System-on-a-Chip(SoC)

Page 47: Layout Design II - ECE:Course Pagecourse.ece.cmu.edu/~ece322/LECTURES/Lecture6/Lecture6.03.pdf · » Verilog / VHDL zLogic Synthesis » Input: Verilog/VHDL and Cell Library » Estimated

© 2003 Herman Schmit

SummaryBasic Layout using Virtuoso

Layout Verification for 322DRCLVS

Design in the largeBuilding “standard cells”Using a library of standard cells and design automation to construct a BIG chipDesign Productivity Problem


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