uart(vhdl) && vga(verilog)

Mid Term Report Saurabh Shukla

MCIS, Manipal University

Table of Contents:

CHAPTER 1: Introduction ................................................................................................................. 6

1. Organization ............................................................................................................................ 6

1.1: Samtel Group Companies ................................................................................................. 6

1.2: Objectives: ............................................................................................................................ 9

1.2.1: UART: ............................................................................................................................. 9

1.2.2: VGA: ............................................................................................................................. 10

CHAPTER 2: Literature Review ...................................................................................................... 11

2.1: FPGA: .................................................................................................................................. 11

2.1.1: Introduction: ................................................................................................................ 11

2.1.2: Key Components and Features: .................................................................................. 11

2.1.3: Fast, Asynchronous SRAM: .......................................................................................... 13

2.1.4: Four – Digit, Seven – Segment LED Display: ................................................................ 15

2.1.5: Switches and LEDs: .......................................................................................................... 17

2.1.5.1: Slide Switches: .......................................................................................................... 17

2.1.5.2: Push Button Switches: .............................................................................................. 18

2.1.5.3: LEDs: ......................................................................................................................... 18

2.1.6: VGA Port: ..................................................................................................................... 19

2.1.7: PS/2 Mouse/Keyboard Port: ........................................................................................ 20

2.1.7: RS – 232 Port: .............................................................................................................. 21

2.1.8: Clock Sources: .............................................................................................................. 22

2.2: Hyper Terminal: .................................................................................................................. 23

2.2.1: Protocols Supported: ................................................................................................... 23

2.3: VHDL: .................................................................................................................................. 29



2.3.1: Entity: .......................................................................................................................... 29

2.3.2: Architecture: ................................................................................................................ 29

2.3.3: Configuration: .............................................................................................................. 29

2.3.4: Package: ....................................................................................................................... 29

2.3.5: Driver: .......................................................................................................................... 29

2.3.6: Bus: .............................................................................................................................. 29

2.3.7: Attribute: ..................................................................................................................... 29

2.3.8: Generic: ....................................................................................................................... 29

2.3.9: Process:........................................................................................................................ 29

2.3.10: Logical Operators: ..................................................................................................... 29

2.3.11: Data Type: ................................................................................................................. 30

2.3.12: Operator: ................................................................................................................... 31

2.3.13: Process and sequential statements: .......................................................................... 31

2.3.13: Sequential – If statement: ......................................................................................... 32

2.3.14: Signals: ....................................................................................................................... 32

2.3.15: Attributes: ................................................................................................................. 32

2.3.16: Value Attributes: ....................................................................................................... 33

2.3.17: Function Attributes: .................................................................................................. 33

2.3.18: Constants: .................................................................................................................. 33

2.3.19: Constant declaration: ................................................................................................ 33

2.3.20: Entity Ports and Mode: .............................................................................................. 33

2.3.21: Enumerated Types:.................................................................................................... 33

2.3.22: Recipe coding of state machines: .............................................................................. 34

2.3.23: Hierarchy: .................................................................................................................. 34

2.3.24: Port Map: ................................................................................................................... 34

2.3.25: User defined Arrays: .................................................................................................. 34



2.4: Verilog: ............................................................................................................................... 35

2.4.1:Abstraction Level of Verilog: ........................................................................................ 35

2.4.2: Gate and Switch delays: .............................................................................................. 36

2.4.3: Identifiers: ................................................................................................................... 37

2.4.4: Data Types: .................................................................................................................. 37

2.4.5: String: .......................................................................................................................... 38

2.4.6: Operators: ................................................................................................................... 38

2.4.7: Procedural Blocks: ....................................................................................................... 39

2.4.8: Blocking Assignment: .................................................................................................. 39

2.4.9: Non – Blocking Assignment: ........................................................................................ 39

2.4.10: Conditional Statement if – else: ................................................................................ 40

2.4.11: Case Statement: ........................................................................................................ 40

2.4.12: Loop Statements: ...................................................................................................... 40

2.4.13: Continuous Assignment statements: ........................................................................ 41

2.4.14: Propagation Delay : ................................................................................................... 41

2.4.15: Task : .......................................................................................................................... 42

2.4.16: Function: .................................................................................................................... 42

2.4.17: $display:..................................................................................................................... 42

2.4.18: $monitor: ................................................................................................................... 42

2.4.19: $Strobe: ..................................................................................................................... 42

2.4.20: $time : ....................................................................................................................... 43

2.4.21: $Stime: ....................................................................................................................... 43

2.4.22: $realtime: .................................................................................................................. 43

2.4.23: $reset: ........................................................................................................................ 43

2.4.24: $stop: ......................................................................................................................... 43

2.4.25: $finish: ....................................................................................................................... 43



2.4.26: $random: ................................................................................................................... 43

2.4.27: Initializing Memories: ................................................................................................ 43

2.5: Xilinx ISE Design Suite 13.1: ................................................................................................ 45

2.5.1: Getting started: ........................................................................................................... 45

2.5.2: Create a New Project: .................................................................................................. 45

2.5.3: Create an HDL Source: ................................................................................................. 46

2.5.4: Design Simulation: ....................................................................................................... 47

Chapter 3: Research Methodology/Experimental Setup: ............................................................. 53

3.1: UART: .................................................................................................................................. 53

3.1.1:Introduction .................................................................................................................. 53

3.1.2: Pin diagram of the UART: ............................................................................................ 54

3.1.3: Pin description of the UART: ....................................................................................... 54

3.1.4: Block Diagram of UART: .............................................................................................. 55

3.1.5: Functional Description of UART: ................................................................................. 55

3.1.6: Baud rate generator for Receiver ................................................................................ 56

3.1.7: FSM of Baud rate generator: ....................................................................................... 56

3.1.8: Functional Description of FSM in each state: .............................................................. 57

3.1.9: Baud rate generator for transmitter .......................................................................... 58

3.1.10: FSM of baud rate generator for Transmitter: ........................................................... 58

3.1.11: Functional Description of FSM in each state: ........................................................... 59

3.1.12: UART Receiver sub system: ....................................................................................... 60

3.1.13: Transmitter sub system. ............................................................................................ 63

3.1.14: asynchronous FIFO Interface circuit .......................................................................... 65

3.2: VGA: .................................................................................................................................... 69

3.2.1: VGA Synchronization: .................................................................................................. 69

3.2.2: Horizontal Synchronization: ........................................................................................ 71



3.2.4: Timing Calculation of VGA synchronization signals:.................................................... 74

3.2.5: Overview Of the pixel Generation circuit: ................................................................... 75

3.3: Conclusion and scope for future work. .............................................................................. 79

3.4: Bibliography: ....................................................................................................................... 79

3.5: Appendices ......................................................................................................................... 80

3.5.1: VHDL CODE OF UART: .................................................................................................. 80

3.5.2: Verilog CODE OF VGA: ................................................................................................ 93

3.6: RESULT .............................................................................................................................. 119

3.6.1: RTL Schematic View ................................................................................................... 119

3.6.2: Simulated behavioral result ...................................................................................... 125

3.6.3: Result of VGA ............................................................................................................. 129

3.6.3.1: Result of Pong Game: ............................................................................................. 129

3.7: ACRONYMS: ...................................................................................................................... 131



CHAPTER 1: Introduction

1. Organization

Samtel Group's journey began in 1973, with a vision to create a world-class organization. Today, Samtel Group is India’s largest integrated manufacturer of a wide range of displays for television, avionics, industrial, medical and professional applications, TV glass, components for displays, machinery and engineering services. The group employs 6000 people in nine world-class factories and has an annual turnover of Rs 12 billion (USD 300M)

Samtel Group has strong design and development skills and is a dependable player with excellent technological capabilities and a long-term commitment to the display industry. Its products are known for ruggedness and reliability and conform to the latest relevant quality standards. The group has excellent relationships with suppliers of key components and the ability to design new products as well as set up hi-tech manufacturing facilities. Samtel has registered many patents for developments in display technology and also developed its own technology for automation.

1.1: Samtel Group Companies

1.1.1: SAMTEL COLOR LTD

Samtel Color, the flagship company of the group manufactures the widest range of Color TV tubes in India – from 14 inches to 29 inches, and has a capacity of over 10 million picture tubes per annum. Integrated backwards with its component divisions at Ghaziabad and Parwanoo, it also manufactures electron guns and deflection yokes for color picture tubes. With a market share of over 60%, it is the largest tube manufacturer and exporter in the country. Its clients include leading domestic and international TV manufacturers.

1.1.2: SAMTEL GLASS LTD

Originally formed as a JV between Corning Inc., USA and Samtel in 1989, Samtel Glass manufactures glass parts for color picture tubes through its plant in Kota, Rajasthan. Samtel Glass is now owned fully by Samtel and is one of the leading manufacturers of glass for color picture tubes.



1.1.3: SAMTEL DISPLAY SYSTEMS LTD

Samtel Display Systems (SDS) is a key Indian player in high-technology products for avionics and military applications in both domestic and international markets. SDS straddles the entire value chain from design, development, manufacture, testing, qualification, repair & maintenance and obsolescence management of avionics products and equipment for military as well as commercial aircraft. Its products include Color Avionic Tubes (CAT), Multi Function Displays (MFD), Head Up Displays (HUD), Helmet Mounted Displays (HMD), Automated Test Equipments (ATE) and IADS, as well as Control Displays for Armored Military Vehicles.

1.1.4: SAMTEL HAL DISPLAY SYSTEMS LTD

Samtel HAL Display Systems (SHDS), a joint venture between Hindustan Aeronautics Limited (HAL) and Samtel, was created to address the avionics requirements of HAL, especially cockpit displays of all kinds. SHDS is responsible for system design, development, manufacturing, MRO and obsolescence management of display systems, ATE and IADS for all Indian platforms.

1.1.5: SAMTEL THALES AVIONICS LTD

Samtel Thales Avionics is a joint venture between Samtel and Thales, and brings Thales' technological expertise to India through Thales' multi-domestic strategy of partnering with leading industry players across the world. The JV will work towards the local development, production, sale and maintenance of Helmets Mounted Sight & Display (HMSD) and other Avionics Systems destined for the Indian market. Samtel Thales Avionics will become the design authority for products and equipment developed and manages them through their entire life cycle.

1.1.6: SAMTEL ELECTRON DEVICES, GmbH

SAMTEL ELECTRON DEVICES GmbH, with its core competencies in the design and manufacturing of high technology Electron Guns and high efficiency Phosphor Screens, is dedicated to professional applications of Cathode Ray Tubes (CRT), scientific instruments (RHEED), X-Ray Guns, Phosphor screens for TEM and other related technologies.



1.1.7: SAMTEL MACHINES

Samtel Machines is a key player in the domain of Industrial Automation and Special Purpose Machines manufacturing in India. Samtel Machines is a consequence of Samtel’s in-house expertise in internal automation for various inhouse automation requirements, focusing on Automation, Material handling, Special Purpose Machines and Assembly lines, which set the foundation for a full-fledged division catering to Machine building – called Samtel Machines.

1.1.8: SAMTEL ENGINEERING AND SOURCING SOLUTIONS

Samtel’s first step in the KPO (Knowledge Process Outsourcing) industry, Samtel Engineering and Sourcing Solutions provides outsourcing solutions to several global companies and multinationals.

1.1.9: SAMTEL USA

Samtel USA is a US Company, wholly owned by Samtel Group of New Delhi, India with offices in San Jose, CA and Princeton, NJ. Samtel USA will facilitate close liaison with Samtel Display Systems’ existing and potential North American customers, while helping to pursue Business Development activities in the region.



1.2: Objectives:

1.2.1: UART: UART receiver / Transmitter have data bits, stop bits scalable. Baud generator has its baud rate divisor scalable. Interface circuit (FIFO) its depth scalable. Tested in Spartan – 3 starter kit board (FPGA).

This Project focuses on the design of high speed UART. The project describing the

behavior of UART circuit using VHDL. In the result and simulation part, in the baud

rate generator part, UART receiver, UART transmitter. VHDL synthesis is for high

reliability systems. UART baud rate of 19200, using 50 MHz system clock rate. The

simulated waveforms in this Project have proven the reliability of the VHDL

implementation to describe the characteristics and the architecture of the design

UART with baud rate generator.

UART provide serial asynchronous receiver data synchronization, parallel- to – serial

and serial – to – parallel data conversion for both the transmitter and receiver

sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital systems. Synchronization for the serial data

stream is accomplished by adding start and stop bit to the transmit data to form a data

character.

UART include a transmitter and receiver. The transmitter is essentially a special shift

register that loads data in parallel and then shifts it out bit by bit at specific rate.

UART Receiver, on the other hand, shifts in data bit by bit and then reassembles the

data. The serial line is high when it is idle.

UART transmission starts with a start bit, which is low, followed by data bits and an

optional parity bit and ends with stop bits, which is high.

The LSB of the data word is transmitted first. No clock information is conveyed

through the serial line. Before the transmission starts, the transmitter and receiver

must agree on a set of parameters in advance, which include the baud rate.

Baud rate , number of bits per second which is 19200.



1.2.2: VGA:

Video Graphics Array is widely supported by PC graphics Hardware and monitors. Basic eight

color 640 by 480 resolution interface for CRT monitors. Tested in Spartan- 3 starter kit

board(FPGA).

The VGA port has five active signal, including the horizontal and vertical synchronization signal.

Three video signal for the Red, Green, blue. one horizontal synchronization signal and one

vertical synchronization signal. A video signal is an analog signal and the video controller uses a

digital – to – analog converter to convert the digital output to the desired analog level. It is

physically connected to a 15 – pin D – subminiature connector. If a video signal is represented

by a N – bit word, it can be converted to 2^N analog levels. The three video signals can generate

2^3N different colors. This is also known as 3N – bit color since a color is defined by 3N bits. In

the S3 board, a 1 – bit word is used for each video signal, this leads to only eight (i.e. , 2^3)

possible colors. If we use the same 1 – bit signal to drive the video signals, they become either

“000” or “111” and the monitor functions as a black and white monochrome monitor.

Red (R) Green(G) Blue(B) Resulting color

0 0 0 Black

0 0 1 Blue

0 1 0 Green

0 1 1 Cyan

1 0 0 Red

1 0 1 Magenta

1 1 0 Yellow

1 1 1 White



CHAPTER 2: Literature Review

2.1: FPGA:

2.1.1: Introduction:

The Xilinx Spartan – 3 starter kit provides a low – cost, easy – to –

use development and evaluation plat form for Spartan – 3 FPGA designs.

2.1.2: Key Components and Features:

Spartan – 3 starter kit board includes the

following components and features:

1) 20,000 gate Xilinx Spartan – 3 Xc3s200 FPGA in a 256 ball thin ball grid array

package.

2) 2 M bit Xilinx XCF02s platform flash, in – system programmable configuration

PROM.

3) Jumper options allow FPGA application to read PROM data or FPGA

configuration from other sources.

4) 1M byte of fast asynchronous SRAM.

5) 3 – bit, 8 – color VGA display port.

6) 9 – pin RS – 232 serial port.

7) RS – 232 transceiver / level translator.

8) Second RS – 232 transmit and receive channel available on board test points.

9) PS/2 – style mouse / Keyboard port.

10) Four – character, seven – segment LED display.

11) Eight slide switches.

12) Eight individual LED outputs.

13) Four momentary – contact push button switches.

14) 50 MHZ crystal oscillator clock source.

15) Socket for an auxiliary crystal oscillator clock source.



16) FPGA configuration mode selected via jumper settings.

17) Push button switch to force FPGA reconfiguration.

18) LED include when FPGA is successfully configured.

19) & 20) & 21) three 40 – pin expansion connection ports to extend and enhance the

Spartan - 3 starter kit board.

22) JTAG port for low – cost download cable.

23) Diligent JTAG download / debugging cable connects to PC parallel port.

24) JTAG download / debug port compatible with the Xilinx parallel cable IV and

multi pro desktop tool.

25) AC power adapter input for include international unregulated + 5 v power supply.

26) Power – on indicator LED.

27) On – board 3.3v regulator.





2.1.3: Fast, Asynchronous SRAM:

The Spartan – 3 starter kit board has a

megabyte of fast asynchronous SRM, surface mounted to the back side of the board. The

memory array includes two 256Kx16 ISSI 10ns SRAM devices.

The SRAM array from either a signal

256Kx32 SRAM memory or two independent 256Kx16 array.

Both SRAM devices share common write –

enable, output – enable and address signal. Each device has a separate chip select enable

control and individual byte – enable controls to select the high or low byte in the 16 – bit

data word.

The 256kx32 configuration is ideally suited

to hold micro blaze instructions. However, it alternately provides high – density data

storage for a Varity of applications such as digital signal processing large data FIFO and

graphics buffers.

External SRM address Bus connections to Spartan – 3 FPGA

Address FPGA Pin A1 Expansion connector Pin

A17 L3 35

A16 K5 33

A15 K3 34

A14 J3 31

A13 J4 32

A12 H4 29

A11 H3 30

A10 G5 27

A9 E4 28

A8 E3 25

A7 F4 26



A6 F3 23

A5 G4 24

A4 L4 14

A3 M3 12

A2 M4 10

A1 N3 8

A0 L5 6

External SRAM Control Signal Connections to Spartan – 3 FPGA:

OE# �� Output Enable

WE# �� Write Enable.

Signal FPGA Pin A1 Expansion connector pin

OE# K4 16

WE# G3 18



2.1.4: Four – Digit, Seven – Segment LED Display:

The Spartan – 3 starter kit

board has a four character, seven segment LED display controlled by FPGA user I/O

pins. Each digit shares eight common control signals to light individual LED segments.

The pin number for each FPGA pin connected to

the LED display appears in parentheses. To light an individual signal, drive the individual

segment control signal low along with the associated anode control signal for the

individual character.

FPGA Connections To seven – Segment Display:

Segment FPGA Pin

A E14

B G13

C N15

D P15

E R16

F F13

G N16

DP P16

Digit Enable (Anode control) Signal:

Anode Control AN3 AN2 AN1 AN0

FPGA Pin E13 F14 G14 D14



Display Characters and resulting LED Segment Control Values:

Character A b c d e f G

0 0 0 0 0 0 0 1

1 1 0 0 1 1 1 1

2 0 0 1 0 0 1 0

3 0 0 0 0 1 1 0

4 1 0 0 1 1 0 0

5 0 1 0 0 1 0 0

6 0 1 0 0 0 0 0

7 0 0 0 1 1 1 1

8 0 0 0 0 0 0 0

9 0 0 0 0 1 0 0

A 0 0 0 1 0 0 0

b 1 1 0 0 0 0 0

C 0 1 1 0 0 0 1

D 1 0 0 0 0 1 0

E 0 1 1 0 0 0 0

F 0 1 1 1 0 0 0



The LED control signals are time – multiplexed to display data on all four

characters. Present the value to be displayed on the segment control inputs and select the

specified character by driving the associated anode control signal LOW. Through

persistence of vision, the human brain perceives that all four characters appear

simultaneously, similar to the way the brain perceives a TV display. This “scanning”

technique reduces the number of I/O pins required for the four characters. If an FPGA pin

were dedicated for each individual segment, then 32 pins are required to drive four 7-

segment LED characters. The scanning technique reduces the required I/O down to 12

pins. The drawback to this approach is that the FPGA logic must continuously scan data

out to the displays a small price to save 20 additional I/O pins.

2.1.5: Switches and LEDs:

2.1.5.1: Slide Switches:

The Spartan – 3 starter kit board has eight slide switches.

The switches are located along the lower edge of the board, toward the right edge.

Slider Switch Connections:

Switch SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0

FPGA

Pin

K13 K14 J13 J14 H13 H14 G12 F12

When in the UP or ON position, a switch connects the

FPGA pin to Vcco, a logic High. When DOWN or in the OFF position, the switch

connects the FPGA pin to ground, logic LOW. The switches typically exhibit about 2 ms

of mechanical bounce and there is no active denouncing circuitry, although such circuitry

could easily be added to the FPGA design programmed on the board.



2.1.5.2: Push Button Switches:

Spartan – 3 starter kit board has four momentary –

contact push buttons are located along the lower edge of the board, toward the right edge.

Push Button Switch Connections:

Push Button FPGA Pin

BTN3 L14

BTN2 L13

BTN1 M14

BTN0 M13

Pressing a push button generates a logic high on the

associated FPGA pin. Again, there is no active debouncing circuitry on the push button.

2.1.5.3: LEDs:

The Spartan – 3 starter kit board has eight individual surface mount LEDs

located above the push button switches. The LED’s are labeled LED7 through LED0.

LED Connections To The Spartan – 3 FPGA:

LED FPGA Pin

LD7 P11

LD6 P12

LD5 N12

LD4 P13

LD3 N14

LD2 L12

LD1 P14

LD0 K12



2.1.6: VGA Port:

The Spartan – 3 starter kit board induces a VGA display port and

DB15 connector. Connect this port directly to most PC monitors or flat – panel LCD

displays using a standard monitor cable.

The Spartan – 3 FPGA controls five VGA signals: Red, Green, Blue, Horizontal sync,

Vertical sync, all available on the VGA connector. VGA port connections to the Spartan

– 3 FPGA.

Signal FPGA Pin

Red R12

Green T12

Blue R11

Horizontal Sync R9

Vertical Sync R10

Each color line has a series resistor to provide 3 – bit color with one bit each for Red,

Green, Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that

the color signal remain in the VGA – specified 0 V to 0.7 V range.

3 – Bit Display Color Codes:

Red Green Blue Resulting Color

0 0 0 Black

0 0 1 Blue

0 1 0 Green

0 1 1 Cyan

1 0 0 Red

1 0 1 Magenta

1 1 0 Yellow

1 1 1 White



2.1.7: PS/2 Mouse/Keyboard Port:

The Spartan – 3 starter kit board include a

PS/2 mouse/Keyboard port and the standard 6 – pin mini – din connector, labeled J3 on

the board. Only pins 1 and 5 of the connector attached to the FPGA.

PS/2 Din pin Signal FPGA Pin

1 Data M15

2 Reserved -------

3 GND GND

4 Voltage Supply -------

5 CLK M16

6 Reserved -------

Both a PC mouse and keyboard use the two – wire

PS/2 serial bus to communicate with a host device, the Spartan – 3 FPGA in this case.

The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus

with identical signal timings and both use 11 – bit words that include a start, stop and add

parity bit. However, the data packets are organized differently for a mouse and key

board. Keyboard interface allows bidirectional data transfers so the host device can

illuminate state LEDs on the keyboard. The clock and data signals are only driven when

data transfers occur and otherwise they are held in the idle state at logic high. The timing

define signal requirements for mouse – to – host communications and bidirectional

keyboard communications.

The keyboard uses open – collector drivers so that either

the keyboard or the host can drive the two – wire bus. If the host never sends data to the

keyboard, then the host use simple input pins. A PS/2 style keyboard uses scan codes to

communicate key press data. Nearly all keyboards in use today are PS/2 style. Each key

has a single unique scan code that is sent whenever the corresponding key is pressed. If

the key is pressed and held the keyboard repeatedly send the scan code every 100 ms or

so. When a key is released, the keyboard sends a “F0” key – up code, followed by the

scan code of the released key. The key - board sends the same scan code, regardless if a

key has different “shift” and “non shift” characters and regardless whether the shift key is

pressed or not. The host determines which character is intended.



A mouse generates a clock and data signal when moved,

otherwise these signals remain high indicating the idle state. Each time the mouse is

moved, the mouse send three 11 – bit words to the host. Each of the 11- bit words

contains a ‘0’ start bit, followed by 8 data bits, fallowed by odd parity bit, and terminated

with a ‘1’ stop bit. Each data transmission contains 33 total bits, where bits 0, 11 and 22

are ‘0’ start bits and bits 10, 21 and 32 are ‘1’ stop bits. A PS/2 mouse employs a relative

coordinate system where in moving the mouse to the right generates a positive value in

the x field and moving to the left generates a negative value in the y field and moving

down represents a negative value. The XS and YS bits in the status byte define the sign of

each value, where a ‘1’ indicates a negative value.

2.1.7: RS – 232 Port:

The Spartan – 3 starter kit board has an Rs – 232 serial

port. The Rs – 232 transmit and receive signal appear on the female DB9 connector. The

connector is a DCE style port and connects to the DB9 DTE – style serial port connector

available on most personal computers and work stations. Use a standard straight –

through derail cable to connect the Spartan – 3 starter kit board to the PC’s serial port.

The connection between the FPGA and the DB9 connector, including the maxim

MAX3232 RS - 232 voltage converter. The FPGA supplies serial output data as LVTLL

or LVCMOS levels to the maxim device, which in turn, converts the logic value to the

appropriate RS – 232 voltage level.

Signal FPGA Pin

RxD T13

TxD R13

RxD – A N10

TxD – A T14



An auxiliary Rs – 232 serial channel from

the maxim device is available on two 0.1 inch stake pins, indicated as J1 in

the schematic. The J1 stake pins are in the lower left corner of the board, to

the right of the DB9 serial connector, below the maxim RS – 232 voltage

translator and to the left of the individual LEDs. The transmitter output from

the maxim device driver the bottom stake pin while the receiver input

connects to the top stake pin.

2.1.8: Clock Sources:

The Spartan – 3 starter kit board has a dedicated 50 Mhz

series clock oscillator source and an optional socket for another clock oscillator source.

The 50 Mhz clock oscillator is mounted on the bottom side of the board, indicated. Use

the 50 Mhz clock frequency as is or derive other frequencies using the FPGAs digital

clock managers (DCMS).

Clock Oscillator Sources:

Oscillator Source FPGA Pin

50 MHz T9

Socket D9



2.2: Hyper Terminal:

Hyper Access is the name for a number of successive

computer communication software, made by Hilgraeve. It was the first software product

from Hilgrare and it was initially designed to let 8 – bit health communicate over a

modem. In 1985 this same product was ported to IBMPCs and compatible systems, as

well as health/ Zenith’s Z – 100 non – PC – compatible MS – DOS computer. over the

year the same version of this technology would be ported to other operating systems

including OS/2, windows 95 and windows NT. It has earned a total of five editors choice

awards form PC magazine. 1995 Hilgraeve licensed a low end version of Hyper Access,

known as Hyper Terminal to Microsoft for use in their set of communications utilities. It

was initially bundled with windows 95 and subsequently all versions all versions of

windows up to and including windows XP. Starting with windows vista, Microsoft no

longer bundled Hyper Terminal, thus windows 7 does not include it either. The

commercial products Hyper Terminal private edition and Hyper Access support all

versions of windows up to and including windows 7.

2.2.1: Protocols Supported:

2.2.1.1: Display:

Minitel, Viewdata, VT100, VT52.

2.2.1.1.1: Minitel:

The minitel is videotext online service accessible through the telephone line and is

considered one of the world’s most successful pre-world wide web online services. It was

launched in france in 1982 by the PTT(Poste telephone Telecommunications).



From it early days, user could make online purchases, make train reservations, check

stock prices, search the telephone directory. Have a mail box and chat in a similar way to

that now made possible by the internet.



2.2.1.1.2: Viewdata:

viewdata is a videotext implementation. It is a type of information retrieval

service in which a subscriber can access a remote data base via a common carrier

channel, receive requested data on a video display over a separate channel. Samuel fedida

was credited as inventor of the system. The access, request and reception are usually via

common carrier broadcast channels. This is in contrast with Tele text.

Viewdata Graphics used in the experimental phone directory of Post office

telecommunications in 1977. The image is a graphical representation of the post office/

British Telecom research laboratories in Suffolk, England. Note the “tecontinue” rather

than the correct “# Te continue”, showing a common rendering error.

2.2.1.1.3: VT100:

It was introduced in August 1987, following its predecessor, the VT52 and

communicated with its host system over serial lone using the ASCII character set and

control sequences standardized by ANSI. The VT100 was also the first digital mass –

market terminal to in corporate “Graphic rendition” as well as a selectable 80 or 132

column display.



All setup of the VT100 was accomplished using interactive displays presented on the

screen, the setup data was stored in non – volatile memory within the terminal. The

VT100 also introduced an additional character set that allowed the drawing of on – screen

forms.

2.2.1.1.4: VT52:

The VT52 was a CRT – base computer terminal produced by digital equipment

corporation introduced in September 1975. It provided a screen of 24 rows and 80

columns of text and supported all 95 ASCII characters as well as 32 graphics characters.

It supported asynchronous communication at baud rate’s up to 9600 bits per second and

did not require any fill characters. The terminal also introduced a separate function

keypad that allowed “gold key” editing.

2.2.1.2: File Transfer:

ASCII, Kermit, XMODEM, YMODEM/YMODEM – G,

ZMODEM.

2.2.1.2.1: ASCII:

Windows – 1252 also known as “ANSI”, other types of extended ASCII, often

just called “ASCII”. All 128 ASCII characters, including non – printable characters. The

95 ASCII graphic characters are numbered from 20 hex to 7Ehex (decimal 32 to 126).

The space character is considered a non – printing graphic.



The American standard code for information interchange is a character – encoding

scheme originally based on the English alphabet. ASCII code represent text in computers,

communications equipment and other devices that use text. Most modern character

encoding schemes are based on ASCII, though they support may more characters ASCII

does.

2.2.1.2.2: Kermit:

Kermit a computer file transfer, management protocol and a set of

communications software tools primarily used in the early years of personal computing in

the 1980s. it provides a consistent approach to file transfer, terminal emulation, script

programming and character set conversion across many different computer hardware and

OS platforms.

The Kermit protocol supports text and binary file transfers on both full – duplex and half

– duplex 8 bit and 7 bit serial connections in a system and medium - independent fashion

and is implemented on hundreds of different computer and operating system platforms.

2.2.1.2.3: XMODEM:

XMODEM is a simple file transfer protocol developed as a quick hack by

ward Christensen for use in his 1977 modem. ASM terminal program. XMODEM

become extremely popular in the early bulletin board system market, largely because it

was so simple to implement. It was also fairly inefficient and as modem speeds increased

this problem led to the development of number of modified versions of XMODEM to

improve performance or address other problems with the protocol. XMODEM like most

file transfer protocols, breaks up the original data into a series of “Packets” that are sent

to the receiver, along with additional allowing the receiver to determine whether that

packet was correctly received.



2.2.1.2.4: YMODEM :

It is a protocol for file transfer used between modems. YMODEM was

developed by check Forsberg as the success or XMODEM and MODEM 7 and was first

implemented in his CP/M YAM program. It was for molly given the name “YMODEM”

in 1985 by word Christensen. The original YMODEM was essentially the same as

XMODEM except that at sent the file’s name, size and time stamp in a regular

XMODEM block, “block 0”, before actually transferring the file. Sending the file size

solved XMODEM’s problem of super flours padding at the end of the file.

2.2.1.2.5: ZMODEM:

It is a file transfer protocol developed by chuck Forsberg in 1986, in a

project funded by telnet in order to improve file transfers on their X.225 network. In

addition to dramatically improved performance compared to older protocols, ZMODEM

also offered restorable transfers auto start by the sender, an expanded 32 bit CRC and

control character quoting, allowing it to be used on networks that might “eat” control

characters. ZMODEM become extremely proper on board systems in the early 1990,

displacing earlier protocols such as XMODEM.



2.3: VHDL:

2.3.1: Entity:

Entity is a most basic building block in a design.

2.3.2: Architecture:

Architecture describes the behavior of the entity.

2.3.3: Configuration:

A configuration can be considered like a parts list for a design. It describes

which behave to use for each entity, much like a parts to use for each part in the design.

2.3.4: Package:

Package is a collection of commonly used data types and subprograms used in a

design.

2.3.5: Driver:

This is a source on a signal. If a signal is driven by two sources, then when both

sources are active, the signal will have two drivers.

2.3.6: Bus:

Bus is a special kind of signal that may have its drivers turned off.

2.3.7: Attribute:

Attribute that are attached to objects or predefined data about objects.

2.3.8: Generic:

A generic is term for a parameter that passes information to an entity. If an

entity is a gate level model with a rise and a fall delay values for the rise and fall delay

could be passed into the entity with generics.

2.3.9: Process:

Process is the basic unit of execution in VHDL. All operations that are performed

in a simulation are broken into single or multiple processes.

2.3.10: Logical Operators:

NOT,AND,NAND,OR,NOR,XOR,XNOR.



2.3.11: Data Type:

2.3.11.1: Predefine Types:

Boolean : False , True.

Bit : ‘0’ , ‘1’.

Bit – vector : “101010”.

Integers : range – (2^(31 – 1)) to (2^(31-1)).

Floating real : -1.E38 to 1.0E38.

Time

Character

String

Enumerated (User defind)

Records, File, Access type (Used in simulation only)

Note:

‘U’ �� Uninitialized.

‘X’ �� Forcing Unknown.

‘0’ �� Forcing 0.

‘1’ �� Forcing 1.

‘Z’ �� High Impedance.

‘W’ �� weak Unknown.

‘L’ �� Weak 0.

‘H’ �� Weak 1.

‘—‘ �� Do not care.



2.3.12: Operator:

2.3.12.1: Relational Operator:

= : Equals.

/= : Not Equals.

< : Less than

>: Greater than

<= Less than or equal

>= Greater than or equal

2.3.13: Process and sequential statements:

Process exist inside the Architecture.

Process have local variables. Processes contain sequential statements. Processes have a

sensitivity list or optional wait statement. Process execute only when a signal in the

sensitivity list changes. Processes can be used to make clocked circuits.

Syntax : Process(optional sensitivity list)

---- local process declarations

begin

---- Sequential statements

End process

Process must have a sensitivity list or a wait statement but never both.



2.3.13: Sequential – If statement:

Used inside the process. It can be used to control

variable and signal assignments. It has optional elseif structure.

Syntax: if <condition>then

---- sequential statements.

elseif <condition>then

---- sequential statements

else

---- sequential statements

endif

2.3.14: Signals:

Signal behave like wire. Signal can be local to an architecture. Signal have no

mode. Signal must have type. Signal carry information between process.

Syntax: architecture sig of show is

signal_name1, signal_name2 : type.

OR

Signal signal_name1; signal signal_name2;

begin

2.3.15: Attributes:

Provide additional information about many VHDL objects. It can be

assigned to most objects including signals, variables, architectures and entities. Many

attributes are predefined by VHDL, however user defined attributes are also allowed.

VHDL pre- defines five of attributes, dependent on the return value type which can be:

value, function, signal, type, range.



2.3.16: Value Attributes:

‘Right’ returns right most value in array. ‘Left’ returns left most

value in array. ‘high’ returns highest index of an array. ‘low’ returns lowest index of an

array. ‘length’ returns the length of an array. ‘ascending’ returns Boolean true if array is

ascending.

2.3.17: Function Attributes:

‘event returns true if the signal had an immediate event on it.

‘active returns true if the signal had a scheduled event on it in the current cycle.

‘last_event returns time since the last event on a signal. ‘last_value returns the value of a

signal prior to an event. ‘last_active returns the time since the last scheduled event on a

signal.

Note: rising_edge is a function pre defined, falling_edge also pre defined defined.

2.3.18: Constants:

Useful for – look up tables, -- Holding circuit parameters, -- ROM

functions. Most be declared before they can be used. Constants can be declared in entity,

architecture, process, procedure, package or function.

2.3.19: Constant declaration:

Constant name_of_constant : type := value of constant;

2.3.20: Entity Ports and Mode:

The mode out problem: entity port signal of mode out can

not feedback into the entity. Use a local signal for feedback. Buffer mode can be used for

feedback. Using mode buffer can cause problems with nested entities. A wire running

straight through multiple levels of entities must be mode buffer in all entities if it is mode

buffer in any entity. examples in this class will use local feedback.

2.3.21: Enumerated Types:

Enumerated types can be user defined. All values must

have unique names. It can be used to hold the states of state machine. Declare a new type

with the type keyword ‘(‘ specify the range of value the new type can have. Make a

signal / Variable assigning it the new type.

Syntax: Type <type_name> is (<string1>), <string2>, …….);



2.3.22: Recipe coding of state machines:

Use two state variables, one for present state

and one for next state. Write two processes: process 1 � create next state from present

state and control inputs. Assign output based on present state. Process 2 �

Asynchronous reset, optional enables. Clock next state into present state.

2.3.23: Hierarchy:

2.3.23.1: Hierarchy a first look:

Using components and port maps, External design files, system

supplied ports.

2.3.23.2: Component Declaration:

A declaration statements does not create new logic. Used

inside the architecture before begin. Component must be declared before they can be

used. Components are used to point the synthesis engine to other entities. Other entities

can be in the design directory or located in libraries.

Syntax: Component component_name

Generic (generic_list);

Port(Port_list);

End component;

2.3.24: Port Map:

Used in conjunction with component to instantiated a port. Used to map

signals into a component. Can map by position or name.

Syntax: two methods positional and name association.

2.3.25: User defined Arrays:

array must be declared before use. Array members must

have a type. Be careful with more then two dimensional arrays for synthesis, after works

in simulation and not synthesis.

Syntax: Type array_name is array (range) of type of array member;



2.4: Verilog:

Verilog is a hardware description language (HDL). HDL is used to

describe a digital system for example, a network switch, a microprocessor or a memory

or simple flip – flop. Verilog is case sensitive. All verilog keywords are lower case.

Identifier are name used to given an object, such as a register or a function or a module, a

name so that it can referenced from other places in a description.

Design Styles:

. Bottom up Design

. Top down Design

2.4.1:Abstraction Level of Verilog:

. Behavioral level

. Register – Transfer level

. Gate level

2.4.1.1: Behavioral level :

The level describes a system by concurrent algorithms (Behavioral).

Each algorithm itself sequential, that means it consists of instructions that executed one

after the other. Functions, tasks, always blocks are the main elements.

2.4.1.2: Register – Transfer level:

Designs using the register – transfer level specify the

characteristics of a circuit by operations and the transfer of data b/w registers. Modern

definition of RTL code is “any code that is synthesizable is called RTL code”. RTL

design contains exact timing possibility, operations are scheduled to occur at certain

times.



2.4.1.3: Gate level:

Within the logic level the characteristics of a system are described by logical

links and their timing properties. All signals are discrete signal. They can only have

definite logical values (‘0’,’1’,’X’,’Z’). The usable operation are predefined logic

primitives (AND, OR, NOT). Using gate level modeling might not be a good idea for any

level of logic design. Gate level code is generated by tools like synthesis tools and this

net list is used for gate level simulation and for backend. Verilog has built in primitives

like gates, transmission gates and switches. Gates have one scalar O/P and multiple scalar

I/P. The 1st terminal in the list of gate terminals is an O/P and other terminals are I/P.

transmission gates are bi – directional and can be resistive or non resistive. Transmission

gate tran and rtran are permanently on and do not have a control line. Tran used to

interface two wire with separate drives and rtran can be used to weaken signals. Resistive

devices reduce the signal strength which appears on the output by one level. All the

switches only pass signals from source to drain, incorrect wiring of the devices will result

in high impedance output.

2.4.2: Gate and Switch delays:

2.4.2.1: Rise delays:

Rise delay is associated with a gate output transition to 1 from another

value (0, X, Z).

2.4.2.2: Fall delays:

The fall delay is associated with a gate O/P transition to 1, X, Z from

another value.

2.4.2.3: Turn – off delays:

Gate output transition to Z from another value (0, 1, X).

2.4.2.4: Minimal delays:

Minimum delay value that the gate is expected to have.

2.4.2.5: Typical delays:

Typical delay value that the gate is expected to have.



2.4.2.6: Maximum delays:

Maximum delay value that the gate is expected to have.

Verilog has built in primitives like gates, transmission gates and switches. This is rather

small number of primitives, if we need more complex primitives, then verilog provides

UDP or simply user defend primitives. By using UDP we can model Combinational logic

and sequential logic.

2.4.3: Identifiers:

Identifiers must start begin with an alphabetic character or the underscore

character(‘_’). Identifiers may contain (a – z, A – Z, _ , $). Identifier can be long up to

1024 character.

2.4.4: Data Types:

2.4.4.1: Nets:

Represents structural connections between components.

2.4.4.2: Registers:

Represent variable used to store data.

2.4.4.3: Register data types:

Register store the last value assigned to them until another

assignment statement changes their value. Register represent data storage constructs. You

can create arrays of register called memories. Register data types are used as variables in

procedural blocks. A register data type is required if a signal is assigned a value with in a

procedural block. Procedural blocks begin with keyword initial and always.

reg: unsigned variable.

integer: signal variable – 32 bits.

time: unsigned integer – 64 bits.

Real: Double precision floating point variable.



2.4.5: String: A string is a sequence of characters enclosed by double quotes and all

contained on signal line. One eight – bit ASCII value representing one character. No

extra bits are required to hold a termination character.

\n � New line character.

\t � Tab character.

\\ � Back slash (\) character.

\” � Double quote (“) character.

\ddd � A character specified in 1 – 3 octal digits.

%% � Percent (%) character.

2.4.6: Operators:

2.4.6.1: Logical Operators:

! (NOT), && (AND), || (OR).

2.4.6.2: Bit – wise Operators:

~ (Negation), & (AND), | (Inclusive OR), ^ (Exclusive OR), ^~ or

~^ (Exclusive NOR).

2.4.6.3: Reduction Operators:

& (AND), ~& (NAND), | (OR), ~| (NOR), ^~ or ~^

(XNOR), ^ (XOR).

2.4.6.4: Shift Operators:

<< (Left Shift), >> (Right Shift). The left operand is shifted by the

number of bit positions given by the right operand. The vacated bit positions are filled

with zeroes.

2.4.6.5: Concatenation Operators:

{}.

2.4.6.6: Replication Operators:

{{}}.



2.4.6.7: Conditional Operators:

Cond_expr ? True_expr : False_expr.

2.4.7: Procedural Blocks:

Two type of procedural blocks in verilog.

2.4.7.1: Initial:

Initial blocks execute only once at time zero.

2.4.7.2: Always:

Always blocks loop to execute over and over again, in other words as name

means, it executes always. Always blocks waits for the event, here positive edge of clock,

where as initial block without waiting just executed all the statements within begin and

end statement.

If a procedure block contain more than one statement, those statement

must be enclosed within:

a) Sequential begin – end Block.

b) Parallel Fork – join Block.

2.4.8: Blocking Assignment:

Blocking assignment are executed in the order they are coded,

hence they are sequential. Since they block the execution of next statement, till current

statement is executed, they are called blocking assignments.

Symbol � =

2.4.9: Non – Blocking Assignment:

Non Blocking assignment are executed in parallel. Since

the execution of next statement is not blocked due to execution of current statement, they

are called non blocking statement.

Symbol � <=



2.4.10: Conditional Statement if – else:

when more than one statement needs to be executed

for a if conditions, then we need to use begin and end. We normally do not include reset

checking in priority as this does not fall in the combo logic input to the flip – flop. When

we need priority logic, we use next if – else statements. On other end if we do not to

implement priority logic, knowing that only that only one I/P is active at a time.

2.4.11: Case Statement:

The case statement compares a expression to a series of cases and

executes the statement or statement group associated with the first matching case. Case

statement supports single or multiple statements. Group multiple statements using begin

and end keywords.

2.4.12: Loop Statements:

2.4.12.1: Forever:

Forever statement executes continually, the loop never ends. Narmally we

use forever statement in initial blocks.

Syntax : forever <Statement>.

If no timing construct is present in the forever statement, simulation could hang.

2.4.12.2: Repeat:

The repeat loop executes statement fixed <number> of times.

Syntax: repeat <Number> <Statement>.

2.4.12.3: While:

The while loop executes as long as an evaluates as true.

Syntax : while ().

2.4.12.4: For:

Syntax: for (initial assignment; expression; step assignment);

Note : i ++ does not have in verilog. i = i + 1 in verilog.



2.4.13: Continuous Assignment statements:

Continuous assignment statements drives

nets. They represent structural connections.

a) They are used for modeling tri – state buffers.

b) They can be used for modeling combinational logic.

c) They are outside the procedural blocks.

d) The continuous assign overrides any procedural assignments.

e) The left – hand side of a continuous assignment must be net data types.

Syntax : Assign (strength, strength) # (delay) net = expression;

2.4.14: Propagation Delay :

Continuous assignments may be have a delay specified,

only one delay for all transitions may be specified.

Syntax : assign #(A minimum : Typical : maximum delay range may be specified)

To model sequential logic, a procedure block must be

sensitive to positive edge or negative edge of clock. Model asynchronous reset, procedure

block must be sensitive to both clock and reset. All the assignments to sequential logic

should be made through non blocking assignments. Some time it tempting to have

multiple edge triggering variables in the sensitive list, this is fine for simulation, but for

synthesis this does not make sense. Delays the execution of a procedural statement by

specific simulation time.

Syntax : # <Time> <Statement>.

Delays the execution of the next statement until the specified

transition on a signal. {edge sensitive event controls}

Syntax: @(<Posedge > | <Negedge> signal) <statement>.

Level – Sensitive even controls (Wait statements) delay execution

of the next statement until the evaluates as true.

Syntax : Wait().

Intra – assignment timing controls evaluate the right side

expression right always and assigns the result after the delay or event control. In non –

intra – assignment controls right side expression evaluated after delay or event control.



Syntax: a = # 10 2.{intra – assignment}.

Modeling combo logic with continuous assignments, whenever any

signal changes on the right hand side, the entire right hand side is re – evaluated and the

result is assigned to the left hand side.

2.4.15: Task :

Task are used in all programming languages, generally known as procedures or

sub routines. Task are defined in the module in which they are used. It is possible to

define task in separate file and use compile directive include to include the task in the file

which instantiates the task. Task can include timing delays, like posedge, negedge, #delay

and wait. Task can have any number of I/P and output. The variables declared within the

task are local to that task. Task can take, drive and source global variables, when no local

variables are used. Task can call another task or function. Task can be used for modeling

both combinational and sequential logic. Task begin with keyword task and end’s with

keyword task. Local variables are declared after I/P and O/P declaration.

2.4.16: Function:

Function is same as task, with very little difference, like function can not

drive more then one output, can not contain delays. Function can not include timing

delays, like posedge, negedge, #delay. Function executed in zero time delay. Function

can have any number of I/P but only one output. Function can call other functions, but

can not call task.

2.4.17: $display:

Display once every time they are executed.

2.4.18: $monitor:

Display every time, one of its parameters changes.

2.4.19: $Strobe:

Display the parameters at the very end of the current simulation time unit

rather than exactly where it is executed.



2.4.20: $time :

Return the current simulation time as a 64 – bit.

2.4.21: $Stime:

Return the current simulation time as a 32 – bit.

2.4.22: $realtime:

Return the current simulation time a real number.

2.4.23: $reset:

It resets the simulation back to time 0.

2.4.24: $stop:

Halts the simulator and puts it in the interactive mode, where user can enter

commands.

2.4.25: $finish:

exits the simulator back to the operating system.

2.4.26: $random:

it generates a random integer every time it is called.

Note :

%d �� decimal

%h �� hexadecimal

%b �� binary

%c �� character

%s �� string

%5d �� gives exactly 5 spaces for the number.

2.4.27: Initializing Memories:

A memory array may be initialized by reading memory

pattern file from disk and storing it on the memory array by using $ readmemb and $

readmemh.



2.4.27.1: $redmemb:

It is used for binary representations of memory content.

2.4.27.2: $readmemh:

it is used for hex representation of memory content.

Syntax : $readmemh (“file – name”, mem-array, start_adder, stop_addr).



2.5: Xilinx ISE Design Suite 13.1:

2.5.1: Getting started:

2.5.1.1: Hardware Requirements:

Spartan -3 startup kit, Containing the

Spartan – 3 startup kit demo board.

2.5.1.2: Starting the ISE Software:

To start ISE, Double – click the desktop icon

OR

Start � All Programs � Xilinx ISE 13.1 � Project Navigator.

2.5.2: Create a New Project:

Select File � New Project � Type Project Name

� Enter or Browse to allocation (directory path) for the new project. A tutorial

subdirectory is created automatically. � Verify that HDL is selected from the Top –

Level source type list � click Next � Fill in the properties in the table as shown below:

Product category All

Family Spartan 3

Device XC3S200

Package FT256

Speed Grade -4

Top – Level Source HDL

Synthesis Tool XST (VHDL/Verilog)

Simulator ISE simulator (VHDL/Verilog)

Preferred Language VHDL/Verilog

. Click Next.



2.5.3: Create an HDL Source:

2.5.3.1: Creating a VHDL /Verilog Source:

. Click the New Source button in the New Project Wizard.

. Select VHDL module/Verilog module.

. Type the file name.

. Verify that the Add to Project check box is selected.

. Click Next.

. Click Finish.

2.5.3.2: Checking the Syntax of the design source:

. Verify that Synthesis/Implementation is selected from the drop – down list in the

sources window.

. Select the design source in the sources window to display the related processes in the

processes window.

. Click the “+” next to the synthesize – XST process to expand the process group.

. Double – Click the check syntax process.

. Close the HDL file.



2.5.4: Design Simulation:

2.5.4.1: Verifying Functionality using Behavioral Simulation:

. Select the design HDL file in the sources window.

. Create a new test bench source by selecting project � New Source.

. In the New Source wizard, select test bench waveform as the source type and type

design_TB in the file name field.

. Click Next.

. The associated source page shows that you are associating the test bench wave form

with the source file design. � Click Next.

. The summary page shows that the source will be added to the project and it displays the

source directory, type and name. � Click Finish.

. The requirements for this design are the following:

a) The counter must operate correctly with an input clock frequency =

25MHz.

b) The direction input will be valid 10ns before the resing edge of clock.

c) The output must be valid 10ns after the rising edge of clock.

. Fill in the field in the initialize timing dialog box with the following information.

a) Clock High Time : 20ns.

b) Clock Low Time : 20ns.

c) Input Setup Time : 10ns.

d) Output valid Delay : 10ns.

e) Offset : on

f) Global Signals : GSR (FPGA).

g) Initial Length of Test Bench : 1500ns.

. Click Finish to complete the timing initialization.



2.5.4.2: Simulating Design Functionality:

Verify that counter design function as you

expect by performing behavior simulation as follows :

a) Verify that Behavioral Simulation and design_TB are selected in the sources

window.

b) In process tab, click the “+” to expand the Xilinx ISE simulator process and

double – click the simulate behavioral module.

c) The ISE simulator opens and runs the simulation to the end of the test bench.

d) To view your simulation results, Select the simulation tab and zoom in an the

transitions.

e) Save the waveform.

f) Select the Behavioral simulation view to see that the test bench waveform file is

automatically added to your project.

g) Close the test bench waveform.

2.5.4.3: Simulating Design Functionality:

Verify that the design function as you expect by performing behavior simulation as

follows:

. Verify that behavioral simulation and design_TB are selected in the sources window.

. In the processes tab, click the “+” to expand the Xilinx ISE simulator process and

double click simulate behavioral mode process.

. The ISE simulator opens and runs the simulation to the end of the test bench.

. To view your simulation results, select the simulation tab and zoom in on the

transitions.

. Verify that the design is working as expected.

. Close the simulation view.



2.5.4.4: Create Timing Constraints:

Specify the timing between the FPGA and

it’s surrounding logic as well as the frequency the design must operate at internal to the

FPGA. The timing is specified by entering constraints that guide the placement and

routing of the design. It is recommended that you enter global constraints. The clock

period constraints specifies the clock frequency at which your design must operate inside

the FPGA. The offset constraints specify when to expect valid data at the FPGA inputs

and when valid data will be available at the FPGA outputs.

2.5.5.5.1: Entering timing constraints:

a) Select synthesis/Implementation from the drop – down list in the sources window.

b) Select the design HDL source file.

c) Click the “+” sign next to the user constraints processes group and double – click the

create timing constraints process.

d) Click yes to add the UCF file to your project.

e) Select clock in the clock net name field, then select the period toolbar button or double

- click the empty period field to display the clock period dialog box.

f) Enter 40ns in the time field.

g) click ok.

h) select the pad to setup tool – bar button or double – click the empty pad to setup field

to display the pad to setup dialog box.

i) Enter 10ns in the OFFSET field to set the input OFFSET constraint.

j) click ok.

k) select the clock to pad toolbar button or double – click the empty clock to pad field to

display the clock to pad dialog box.

l) Enter 10ns in the OFFSET field to set the output delay constraint.

m) click OK.

n) Save the time constraints. If you are prompted to rerun the translate or XST set, click

ok to continue.

o) Close the constraints editor.



2.5.5.6: Implement Design and Verify Constraints:

Implement the design and

verify that it meets the timing constraints specified in the previous section.

6.5.5.6.1: Implementing the design:

a) Select the design source file in the sources file in the sources window.

b) Open the design summary by double – clicking the view design summary process in

the processes tab.

c) Double – click the implement design process in the processes tab.

d) Notice that after implementation is complete, the implementation processes have a

green check mark next to them check mark next to them indicating that they completed

successfully without error or warnings.

e) Locate the performance summary table near the bottom of the design summary.

f) Click the all constraints met link in the timing constraints field to view the timing

constraints report. Verify that design meets the specified timing requirements.

2.5.5.6.2: Assigning Pin Location Constraints:

Specify the pin locations for the ports of the

design so that they are connected correctly on the Spartan – 3 startup kit demo board.

To constrain the design ports to package pins, do the following:

A) Verify that design is selected in the sources window.

B) Double – click the assign package Pine process found in the user constraints

process group.

C) Select the package view tab.

D) Select File � Save.

E) Close PACE.



2.5.5.6.3: Re implement Design and Verify Pin Locations:

Reimplement the design and

verify that the ports of the design are routed to the package Pins specified in the previous

section.

A) Open the design summary by double – clicking the view design summary process

in the processes window.

B) Select the pin out report and select the signal name column header to sort the

signal names.

C) Re implement the design by double – clicking the implement design process.

D) Select the pin out report again and select the signal Name column header the sort

the signal names.

E) Verify that signals are now being routed to the correct package pins.

F) Close the design summary.

2.5.5.6.4: Design to the Spartan Board:

A) Connect 5v DC power cable to the power input on the board.

B) Connect the download cable between the PC and board.

C) Select synthesis/ Implementation from the drop – down list in the sources window.

D) Select design in the sources window.

E) Click the “ +” sign to expand the generate programming file processes.

F) Double – click the configure device (iMPACT) processes.

G) The Xilinx web talk dialog box may open during this process. Click decline.

H) Select disable the collection of device usage statistics for this project only and click

ok.

I) Select configure devices using boundary – scan(JTAG).

J) Verify that Automatically connect to a cable and identify boundary – scan chain is

selected.

K) Click finish.



L) Assign New configuration file dialog box appears to assign a configuration file to the

XC3s200 device in the JTAG chain.

M) If you get a warning message. Click ok.

N) Select bypass to skip any remaining devices.

O) Right – click on the XC3s200 device image and select program.

P) Click OK.

Q) Close iMPACT without saving.



Chapter 3: Research Methodology/Experimental Setup:

3.1: UART:

3.1.1:Introduction

An UART (universal asynchronous receiver/transmitter) is responsible for

performing the main task in serial communications with computers. The device

changes incoming parallel information to serial data which can be sent on a

communication

line.

UART is circuit that sends parallel data through a serial line. UART are frequently

used in conjunction with the electronic industries alliance RS-232 standard, ethic

specifies the electrical, mechanical, functional and procedural characteristics of

two data communication equipment. Because the voltage level defined in RS-232

is different from that of FPGA input/output, a voltage converter chip is needed

between a serial port and an FPGA’s input/output pins. The S3 board has RS-

232 port with the standard nine- pin connector. The board contains the necessary

voltage converter chip and configures the various RS- 232’s control signals to

automatically generate acknowledgment for the PC’s serial port. A standard

straight through serial cable can be used to connect the S3 board and PC’s serial

port. The S3 board basically handles the RS- 232 standard and we only need to

concentrate on the design of the UART circuit.



3.1.2: Pin diagram of the UART:

LED_OUT[7:0]

CLK

Rx

Tx

Pin Diagram Of UART

3.1.3: Pin description of the UART:

PIN Name INPUT/OUTPUT DESCRIPTION

CLK INPUT operating clock

Rx INPUT signal is used for one bit input

Tx OUTPUT signal is used for one bit out

LED_OUT OUTPUT(FPGA Led) signal is used for 8 bit data bus for

display on FPGA



3.1.4: Block Diagram of UART:

3.1.5: Functional Description of UART:

UART include baud rate generator for receiver, Receiver

Subsystem, baud rate generator for transmitter, Transmitter subsystem and asynchronous FIFO

interface circuit. UART is a circuit that send parallel data through serial line. Clock (clk) is input

for the baud rate generator of receiver and baud is output of baud rate generator for receiver.

Output (baud) of baud rate generator for receiver is input of baud rate generator for transmitter

and Tx_baud is output of the baud rate generator for transmitter. Output (baud) of baud rate

generator for receiver and Rx (one bit signal) are inputs of UART receiver sub system. Baud used

as clock signal for UART receiver sub system and taking Rx as a input and gives the 8 bit data as

out put. Receiver sub system shift the Rx input bit by bit and then reassemble the data. Output

(Tx_baud) of baud rate generator for transmitter and data_in (8 bit ) data and data_in_enable are

input for transmitter sub system. Tx_baud used as clock signal for UART Transmitter sub system

and then gives one bit Tx output. Transmitter sub system load the 8 bit data parallel and shift the

data bit by bit. Asynchronous FIFO interface circuit. Tx_baud(output of baud rate generator for

transmitter(Tx_baud)), Rx_baud(output of baud rate generator for receiver(baud)),

data_in_enable (output of receiver sub system (byte_done)),data_in 8 bit (output of receiver

subsystem( data_out)) are input of Asynchronous FIFO and then output data_out 8 bit,

data_out_enable signal. Rx_baud used as clock signal for writing data in memory and Tx_baud

used as clock signal for reading data from memory.



3.1.6: Baud rate generator for Receiver

The baud rate generator generates a

sampling signal whose frequency is exactly 16 time of the UART’s designated baud rate.

For 19,200 baud rate, the sampling rate has to be 19,200 X 16. Which is 307,200. Since

the clock rate is 50 MHz

The baud rate generator needs a mod 163 counter. We can calculate mod count by

using formula

Mod count = [system clock rate / (baud rate X 16)]

Mod count = [50 MHz / (19,200 X 16)]

= [(50 X 10^6) / ( 19,200 X 16)]

= [50 x 10^6) / 307200]

= 163 count.

3.1.7: FSM of Baud rate generator:



3.1.8: Functional Description of FSM in each state:

State S0 : here count is input for state S0.

When count >= 0 and count <= 81 then baud set to be Low.

When count > 81 then it goes to next state S1.

State S1: here also count is input for state S1.

When count > 81 and count < 163 then baud set to be high.

When count = 163 then it goes to next state S0.

Initial value of count set to be 0. Each and every posedge clock(clk) the comparator

checks or we can say compare the count value and register value. If count value equal

to register value then comparator generate high signal which is 1. If count value not

equal to register value then comparator generate low signal which is 0. If comparator

generate high signal then count become 0. If comparator generate low signal then count

get incremented by one in each and every posedge clock(clk).



3.1.9: Baud rate generator for transmitter

No over sampling involved, the

frequency of the mode count is 16 times slower the UART receiver. Transmitter

baud rate generator use 16 times deviser in receiver baud rate generator

output(baud) and generate the Tx_baud_rate.

3.1.10: FSM of baud rate generator for Transmitter:



3.1.11: Functional Description of FSM in each state:

State S0 : here count is input for state S0.

When count >= 0 and count <= 7 then baud set to be Low.


State S1: here also count is input for state S1.

When count > 7 and count <= 15 then baud set to be high.


Initial value of count set to be 0. Each and every posedge clock(baud_clk) the

comparator checks or we can say compare the count value and register value. If count

value equal to register value then comparator generate high signal which is 1. If count

value not equal to register value then comparator generate low signal which is 0. If

comparator generate high signal then count become 0. If comparator genrate low signal

then count get incremented by one in each and every posedge clock(baud_clk).



3.1.12: UART Receiver sub system:

Since no clock information is conveyed from

the transmitted signal, the receiver can retrieve the data bits only by using the

predetermined parameters.

3.1.12.1: Oversampling:

The most commonly used sampling rate is 16 times the baud

rate, which means that each serial bit is sampled 16 times.

Assume that the communication uses N data bits and M stop bits.

a) Wait until the incoming signal becomes low which is 0. The begging of the start

bit and then start the sampling tick counter.

b) When the counter reaches 7, the incoming signal reaches the middle point of the

start bit. Clear the counter to 0 and reset it.

c) When the counter reaches 15 the incoming signal reaches the middle point of the

1st bit. Retrieve its value, shift it into a register and restart the counter.

d) Repeat step 3 N-1 more times to retrieve the remaining data bits.

e) Repeat stop 3 M more time to obtain the stop bits.



3.1.12.2: FSM of UART receiver sub system:



3.1.12.3: Functional Description of FSM in each state:

State S0 : here Rx(one bit) is input for state S0.

When Rx = high, then count1, byte_done1 and byte_done set to be Low.

When Rx = low, then it goes to next state S1.

State S1: here count1 is input for state S1.

When count1 >= 0 and count1 < 7, then count2 set to be 0 and count1 get

incremented by one with each posedge clk.

When count1 > 7, then it goes to next state S2.


When count2 >= 0 and count2 < 15, then count2 get incremented by one

with each posedge clk.

when count2 = 15, then it goes to next state S3.

State S3: here Num is input for state S3.Num signal used to indicate position of data bit.

When num >= 0 and num < 8, then it goes to next state S2. Corsponding

to num value the data bit shifted in the 8 bit register.

When num = 8, then it goes to next state S4.


When count3 >= 0 and count < 15,then num set to be 0 and count3 get

incremented by one with each posedge clk.

When count3 = 15, then it goes to next state S5.

State S5: here byte_done1 is input for state S5.

When byte _done = low, then byte_done set to be high and 8 bit data bus

Assign to data_out.

When byte_done = high, then it goes to next state S0.



3.1.13: Transmitter sub system.

UART transmitter is essentially a shift register

that shifts out data bit at a specific rate.

The rate can be controlled by one- clock- cycle enable ticks generated by the

baud rate generator of transmitter.

3.1.13.1: FSM of Transmitter sub system:




State S0: here data_in_enable is input for state S0.

When data_in_enable = low, then Tx set to be high.

When data_in_enable = high, then Tx set to be Low. it goes to next

state S2.

State S2: here count is input for state S2, here count indicate position of data bit .

When count < 8, then Tx set to be Low or high corresponding bit

value of data_in with respect to count value.

When count = 8, then Tx set to be high. It goes to next state S0.

Each and every clock (Tx_baud_clk) comparator compare the Flag signal

and register. If Flag signal equal to register then comparator output will be

high which is 1. If Flag signal not equal to register then comparator output will

be Low. If comparator output is high then count will get incremented by one in

each and every Tx_baud_clk. If comparator output is low then count will

become 0.



3.1.14: asynchronous FIFO Interface circuit

The receiver’s interface circuit

has two functions.

a) It provides a mechanism to signal the availability of a new word and to

prevent the received word from being retrieved multiple time.

b) It can provide buffer space between the receiver and the main system.

There are tree commonly used schemes :

a) A flag FF

b) A flag FF and one word buffer

c) A FIFO buffer

The old word will be over written, an error known as data overrun. FIFO is

used in the project to prevent the overrun problem.



3.1.14.1: FSM of write in FIFO:


State S0 : here data_in_enable is input for state S0.

When data_in_enable = low, then wr_done set to be low.

When data_in_enable = high, then it goes to next state S1.

State S1 : here wr_done is input for state S1.

When wr_done = low, then wr_address get incremented by one with

respect to each and every posedge clk and corresponding to wr_address the

incoming data stored in the FIFO memory.

When wr_done = high, then it goes to next state S0.



3.1.14.3: FSM OF READ FIFO:

3.1.14.4: Functional Description of FSM in each state

state P0: here Flag is input for state P0.

When Flag = low, then flag count and rd_done set to be low.

When Flag = high, then it goes to next state P1.

state P1: here Rd_done is input for state P1.

When Rd_done = low, then rd_addrss get incremented by one with

respect to each and every posedge clk and corresponding to rd_addrss the data is

taken out from the memory.

When Rd_done = high, then it goes to the next state P2.

state P2: here count is input for state P2.

When count >= 0 and count < 8, then rd_done and data_out_enable set

to be low.

When count = 8, then it goes to next state P0.



Each and every clock (Tx_baud_clk) comparator compare the Flag Count

signal and register. If Flag Count signal equal to register then comparator

output will be high which is 1. If Flag Count signal not equal to register then

comparator output will be Low. If comparator output is high then count will get

incremented by one in each and every Tx_baud_clk. If comparator output is

low then count will become 0. Another comparator is used to compare the

count value and register value. If register value is equal to count then

comparator output will be high and count set to be 0. If register value is not

equal to count value then comparator output will be low and count will get

incremented by one in each and every posedge clock(Tx_baud_clk).



3.2: VGA:

A video controller generates the synchronization signals and outputs data

pixel serially. It contains a synchronization circuit, labeled VGA_Sync, a pixel generation

circuit. The VGA_Sync circuit generates timing and synchronization signals. The Hsync

and Vsync signal are connected to the VGA port to control the horizontal and vertical

scans of the monitor. Two signals are decoded from the internal counters, whose outputs

are the pixel_x and pixel_y signals.the pixel_x and pixel_y signal indicate the relative

positions of the scans and essentially specify the location of the current pixel. The

VGA_sync also generates the video_on signal to indicate whether to enable or disable the

display. The pixel generation circuit generates the three vido signal, which are

collectively referred to as the RGB signal. A color value is obtained according to the

current cording to the current coordinates of the pixel (the pixel_x and pixel_y signal)

and the external control and data signals.

3.2.1: VGA Synchronization:

The video synchronization circuit generates the hsync signal.

Hsync signal specifies the required time to traverse (scan) a row and vsync signal, which

specifies the required time to traverse (scan) the entire screen. Discussions are based on

640 by 480 VGA screen with a 25 MHz pixel rate, which means that 25M pixels are

processed in a second. This resolution is also known as the VGA mode. The coordinate

of the vertical axis increases downward. The coordinates of the top – left and bottom –

right corners are (0,0) and (639,479), respectively.



3.2.2: Horizontal Synchronization:

A detailed timing diagram of one horizontal scan. A period

of the hsync signal contains 800 pixels and can be divided into four regions.

3.2.2.1:Display: Region where the pixels are actually display on the screen. The length

of this region is 640 pixels.

3.2.2.2: Retrace: Region in which the electron beams return to the left edge. The video

signal should be disabled (i. e. , black), and the length of this region is 96 pixels.

3.2.2.3: Right border: Region that forms the right border of the display region. It is

also known as the front porch (i. e. , porch before retrace). The video signal should be

disabled and the length of the region is 16 pixels.

3.2.2.4: Left border: Region that forms the left border of the display region. It is also

know as the back porch (i. e. , porch after retrace). The video signal should be disabled

and the length of this region is 48 pixels.

The hsync signal can be obtained by a special mod

– 800 counter and a decoding circuit. Start the counting from the beginning of the display

region. This allows us to use the counter. This allows us to use the counter output as the

horizontal (X- axis) coordinate. This output constitutes the pixel – x signal. The hsync

signal goes low when the counter’s output is between 656 and 751. CRT monitor should

be block in the right and left borders and during retrace. We use the h_video_on signal to

indicate whether the current horizontal coordinate is in the displayable region. It is

asserted only when the pixel count is smaller than 640.



3.2.2.5: FSM of Horizontal Synchronization:



3.2.2.6: Vertical Synchronization:

During the vertical scan, the electron beams move grodully

from top to bottom and then return to the top. This corresponds to the time required to

refresh the entire screen. The time unit of the movement is represented in terms of

horizontal scan lines. A period of the Vsync signal is 525 lines can be divided into four

regions.

3.2.2.6.1: Display: Region where the horizontal lines are actually displayed on the

screen. The of this region is 480 lines.

3.2.2.6.2: Retrace: Region that the electron beams to the top of the screen. The vido

signal should be disabled and the length of this region is 2 lines.

3.2.2.6.3: Bottom Border: Region that forms the bottom border of the display region. It

is also known as the front porch (i. e. , porch before retrace). The video signal should be

disabled and the length of this region is 10 lines.

3.2.2.6.4: Top Border: Region that forms the top border of the display region. It video

signal should be disabled and the length of this region is 33 lines.

3.2.3.1: FSM of Clock for vertical synchronization:



3.2.3.2: FSM of Vertical synchronization:

3.2.4: Timing Calculation of VGA synchronization signals:

Pixel rate is determined by three parameters:

P� The number of pixels in a horizontal scan line. For 640 – by – 480 resolution, it is P

= 800 pixels/Line.

L � The number of lines in a screen () for 640 – by – 480 resolution, it L = 525 lines/

screen.

S � The number of screens per second. For flicking free operation, we can set to S � 60

screens/ Second.

The S parameter specifies how fast the screen should be

refreshed. For a human eye, the refresh rate must be at least 30 screens per second to make to

monitor usually has a much higher rate, such as the 60 screens per second specification above.

The pixel rate can be calculated by the three parameters :

Pixel Rate = P * L * S = 25 M Pixels/Second.



3.2.5: Overview Of the pixel Generation circuit:

The Pixel generation circuit generates the 3

– bit RGB signal for the VGA port. The external control and data signals specifify the

content of the screen and the screen and the pixel_x and pixel_y signals from the VGA

_sync circuit provide the current coordinates off the pixel. We divided this circuit into

three broad categories:

3.2.5.1: Bit – Mapped Scheme:

A video memory is used to store the data to be display on the

screen. Each pixel of the screen is mapped directly to a memory word and the pixel_x

and Pixel_y signals from the address. A graphics processing circuit continuously updates

the screen and writes relevant data to the video memory. A retrieval circuit continuously

reads the video memory and routes the data to the data to the RGB signal. This is the

scheme used in today’s high – performance video controller. For 640 – by – 480

resolution, there are about 310K (i. e. , 640 * 480) pixels on a screen. This translates to

310 K memory bits for a monochrome display and 930 K memory bits (i. e. , 3 – bits per

pixel) for a 3 – bit color display.

3.2.5.2: Tile – Mapped Scheme: It is used as a alternative to reduce the memory

requirement. We group a collection of bits to form a tile and each treat each tile as a

display unit. We can define an 8 by 8 square of pixels as a title. The 640 by 480 pixel –

oriented screen becomes an 80 by 60 till – oriented screen. Only 4800 words are need for

the title memory. The number of bits in a word depends on the number of tile patterns. If

there are 32 tile patterns, each word should contain 5 bits and the size of the tile memory

is about 24 K bits. The till-mapped scheme usually requires a ROM to store the tile

patterns it is called as pattern memory. Each 8 by 8 tile pattern requires 64 bits and the

entire 32 patterns need 2K bits. The overall memory requirement is about 26K bits, which

is much smaller than the 310 K bits of the bit – mapped scheme.

3.2.5.3: Object – Mapped Scheme: The video display can be very simple and

contains only a few objects. Instead of wasting memory to store a mostly blank screen we

can generate these objects using simple object generation circuit. Which is called as

object – mapped scheme. The three schemes can be mixed together to generate a full

screen. Bit – mapped scheme to generate the background. Object – mapped schemed

scheme to produce the main objects. We can also use a bit – mapped scheme for one

portion of a screen and tile mapped text for another part of the screen.



3.2.5.4: Graphic Generation With An Object – Mapped Scheme:

An object generation circuit

performs the following tasks:

a) It keep the coordinates of the current object and compares them with the current

scan location provided by the pixel_x and Pixel_y signal.

b) If the current scan location falls with the region, it asserts the obj-i-on signal to

indicate that the current scan location is within the region of the ith object and the

object should be “turned on”.

c) It specifies the desired color in the obj-i-rgb signal.

The rgb mux circuit performs multiplexing according to an internal prioritize scheme. It

examines various obj-i-on signal and determines which object obj-1-rgb signal is to be

routed to the rgb output. The prioritizing scheme prioritizes the order of the displays

when multiple obj-i-on signal are asserted at the same time. It corres - propounds to

selecting an object for the foreground.

3.2.5.5: FSM Of video ON/OFF Signal:



3.2.5.5: FSM of Object Generation Circuit:

3.2.5.6: FSM Of object color Generation circuit:



3.2.5.6: FSM Of full wall on screen:



3.3: Conclusion and scope for future work.

In this project we had design of

UART in VHDL language and VGA in verilog language and simulation done in Xilinx

ISE Design Suite 12.2 and then we got the proper simulated behavioral result and RTL

schematic view and then implemented design and generated programming file which is

diffused in side the Spartan 3 FPGA board. Tested the UART VHDL code and VGA

Verilog code by using terminal. During this project we got know about UART and VGA

functionality.

3.4: Bibliography:

1. Hand book of FPGA Prototyping by VHDL Examples, by Pong P. chu.

2. Hand book of VHDL Programming by Example (Fourth edition), by Dougles L. Perry.

3. PPT of VHDL by Avent Spees Way Design Workshop.

4. www.applied VHDL.com

5. ISE Quick start tutorial www.xilinx.com.



3.5: Appendices

3.5.1: VHDL CODE OF UART:

3.5.1.1: Top Module:

---------------------------------------------------------------------------- ------ -- Company: -- Engineer: -- -- Create Date: 14:14:55 11/21/2011 -- Design Name: -- Module Name: topcode - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------- ------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity topcode is Port ( Rx : in STD_LOGIC; Tx : out STD_LOGIC; clk : in STD_LOGIC; LED_OUT : out STD_LOGIC_VECTOR (7 downto 0)); end topcode; architecture Behavioral of topcode is signal D,din : std_logic_vector(7 downto 0) := (others => '0'); signal xr,xt,z,T : std_logic := '0'; component Rxbaud is Port ( clk : in STD_LOGIC; baud : out STD_LOGIC); end component;



component Rxcode is Port ( Rx : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0); baud_clk : in STD_LOGIC ; byte_done : out std_logic); end component; component Txbaud is Port ( baud_clk : in STD_LOGIC; baud : out STD_LOGIC); end component;

component Txcodefull is Port ( data_in_enable : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (7 downto 0); Tx : out STD_LOGIC; baud_clk : in STD_LOGIC); end component; component loopcode is Port ( Tx_baud_clk : in STD_LOGIC; Rx_baud_clk : in std_logic; data_in : in STD_LOGIC_VECTOR (7 downto 0); data_out : out STD_LOGIC_vector(7 downto 0); data_in_enable : in STD_LOGIC; data_out_enable : out STD_LOGIC); end component; begin Rx_baud_program : Rxbaud Port map( clk => clk, baud => xr); Rx_program : Rxcode port map(Rx => Rx, data_out => D, baud_clk => xr, byte_done => z); Tx_baud_program : Txbaud port map(baud_clk => xr, baud => xt); Tx_program : Txcodefull port map(data_in_enable => T, data_in => din, Tx => Tx, baud_clk => xt); Loopprogram : loopcode port map(Tx_baud_clk => xt, Rx_baud_clk => xr, data_in => D, data_out => din, data_in_enable => z, data_out_enable => T ); LED_OUT <= din; end Behavioral;

3.5.1.2: Receiver baud generator code

----------------------------------------------------------------------------



------ -- Company: -- Engineer: -- -- Create Date: 03:29:41 11/18/2011 -- Design Name: -- Module Name: RXbaud - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------- ------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity RXbaud is Port ( clk : in STD_LOGIC; baud : out STD_LOGIC); end RXbaud; architecture Behavioral of RXbaud is type shukla1 is(s0,s1,s2); signal Nx_state,Pr_state : shukla1; signal count :integer range 0 to 163 := 0; begin process(Pr_state,count) begin case Pr_state is when s0 => if((count >= 0) and (count <= 81))then Nx_state <= s0; else Nx_state <= s1; end if; when s1 => if((count >81) and (count < 163))then Nx_state <= s1; else Nx_state <= s0;

end if; when others => Nx_state <= s0; end case;



end process; process(clk) begin if(clk' event and clk ='1')then Pr_state <= Nx_state; case Nx_state is when s0 => baud <= '1'; when s1 => baud <= '0'; when others => baud <= '1'; end case; end if; end process; process(clk,count) begin if(clk' event and clk = '1')then count <= count + 1; else count <= count; end if; if(count = 163 )then count <= 0; end if; end process; end Behavioral;



3.5.1.3: Receiver code:

---------------------------------------------------------------------------- ------ -- Company: -- Engineer: -- -- Create Date: 22:49:58 11/17/2011 -- Design Name: -- Module Name: Rxcode - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------- ------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Rxcode is Port ( Rx : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0); baud_clk : in STD_LOGIC ; byte_done : out std_logic); end Rxcode; architecture Behavioral of Rxcode is type shukla is(s0,s1,s2,s3,s4,s5); signal Pr_state, Nx_state : shukla; signal count1, count2,count3 : integer range 0 to 15 := 0; signal num : integer range 0 to 8 := 0; signal byte_done1 : std_logic := '0'; signal data : std_logic_vector (7 downto 0) := (others => '0'); begin process(Pr_state,Rx,count1,count2,count3,num,byte_done1) begin case Pr_state is when s0 =>

if(Rx = '0')then Nx_state <= s1;

else



Nx_state <= s0; end if;

when s1 => if(count1 = 7 )then

Nx_state <= s2; else


when s2 => if(count2 = 15)then



when s3 => if(num = 8)then



when s4 => if(count3 = 15 ) then



when s5 => if(byte_done1 = '1')then



when others => Nx_state <= s0;

end case; end process; process (baud_clk) begin if(baud_clk' event and baud_clk = '1')then

Pr_state <= Nx_state; case Nx_state is when s0 =>

count1 <= 0; byte_done1 <= '0';

byte_done <= '0'; -- Rx_done <= '0';

when s1 => count1 <= count1 + 1; count2 <= 0;

when s2 => count2 <= count2 + 1;

when s3 => data(num) <= Rx; num <= num + 1; count2 <= 0; count3 <= 0;

when s4 =>



num <= 0; count3 <= count3 + 1;

when s5 => byte_done1 <= '1'; byte_done <= '1'; data_out <= data;

when others => byte_done <= '0';

end case; end if; end process; end Behavioral;

3.5.1.4: Transmitter baud generator code:

---------------------------------------------------------------------------- ------ -- Company: -- Engineer: -- -- Create Date: 03:21:38 11/18/2011 -- Design Name: -- Module Name: Txbaud - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------- ------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Txbaud is Port ( baud_clk : in STD_LOGIC; baud : out STD_LOGIC); end Txbaud; architecture Behavioral of Txbaud is type shukla is(s0,s1,s2,s3); signal Nx_state,Pr_state : shukla; signal count : integer range 0 to 16 := 0; begin



process(Pr_state,count) begin case Pr_state is when s0 =>

if((count >= 0) and (count <= 7))then Nx_state <= s0;

else Nx_state <= s1;

end if; when s1 =>

if((count >= 7)and (count <= 15))then Nx_state <= s1;

else Nx_state <= s0;

end if; when others =>

Nx_state <= s0; end case; end process; process(baud_clk) begin

if(baud_clk' event and baud_clk ='1')then Pr_state <= Nx_state; case Nx_state is when s0 =>

baud <= '1'; when s1 =>

baud <= '0'; when others =>

baud <= '1'; end case;

end if; end process; process(baud_clk,count) begin

if(baud_clk' event and baud_clk = '1')then count <= count + 1;

else count <= count;

end if; if(count = 16 )then

count <= 0; end if;

end process; end Behavioral;



3.5.1.5: Transmitter code

---------------------------------------------------------------------------- ------ -- Company: -- Engineer: -- -- Create Date: 03:36:36 11/18/2011 -- Design Name: -- Module Name: Txcodefull - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------- ------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Txcodefull is Port ( data_in_enable : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (7 downto 0); Tx : out STD_LOGIC; baud_clk : in STD_LOGIC); end Txcodefull; architecture Behavioral of Txcodefull is type shukla is(s0,s1,s2,s3,s4,s5,s6); signal Nx_state,Pr_state : shukla; signal count : integer range 0 to 8 := 0; signal flage : std_logic := '0'; signal data : std_logic_vector (7 downto 0) := (others => '0'); begin process(Pr_state,data_in_enable,count,data_in) begin case Pr_state is

when s0 => if(data_in_enable = '1')then

data <= data_in; Tx <= '0'; Nx_state <= s2;

else Tx <= '1';




when s2 => if(count = 8)then

Tx <= '1'; flage <= '0'; Nx_state <= s0;

else flage <= '1'; Tx <= data(count); Nx_state <= s2;

end if; when others =>

Nx_state <= s0; Tx <= '1'; flage <= '0';

end case; end process; process(baud_clk) begin

if(baud_clk' event and baud_clk = '1')then Pr_state <= Nx_state;

end if; end process; process(baud_clk,flage) begin

if(baud_clk' event and baud_clk = '1')then if(flage = '1')then

count <= count + 1; end if; if(flage = '0')then

count <= 0; end if;

end if; end process; end Behavioral;



3.5.1.6: Asynchronous FIFO code

---------------------------------------------------------------------------- ------ -- Company: -- Engineer: -- -- Create Date: 10:23:34 11/18/2011 -- Design Name: -- Module Name: loopcode - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------- ------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity loopcode is Port ( Tx_baud_clk : in STD_LOGIC; Rx_baud_clk : in std_logic; data_in : in STD_LOGIC_VECTOR (7 downto 0); data_out : out STD_LOGIC_vector(7 downto 0); data_in_enable : in STD_LOGIC; data_out_enable : out STD_LOGIC); end loopcode; architecture Behavioral of loopcode is type shukla is(s0,s1,s2,s3,s4); signal Rx_Nx_state,Rx_Pr_state : shukla; type shukla1 is(p0,p1,p2,p3,p4); signal Tx_Nx_state,Tx_Pr_state : shukla1; type saurabh is array(0 to 7) of std_logic_vector(7 downto 0); signal memory : saurabh; signal wr_addr,rd_addr : std_logic_vector(2 downto 0) := (others => '0'); signal count : integer range 0 to 8 := 0; signal wr_done,rd_done,flage,flagecount : std_logic := '0'; begin process(Rx_Pr_state,data_in_enable,wr_done) begin

case Rx_Pr_state is when s0 =>



if(data_in_enable = '1')then

Rx_Nx_state <= s1; else

Rx_Nx_state <= s0; end if;

when s1 => if(wr_done = '1')then

Rx_Nx_state <= s0; else

Rx_Nx_state <= s1; end if;

when others => Rx_Nx_state <= s0;

end case; end process; process(Rx_baud_clk) begin

if(Rx_baud_clk' event and Rx_baud_clk = '1')then Rx_Pr_state <= Rx_Nx_state; case Rx_Nx_state is when s0 =>

wr_done <= '0'; when s1 =>

memory(conv_integer(wr_addr)) <= data_in; wr_addr <= wr_addr + '1'; wr_done <= '1'; flage <= '1';

when others => wr_done <= '0'; flage <= '0';

end case; end if;

end process; process(Tx_Pr_state,flage,rd_done,count) begin case Tx_Pr_state is when p0 =>

if(flage = '1')then Tx_Nx_state <= p1;

else Tx_Nx_state <= p0;

end if; when p1 =>

if(rd_done = '1')then Tx_Nx_state <= p2;

else Tx_Nx_state <= p1;

end if;

when p2 => if(count = 8)then

Tx_Nx_state <= p0; else

Tx_Nx_state <= p2; end if;

when others => Tx_Nx_state <= p0;



end case; end process; process(Tx_baud_clk) begin if(Tx_baud_clk' event and Tx_baud_clk = '1')then

Tx_Pr_state <= Tx_Nx_state; case Tx_Nx_state is when p0 =>

rd_done <= '0'; flagecount <= '0';

when p1 => if(rd_addr(2 downto 0) /= wr_addr(2downto 0))then

data_out <= memory(conv_integer(rd_addr)); rd_addr <= rd_addr + '1'; rd_done <= '1'; data_out_enable <= '1'; flagecount <= '1';

end if; when p2 =>

rd_done <= '0'; data_out_enable <= '0';

when others => rd_done <= '0'; flagecount <= '0';

end case; end if; end process; process(Tx_baud_clk,flagecount,count) begin

if(flagecount = '1')then if(Tx_baud_clk' event and Tx_baud_clk = '1')then

count <= count + 1; if(count = 8)then

count <= 0; end if;

end if; end if;

end process; end Behavioral;



3.5.2: Verilog CODE OF VGA:

3.5.2.1: TOP VGA Code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 17:29:56 01/09/2012 // Design Name: // Module Name: TOP_VGA_Code // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module TOP_VGA_Code(Rst,clk,RGB,H_synch,V_synch,Pixel_y); output V_synch; output H_synch; output [2:0]RGB; input Rst; input clk; output [9:0]Pixel_y; wire a; wire [9:0]x; wire VO; wire o1,o2,o3,o4,o5,o6,o7,o8; VGA_system_CLK_module U1(.Rst(Rst),.clk_in(clk),.clk_out(a)); MAIN_TOP_VGA_Synch U2(.Rst(Rst),.clk(a),.Pixel_x(x),.Pixel_y(Pixel_y),. video_on(VO),.H_synch(H_synch),.V_synch(V_synch)); //Object_Generation_code U3(.Rst(Rst),.clk(a),.Pixel_x(x),.Pixel_y(y),.video_on(VO),.object1(o1),.obje ct2(o2),.object3(o3)); //MUX_RGB_CODE U4(.Rst(Rst),.clk(a),.obj1(o1),.obj2(o2),.obj3(o3),.RGB(RGB)); //wall_object_module W1(.Rst(Rst),.clk(clk),.obj1(o1),.obj2(o2),.obj3(o3),.obj4(o4),.obj5(o5),.obj 6(o6),.obj7(o7),.obj8(o8),.video_on(VO),.Pixel_x(x)); WALL_MUX_Module W2(.Rst(Rst),.clk(clk),.RGB(RGB),.obj1(o1),.obj2(o2),.obj3( o3),.obj4(o4),.obj5(o5),.obj6(o6),.obj7(o7),.obj8(o8)); Anim_VGA_Pixel_module AN1(.Rst(Rst),.clk(clk),.obj1(o1),.obj2(o2),.obj3(o3 ),.obj4(o4),.obj5(o5),.obj6(o6),.obj7(o7),.obj8(o8),.video_on(VO),.Pixel_x(x )); Endmodule



3.5.2.2: Vertical System Clock:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 11:11:35 01/09/2012 // Design Name: // Module Name: VGA_system_CLK_module // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module VGA_system_CLK_module(Rst,clk_in,clk_out); parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; output clk_out; input clk_in; input Rst; reg clk_out; reg [1:0] Pr_state; reg [1:0] Nx_state; integer count; always@(Pr_state or count) begin

Nx_state = S0; case(Pr_state) S0: begin

if((count >= 0) && (count < 1)) begin

Nx_state = S0; end else begin

Nx_state = S1; end

end

S1: begin


Nx_state = S1;



end else begin

Nx_state = S0; end

end default:

begin Nx_state = S0;

end endcase end

always@(posedge clk_in or posedge Rst) begin

if(Rst) begin

count = 0; Pr_state = S0;

end else begin

Pr_state = Nx_state; case(Nx_state) S0: begin


clk_out = 1; count = count + 1;

end end S1: begin



end if(count > 1) begin

count = 0; end

end

default: begin

count = 0; end

endcase end end

endmodule



3.5.2.3: VGA Vertical Synch Clock:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 10:31:23 01/10/2012 // Design Name: // Module Name: VGA_V_synch_clk // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module VGA_V_synch_clk(Rst,clk_in,clk_out); parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; output clk_out; input clk_in; input Rst; reg clk_out; reg [1:0]Nx_state; reg [1:0]Pr_state; integer count; always@(Pr_state or count) begin


if((count >= 0) && (count <= 399)) begin


Nx_state = S1; end

end S1: begin

if((count >= 400) && (count <= 799))




end else begin

Nx_state = S0; end

end default: begin

Nx_state = S0; end

endcase end always@(posedge clk_in or posedge Rst) begin

if(Rst) begin

clk_out = 0; count = 0; Pr_state = S0;

end else begin




end end S1: begin




count = 0;

end end default:

begin count = 0;

end endcase end end endmodule



3.5.2.4: TOP VGA Synch Code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 12:58:55 01/09/2012 // Design Name: // Module Name: TOP_VGA_Synch_code // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module TOP_VGA_Synch_code(Rst,clk,video_on,H_video,V_video); parameter S0 = 2'b00; parameter S1 = 2'b01; output video_on; input Rst; input clk; input H_video; input V_video; reg video_on; reg [1:0] Nx_state; reg [1:0] Pr_state; always@(Pr_state or H_video or V_video) begin


if((H_video) && (V_video)) begin


Nx_state = S1; end

end

S1: begin

if((H_video == 0) || (V_video == 0)) begin

Nx_state = S1; end



else begin

Nx_state = S0; end

end default:


end endcase end always@(posedge clk or posedge Rst) begin

if(Rst) begin

video_on = 0; Pr_state = S0;

end else begin


video_on = 1; end S1: begin

video_on = 0; end default: begin

video_on = 0; end endcase

end end endmodule



3.5.2.5: Horizontal Synch code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 11:51:33 01/09/2012 // Design Name: // Module Name: Horizontal_synch_code // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module Horizontal_synch_code(Rst,clk,H_video_on,H_synch,Pixel_x); parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; output H_video_on; output H_synch; output [9:0]Pixel_x; input Rst; input clk; reg H_video_on; reg H_synch; reg [9:0]Pixel_x; reg [1:0] Nx_state; reg [1:0] Pr_state; integer count; always@(Pr_state or count) begin



Nx_state = S0; end

else begin

Nx_state = S1; end

end S1:



begin if((count >= 640) && (count <= 655)) begin


Nx_state = S2; end

end S2: begin



Nx_state = S3; end

end S3: begin



Nx_state = S0; end

end default: begin

Nx_state = S0; end

endcase end always@(posedge clk or posedge Rst) begin

if(Rst) begin

count = 0;

Pr_state = S0; end else begin

Pr_state = Nx_state; case(Nx_state) S0: begin if((count >= 0) && (count <= 639)) begin

H_video_on = 1; H_synch = 1; Pixel_x = count;



count = count + 1; end

end S1: begin


H_video_on = 0; H_synch = 1; Pixel_x = count; count = count + 1;

end end S2: begin



end end S3: begin




count = 0; end

end

default: begin

count = 0; end endcase end end endmodule



3.5.2.6: Vertical Synch code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 12:27:30 01/09/2012 // Design Name: // Module Name: Vertical_synch_code // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module Vertical_synch_code(Rst,clk,V_video_on,V_synch,Pixel_y); parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; output V_video_on; output V_synch; output [9:0]Pixel_y; input Rst; input clk; reg V_video_on; reg V_synch; reg [9:0] Pixel_y; reg [1:0] Nx_state; reg [1:0] Pr_state; integer count; always@(Pr_state or count) begin



Nx_state = S0; end

else begin

Nx_state =S1; end

end S1:



begin if((count >= 480) && (count <= 489)) begin

Nx_state = S1; end

else begin

Nx_state = S2; end

end S2: begin


Nx_state = S2; end

else begin

Nx_state = S3; end

end S3: begin



Nx_state = S0; end

end default: begin

Nx_state = S0; end endcase end always@(posedge clk or posedge Rst) begin if(Rst) begin

count = 0;




V_video_on = 1; V_synch = 1; Pixel_y = count;



count = count + 1; end

end S1: begin


V_video_on = 0; V_synch = 1; Pixel_y = count; count = count + 1;

end end S2: begin



end end S3: begin




count = 0; end

end default: begin

count = 0; end endcase end end endmodule



3.5.2.7: MUX RGB Code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 17:08:29 01/09/2012 // Design Name: // Module Name: MUX_RGB_CODE // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module MUX_RGB_CODE(Rst,clk,obj1,obj2,obj3,RGB); parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; output [2:0]RGB; input Rst; input clk; input obj1; input obj2; input obj3; reg [2:0]RGB; reg [1:0]Nx_state; reg [1:0]Pr_state; always@(Pr_state or obj1 or obj2 or obj3) begin


if(obj1) begin

Nx_state = S0; end

else begin

Nx_state = S1;

end end S1: begin

if(obj2) begin




Nx_state = S2; end

end S2: begin

if(obj3) begin


Nx_state = S0; end

end default: begin

Nx_state = S0; end endcase end always@(posedge clk or posedge Rst) begin if(Rst) begin



if(obj1) begin

RGB = 3'b001; end else begin

RGB = 3'b000;

end end S1: begin

if(obj2) begin


RGB = 3'b000; end

end S2:



begin if(obj3) begin


RGB = 3'b000; end

end default: begin

RGB = 3'b000; end endcase end end endmodule

3.5.2.8: Object Generation Code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 14:14:14 01/09/2012 // Design Name: // Module Name: Object_Generation_code // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module Object_Generation_code(Rst,clk,Pixel_x,Pixel_y,video_on,object1, object2,object3); parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; output object1; output object2; output object3; input video_on; input Rst; input clk;



input [9:0]Pixel_x; input [9:0]Pixel_y; reg object1; reg object2; reg object3; reg [1:0]Nx_state; reg [1:0]Pr_state; always@(Pr_state or Pixel_x or Pixel_y or video_on) begin

Nx_state = S0; object1 = 1; object2 = 0; object3 = 0;

case(Pr_state)

S0: begin

if((Pixel_x >= 32) && (Pixel_x <= 35) && (video_on)) begin

object1 = 1; object2 = 0; object3 = 0; Nx_state = S0;

end else begin


end end S1: begin

if((Pixel_x >= 200) && (Pixel_x <= 205) && (Pixel_y >= 104) && (Pixel_y <= 175) && (video_on)) begin


end else begin


end end S2: begin

if((Pixel_x >= 300) && (Pixel_x <= 350) && (Pixel_y >= 190) && (Pixel_y <= 210) && (video_on)) begin

object1 = 0; object2 = 0; object3 = 1;





end

end default: begin


end endcase end always@(posedge clk or posedge Rst) begin if(Rst) begin


Pr_state = Nx_state; end end endmodule



3.5.2.9: Wall MUX code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 16:00:29 01/10/2012 // Design Name: // Module Name: WALL_MUX_Module // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module WALL_MUX_Module(Rst,clk,RGB,obj1,obj2,obj3,obj4,obj5,obj6,obj7,obj8); parameter S0 = 4'b0000; parameter S1 = 4'b0001; parameter S2 = 4'b0010; parameter S3 = 4'b0011; parameter S4 = 4'b0100; parameter S5 = 4'b0101; parameter S6 = 4'b0110; parameter S7 = 4'b0111; input obj1,obj2,obj3,obj4,obj5,obj6,obj7,obj8; input Rst; input clk; output [2:0]RGB; reg [2:0]RGB; reg [3:0] Nx_state; reg [3:0] Pr_state; always@(Pr_state or obj1 or obj2 or obj3 or obj4 or obj5 or obj6 or obj7 or obj8) begin


if(obj1) begin

RGB = 3'b001; Nx_state = S0;

end else begin


end



end S1: begin

if(obj2) begin


end else begin


end end S2: begin

if(obj3) begin


end else begin


end end S3: begin

if(obj4) begin


end else begin


end end S4: begin

if(obj5) begin

RGB = 3'b101;



end end S5: begin

if(obj6) begin




end else begin


end end S6: begin

if(obj7) begin


end else begin


end end S7: begin

if(obj8) begin


end else begin


end end default: begin


end endcase end always@(posedge clk or posedge Rst) begin

if(Rst) begin


Pr_state = Nx_state; end

end endmodule



3.5.2.10: Wall Object code:

`timescale 1ns / 1ps ///////////////////////////////////////////////////////////////////////////// ///// // Company: // Engineer: // // Create Date: 15:10:53 01/10/2012 // Design Name: // Module Name: wall_object_module // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ///////////////////////////////////////////////////////////////////////////// ///// module wall_object_module(Rst,clk,obj1,obj2,obj3,obj4,obj5,obj6,obj7,obj8, video_on,Pixel_x); parameter S0 = 4'b0000; parameter S1 = 4'b0001; parameter S2 = 4'b0010; parameter S3 = 4'b0011; parameter S4 = 4'b0100; parameter S5 = 4'b0101; parameter S6 = 4'b0110; parameter S7 = 4'b0111; output obj1,obj2,obj3,obj4,obj5,obj6,obj7,obj8; input Rst; input clk; input video_on; input [9:0]Pixel_x; reg obj1,obj2,obj3,obj4,obj5,obj6,obj7,obj8; reg [3:0] Nx_state; reg [3:0] Pr_state; always@(Pr_state or video_on or Pixel_x) begin



obj1 = 1; obj2 = 0; obj3 = 0; obj4 = 0; obj5 = 0; obj6 = 0; obj7 = 0;



obj8 = 0; Nx_state = S0;

end else begin

obj1 = 0; obj2 = 0; obj3 = 0; obj4 = 0; obj5 = 0; obj6 = 0; obj7 = 0; obj8 = 0; Nx_state = S1;

end end S1: begin



end else begin


end end S2: begin



end else



begin obj1 = 0; obj2 = 0; obj3 = 0; obj4 = 0; obj5 = 0; obj6 = 0; obj7 = 0; obj8 = 0; Nx_state = S3;

end end S3: begin



end else begin


end end

S4: begin



end else begin

obj1 = 0; obj2 = 0;



obj3 = 0; obj4 = 0; obj5 = 0; obj6 = 0; obj7 = 0; obj8 = 0; Nx_state = S5;

end end S5: begin



end else begin


end end S6: begin



end else begin

obj1 = 0; obj2 = 0; obj3 = 0; obj4 = 0; obj5 = 0;



obj6 = 0; obj7 = 0; obj8 = 0; Nx_state = S7;

end end S7: begin



end else begin

obj1 = 0; obj2 = 0; obj3 = 0; obj4 = 0; obj5 = 0; obj6 = 0;

obj7 = 0; obj8 = 0; Nx_state = S0;

end end default: begin

obj1 = 0; obj2 = 0; obj3 = 0; obj4 = 0; obj5 = 0; obj6 = 0; obj7 = 0; obj8 = 0;

end endcase end always@(posedge clk or posedge Rst) begin if(Rst) begin


Pr_state = Nx_state; end end



3.6: RESULT

3.6.1: RTL Schematic View

3.6.1.1: TOP module Schematic View



3.6.1.2: Receiver baud generator Schematic View



3.6.1.3: Receiver Schematic View



3.6.1.4: Transmitter baud generator Schematic View



3.6.1.5: Transmitter Schematic View



3.6.1.6: Asynchronous FIFO Schematic View



3.6.2: Simulated behavioral result

3.6.2.1: TOP module Simulated behavioral result

3.6.2.2: Receiver baud generator Simulated behavioral result



3.6.2.3: Receiver Simulated behavioral result

3.6.2.4: Transmitter baud generator Simulated behavioral result



3.6.2.5: Transmitter Simulated behavioral result

3.6.2.6: Asynchronous FIFO Simulated behavioral result



3.6.3: Result of VGA

3.6.3.1: Result of Pong Game:



3.6.3.2: Result of WALL object:



3.7: ACRONYMS:

1: CLK = CLOCK

2: baud = mode count

3: Tx = Transmitter

4: Rx = Receiver

5: LED_OUT = FPGA LED

6: baud_clk = mode count CLOCK

7: Tx_baud_clk = Transmitter mode count CLOCK(Transmitter baud CLOCK)

8: Rx_baud_clk = Receiver mode count CLOCK(Receiver baud CLOCK)

9: rd_addrs = read address used in FIFO memory

10: wr_addrs = write address used in FIFO memory

uart(vhdl) && vga(verilog)

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