uart (verilog code) with fsm
DESCRIPTION
All Task in UART with FSMTRANSCRIPT
1. Objective of work
A: Core Objective Study, Design and Testing Of Universal Asynchronous Receiver /
Transmitter using language Verilog.
B: Specific Objective
UART receiver / Transmitter have 8 data bits, one stop bits with one start bit. Baud
generator has its baud rate divisor . Interface circuit (FIFO). Tested in Spartan – 3 starter kit
board (FPGA).
2. Functional Partitioning Of project
Task I : Design of Baud rate generator for Receiver.
Task II : Design of UART Receiver sub system.
Task III : Design of Baud rate generator for transmitter.
Task IV : Design of Transmitter sub system.
Task IV : Design of asynchronous FIFO Interface circuit.
3: Functional Task completed of Project
Task I : Design of Baud rate generator for Receiver.
Task II : Design of UART Receiver sub system.
Both task I and Task II completed successfully and Tested in Spartan – 3
starter kit board (FPGA).
Task III : Design of Baud rate generator for transmitter.
Task completed successfully but have to test in Sparten- 3 starter
kit board(FPGA).
Task IV and Task V:
Both Task in process.
4: FSM of Baud Rate generator of receiver:
5: FSM of UART Receiver:
6: Appendices
6.1: Verilog code for Top Module of receiver:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:33:31 12/07/2011
// Design Name:
// Module Name: Rx_TOP_code
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Rx_TOP_code(Rst,clk,Rx,Rx_data_out,Rx_data_out_done);
output [7:0]Rx_data_out;
output Rx_data_out_done;
input clk;
input Rx;
input Rst;
wire a;
new_Rx_baud U1(.Rst(Rst),.clk(clk),.Rx_baud(a));
new_Rx
U2(.Rst(Rst),.Rx_baud(a),.Rx_data_out(Rx_data_out),.Rx_data_out_done(Rx_data_out_done),.Rx(Rx))
;
endmodule
6.2: Verilog code of Baud rate Generator of Receiver
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:27:11 12/07/2011
// Design Name:
// Module Name: new_Rx_baud
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module new_Rx_baud(clk,Rst,Rx_baud);
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
output Rx_baud;
input Rst;
input clk;
reg Rx_baud;
reg [1:0]Pr_state;
reg [1:0]Nx_state;
integer count;
always@(Rst or count or Pr_state)
begin
case(Pr_state)
S0:
begin
if(Rst)
begin
Nx_state = S0;
end
else
begin
Nx_state = S1;
end
end
S1:
begin
if((count >= 0) && (count <= 81))
begin
Nx_state = S1;
end
else
begin
Nx_state = S2;
end
end
S2:
begin
if((count > 81) && (count < 163))
begin
Nx_state = S2;
end
else
begin
Nx_state = S0;
end
end
default:
begin
Nx_state = S0;
end
endcase
end
always@(posedge clk or posedge Rst)
begin
if(Rst)
begin
count = 0;
Pr_state = S0;
end
else
begin
Pr_state = Nx_state;
case(Nx_state)
S0:
begin
count = 0;
end
S1:
begin
Rx_baud = 1;
count = count + 1;
end
S2:
begin
Rx_baud = 0;
count = count + 1;
end
default:
begin
count = 0;
Rx_baud = 1;
end
endcase
end
end
endmodule
6.3: Verilog code of UART Receiver:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:22:43 12/07/2011
// Design Name:
// Module Name: new_Rx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module new_Rx(Rx_baud,Rst,Rx_data_out,Rx_data_out_done,Rx);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b110;
parameter S7 = 3'b111;
output [7:0]Rx_data_out;
output Rx_data_out_done;
input Rx_baud;
input Rst;
input Rx;
reg [2:0]Pr_state;
reg [2:0]Nx_state;
reg [7:0]Rx_data_out;
reg Rx_data_out_done;
reg [4:0] count2,count3;
reg [3:0] count1,bit_num;
reg data_done;
reg [7:0]data;
always@(Pr_state or Rst or count1 or count2 or count3 or data_done or bit_num or Rx)
begin
case(Pr_state)
S0:
begin
if(Rst)
begin
Nx_state = S0;
end
else
begin
Nx_state = S1;
end
end
S1:
begin
if(Rx)
begin
Nx_state = S1;
end
else
begin
Nx_state = S2;
end
end
S2:
begin
if((count1 >= 0 ) && (count1 < 7))
begin
Nx_state = S2;
end
else
begin
Nx_state = S3;
end
end
S3:
begin
if((count2 >=0) &&(count2 < 15))
begin
Nx_state = S3;
end
else
begin
Nx_state = S4;
end
end
S4:
begin
if((bit_num >= 0) &&(bit_num <= 7))
begin
Nx_state = S3;
end
else
begin
Nx_state = S5;
end
end
S5:
begin
if((count3 >= 0) &&(count3 < 15))
begin
Nx_state = S5;
end
else
begin
Nx_state = S6;
end
end
S6:
begin
if(data_done)
begin
Nx_state = S0;
end
else
begin
Nx_state = S6;
end
end
default:
begin
Nx_state = S0;
end
endcase
end
always@(posedge Rx_baud or posedge Rst)
begin
if(Rst)
begin
count1 = 0;
count2 = 0;
count3 = 0;
bit_num = 0;
data_done = 0;
Pr_state = S0;
end
else
begin
Pr_state = Nx_state;
case(Nx_state)
S0:
begin
count1 = 0;
count2 = 0;
count3 = 0;
bit_num = 0;
data_done = 0;
data_done = 0;
Rx_data_out_done = 0;
end
S1:
begin
count1 = 0;
end
S2:
begin
count1 = count1 + 1;
end
S3:
begin
count2 = count2 + 1;
end
S4:
begin
data[bit_num] = Rx;
bit_num = bit_num + 1;
count2 = 0;
end
S5:
begin
count3 = count3 + 1;
end
S6:
begin
data_done = 1;
Rx_data_out = data;
Rx_data_out_done = 1;
end
default:
begin
data_done = 0;
count1 = 0;
count2 = 0;
count3 = 0;
bit_num = 0;
end
endcase
end
end
endmodule
7: Result:
7:1. RTL Schematic View of receiver Top module:
7.2: RTL Schematic View of receiver Baud Rate Generator
module
7.3: RTL Schematic View of receiver module
8: Simulated Behavioral Result:
8:1. Simulated Behavioral Result of Top module of Receiver:
8:2. Simulated Behavioral Result of Baud rate generator of
Receiver:
8:2. Simulated Behavioral Result of UART Receiver:
