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  • 7/28/2019 L17_FSM Design Example With Verilog

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    Logic Design :Verilog FSM in class design example s 1 S. Yoder ND, 2010

    CSE 20221: Logic Design

    Verilog FSM Design Example

    Automatic Garage Door Opener

    &

    Timers

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    Logic Design :Verilog FSM in class design example s 2 S. Yoder ND, 2010

    Inputs / Outputs

    Define the module interface

    NAME TYPE FUNCTION

    activate (A) input starts the door to go up or down or stops the motion

    Up_limit (UPL) input indicates maximum upward travel

    Dn_limit (DNL) input indicates maximum downward travel

    Motor_up (MU) output Causes motor to run in direction to raise the door

    Motor_dn (MD) output Causes motor to run in direction to lower door

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    Logic Design :Verilog FSM in class design example s 3 S. Yoder ND, 2010

    Inputs / Outputs

    NAME TYPE FUNCTION

    activate (A) input starts the door to go up or down or stops the motion

    Up_limit (UPL) input indicates maximum upward travel

    Dn_limit (DNL) input indicates maximum downward travel

    Motor_up (MU) output Causes motor to run in direction to raise the door

    Motor_dn (MD) output Causes motor to run in direction to lower doorreset input Force the controller to enter into the initial state

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    Logic Design :Verilog FSM in class design example s 4 S. Yoder ND, 2010

    State Diagram

    initial

    upnext

    dnnext

    movingup

    movingdown

    A

    UPL

    A

    DNL

    A

    MU MD

    UPLUPL

    AA

    A DNL

    A DNL

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    Logic Design :Verilog FSM in class design example s 5 S. Yoder ND, 2010

    Make the State Assignments

    initial

    upnext

    dnnext

    movingup

    movingdown

    A

    UPL

    A

    DNL

    AMU MD

    UPLUPLA A

    ADNL

    A

    DNL

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    Logic Design :Verilog FSM in class design example s 6 S. Yoder ND, 2010

    Setup clear and state register

    initial

    upnext

    dnnext

    moving

    up

    moving

    down

    A

    UPL

    A

    DNL

    AMU MD

    UPL

    UP

    L

    A A

    ADNL

    ADNL

  • 7/28/2019 L17_FSM Design Example With Verilog

    7/23Logic Design :Verilog FSM in class design example s 7 S. Yoder ND, 2010

    Describe the Behavior

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    8/23Logic Design :Verilog FSM in class design example s 8 S. Yoder ND, 2010

    Behavior Continued

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    9/23Logic Design :Verilog FSM in class design example s 9 S. Yoder ND, 2010

    Xilinx Verilog Test Fixture

    1

  • 7/28/2019 L17_FSM Design Example With Verilog

    10/23Logic Design :Verilog FSM in class design example s 10 S. Yoder ND, 2010

    Test Bench for Clock

  • 7/28/2019 L17_FSM Design Example With Verilog

    11/23Logic Design :Verilog FSM in class design example s 11 S. Yoder ND, 2010

    Simulation Results

  • 7/28/2019 L17_FSM Design Example With Verilog

    12/23Logic Design :Verilog FSM in class design example s 12 S. Yoder ND, 2010

    Simulation Results Continued

  • 7/28/2019 L17_FSM Design Example With Verilog

    13/23Logic Design :Verilog FSM in class design example s 13 S. Yoder ND, 2010

    Xilinx Simulation Tips

    Provide a means (reset signal) to initialize allinternal variables, otherwise dont careconditions occur throughout the simulation.

    always @(posedge clk)

    begin

    if (reset) begincountValue = 0;

    clkDivOut

  • 7/28/2019 L17_FSM Design Example With Verilog

    14/23Logic Design :Verilog FSM in class design example s 14 S. Yoder ND, 2010

    CSE 20221: Logic Design

    Timers, Frequency Divider Examples

  • 7/28/2019 L17_FSM Design Example With Verilog

    15/23Logic Design :Verilog FSM in class design example s 15 S. Yoder ND, 2010

    Timers

    Timer

    time events

    divide clock frequency

    provide delay

    In each case the basic idea is to count clockpulses

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    16/23Logic Design :Verilog FSM in class design example s 16 S. Yoder ND, 2010

    Verilog Code for Timer

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    Logic Design :Verilog FSM in class design example s 17 S. Yoder ND, 2010

    Timer Simulation

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    Logic Design :Verilog FSM in class design example s 18 S. Yoder ND, 2010

    Verilog Code for Frequency Divider

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    Logic Design :Verilog FSM in class design example s 19 S. Yoder ND, 2010

    Frequency Divider Simulation

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    Logic Design :Verilog FSM in class design example s 20 S. Yoder ND, 2010

    Design of a Derived Clock

    Design a 1 millisecond clock that is derived froma 50 MHz system clock.

    Design approach

    Frequency divider

    Divide by 50,000

    Determining size (N) of counter

    given division factor, DF

    N = roundUp(ln DF / ln 2) -1

    Parameter [N:0] countValue;

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    Logic Design :Verilog FSM in class design example s 21 S. Yoder ND, 2010

    Verilog Description

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    Logic Design :Verilog FSM in class design example s 22 S. Yoder ND, 2010

    Test Fixture

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    Logic Design :Verilog FSM in class design example s 23 S Yoder ND 2010

    Similation Results


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