Digital System DesignVerilog-Part V

Amir Masoud Gharehbaghiamgh@mehr.sharif.edu

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Function Declaration

Functions can be defined in a module.

function <range_or_type> function_name;<input declarations><register declarations><function statements>endfunction

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Function Declaration (cont.)

Functions have a return valueReturn value is one bit by defaultReturn value can be a vector (if range specified)Return value can be of different register types

integer…

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Function Declaration (cont.)

Function must have at least one inputMay have more than one input

Local variables of Register type can be defined in a function

reginteger…

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Function Statements

Any sequential statementDelay or Event control is not supported in function statements

Functions are executed in 0 time

Nested function call is supported

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Function Call

Appears in expressionsFormat:function_name (input_list)

Order of inputs is the order of definition in function body

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Example: Parity Checkermodule parity (a, p) ;

input [7:0] a; output p;function par ;

input [7:0] data;par = ^ data;

endfunctionassign #10 p = par(a);

endmodule

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Example: Shiftermodule shifter (o, in, shift, lr);

input [15:0] in; input [3:0] shift;input lr;output [15:0] o; reg [15:0] o;

always @(in or shift or lr)o <= shift_lr(in, shift, lr);

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Example: Shifter (cont.)function [15:0] shift_lr ;

input [15:0] in; input [4:1] num_shift;input left_right;shift_lr = left_right ? in << num_shift :

in >> num_shift ;endfunctionendmodule

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Example: Shifter (cont.)function [15:0] shift_lr ;

input [15:0] in; input [4:1] num_shift;input left_right;reg [15:0] shl, shr;shl = in << num_shift;shr = in >> num_shift;if (left_right) shift_lr =shl; else shift_lr =shr;

endfunctionendmodule

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Example: Multifunction ALUmodule alu (a, b, s, sel);

input [7:0] a, b; input [1:0] sel;output [7:0] s; reg [7:0] s;

// function declaration comes here -> next slide

always @(a or b or sel) s <= func (a, b, sel);

endmodule

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Example: Multifunction ALU (cont.)

function integer func ;input [1:8] in1, in2; input [1:0] sel;case (sel)

0: func <= in1 + in2;1: func <= in1 - in2;2: func <= in1 << in2;3: func <= in1 >> in2;default: func <= 0;

endcaseendfunction

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Example: Moore 011 Detectormodule moore_011 (x, z, clk);

input x, clk; output z; reg z; reg [2:1] state = 0;function calc_out ; input [1:0] s;

calc_out = s == 3;endfunctionalways @(posedge clk)

state <= next_st(state,x);always @ (state) z <= calc_out (state);

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Moore 011 Detector (cont.)function [2:1] next_st ;

input [2:1] state; input xif (state == 0) next_st <= x ? 0 : 1;else if (state == 1) next_st <= x ? 2 : 1;else if (state == 2) next_st <= x ? 3 : 1;else if (state == 3) next_st <= x ? 0 : 1;else next_st <= 0;

endfunctionendmodule

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Task Declaration

Tasks can be defined in a module.

Task task_name;<interface declarations><task declarations><task statements>endtask

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Task Declaration (cont.)Interfaces can be

input / output / inoutNumber of interfaces is 0 or moreReturn values through output / inoutinterfacesLocal variables of Register type can be defined in a task

reginteger…

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Task Statements

Any sequential statementDelay or Event control is supported in task statements

Tasks may be executed in 0 time or not

Tasks can enable another tasks or have function call

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Task Enable

Appear in sequential bodiesFormat:task_name (interface_list) ;

Order of interfaces are the order of definition in task body

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Example: 011 Detectormodule mealy_011 (x, z, clk);

input x, clk; output z; reg z;reg [2:1] state = 0, next_st = 0;always @(posedge clk)

state <= next_st;task calc_out;

input [2:1] state; input x; output z;#10if (state == 2 && x) z <= 1; else z <= 0;

endtaskalways @(state or x) calc_out(state, x , z);

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Example: 011 Detector (cont.)always @(state or x)

case (state)2'b00 : next_st <= x ? 0 : 1;2'b01 : next_st <= x ? 2 : 1;2'b10 : next_st <= x ? 0 : 1;default: next_st <= 0;

endcaseendmodule

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Example: Apply Inputsmodule testbench ;

reg [7:0] a, b;// a module instantiation comes hereinitial apply (a, b);initial a = 0; initial b = 0;task apply;

output [7:0] a, b;#10 a = a + 3; #5 b = b + 1;

endtaskendmodule