journal of la a 14-enob delta-sigma based readout ...1213039/fulltext01.pdf · a 14-enob...

JOURNAL OF LATEX CLASS FILES, VOL. ??, NO. ??, ??? ??? 1

A 14-ENOB Delta-Sigma Based ReadoutArchitecture for ECoG Recording Systems

Nikola Ivanisevic, Student Member, IEEE, Saul Rodriguez, Member, IEEE, and Ana Rusu, Member, IEEE

Abstract—This paper presents a delta-sigma based readout ar-chitecture targeting electrocortical recording in brain stimulationapplications. The proposed architecture can accurately record apeak input signal up to 240 mV in a power-efficient mannerwithout saturating or employing offset rejection techniques.The readout architecture consists of a delta-sigma modulatorwith an embedded analog front-end. The proposed architectureachieves a total harmonic distortion of -95 dB by employing acurrent-steering DAC and a multi-bit quantizer implemented as atracking ADC. A system prototype is implemented in a 0.18 µmCMOS triple-well process and has a total power consumptionof 54 µW. Measurement results, across ten packaged samples,show approximately 14-ENOB over a 300 Hz bandwidth with aninput referred noise of 5.23 µVrms, power-supply/common-moderejection ratio of 100 dB/98 dB and an input impedance largerthan 94 MΩ.

Index Terms—readout, delta-sigma, ADC, instrumentation am-plifier, current-steering, DAC, tracking, DEM, ECoG.

I. INTRODUCTION

THE development of readout architectures for application-specific integrated circuits is driven by the prolifera-

tion of smart implants in the next-generation health caresystems [1]. A prime example are the implantable neuralrecording interfaces [2], which can facilitate a wide rangeof medical applications due to the integration of wirelesstelemetry [3], [4], multi-channel recording [5], [6], on-chipfeature extractions [7], data compression [8], bio-impedancemeasurements [9] and closed-loop brain stimulation [10], [11].

Traditionally, the main purpose of a neural recording in-terface has been to precisely measure the slowly changingbio-potentials, which are generated by the neural activity inthe brain, under very stringent constraints (e.g., concerningpower, area, noise, common-mode rejection, and distortion)[7], [12]. An additional challenge is the high dynamic rangeassociated with bio-potential measurements [4], [9], [12]–[14]. For instance, an electrocortical (ECoG) signal is usuallysensed, as depicted in Fig. 1, via an invasive microelectrodegrid array, which is implanted on the surface of the brain.The electrochemical interaction between the electrode and thetissue produces an offset voltage, referred to as the half-cellpotential. Ideally, in a differential measurement, two identical

Manuscript received XX YY, ZZZZ; revised XX YY, ZZZZ. Date ofpublication XX YY ZZZZ; date of current version XX YY. ZZZZ. This paperwas approved by XXXX. This work was supported by the Swedish ResearchCouncil (VR).

N. Ivanisevic, S. Rodriguez and A. Rusu are with the School of ElectricalEngineering and Computer Science, KTH Royal Institute of Technology,SE-164 40 Kista, Stockholm, Sweden (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org. Digital Object Identifier XXXX

Microelectrode array

Fig. 1. Block diagram of the proposed ECoG recording system.

electrodes should cancel-out their half-cell potentials [15]. Inpractice, a random differential electrode offset, up to hundredmillivolts, can appear [4], [13], [16], [17]. Moreover, the situa-tion is worsened when the recording functionality is combinedwith the brain stimulation, where a build-up of charge occursbetween electrodes [18]–[20], as well as undesired in-bandstimulation artifacts [16], [17]. As a result, several approacheshave been reported to cope with these problems, and they canbe classified in the following categories: AC coupling, analogDC servo loop, digitally assisted servo loop and high dynamicrange neural recording.

The most straightforward method of rejecting the electrodeoffset is by AC coupling, which performs passive high-passfiltering with a very low cut-off frequency [14], [21]–[23].However, the total common-mode rejection is limited by thecapacitor matching accuracy, which is further deteriorated bythe impedance unbalance between the sensing and referenceterminals of the analog front-end [24], [25]. An alternativesolution is to use an analog DC servo loop, which performsactive high-pass filtering, at the cost of an integrator with aconsiderable time constant [9], [26]. The main disadvantage ofthese approaches is that the cut-off frequency of each recordingchannel is prone to different variations [4]. A digitally assistedservo loop can be used to overcome this issue by controllingthe corner frequency in the digital domain [4], [13], [27]–[29]. However, the stability of a digitally assisted servo loop isimpacted by the latency of the digital filter. Another drawbackof this solution is that a charge-redistribution DAC is directlydriven by the fluctuating electrode-tissue impedance, whichcan introduce distortion in the readout due to finite inputimpedance. To circumvent this issue, a DC-coupled neuralrecording interface with a current-steering DAC was usedin [4] and [27], but with a limited peak input (± 50 mV).Although the aforementioned techniques are effective forrejecting the electrode offset in traditional neural recordinginterfaces, a different approach is needed for brain stimulationsystems. In particular, neural recording interfaces with ahigh effective-number-of-bits (ENOB>12-bit) are needed tolinearly capture the ECoG signal in the presence of largestimulation artifacts, without saturating the readout architec-


ture [16], [17]. However, even these interfaces still rely on theaforementioned offset rejection techniques.

This paper presents a power-efficient ∆Σ based readout ar-chitecture with 14-ENOB for a peak input signal of ±240 mVover a 300 Hz bandwidth, which can facilitate high-fidelityECoG recording in the presence of large stimulation artifactsand differential electrode offset, as shown in Fig. 1. Theproposed system consists primarily of a ∆Σ modulator thathas inherent immunity to flicker noise, common-mode andpower supply noise. A DC-coupled instrumentation amplifieris embedded inside the ∆Σ modulator to achieve high linearityat peak input signal and to provide a high-impedance interfacewith the electrodes. The output voltage swing requirementof the instrumentation amplifier is relaxed by employing acurrent-steering DAC and a multi-bit quantizer implementedas a tracking ADC. The system prototype is fully verifiedand the measurement results show consistent performanceacross ten packaged samples. The remainder of the paperis organized as follows. The proposed system architectureis explained in the Section II. The circuit implementation isdescribed in Section III. The measurement results are reportedand discussed in Sections IV and V, respectively. Finally, thepaper is concluded in Section VI.

II. SYSTEM ARCHITECTURE

A. Design Challenges

To acquire a deep understanding of the proposed readout ar-chitecture, key concepts are progressively introduced as shownin Fig. 2. The readout architecture presented in Fig. 2a consistsof a DC-coupled instrumentation amplifier (IA) followed bya multi-bit ∆Σ modulator [30]. The chopping technique isused to mitigate the flicker noise contribution of the readoutarchitecture, as well as to separate the input signal spectrumfrom any low-frequency common-mode or power supply noise.A dynamic element matching (DEM) technique is employed tocircumvent the linearity limitations of a multi-bit DAC. How-ever, the readout architecture in Fig. 2a introduces two keydesign challenges: the need for a power-efficient quantizationof a chopper modulated input signal and the high linearityrequirements of the instrumentation amplifier.

The first challenge can be resolved by employing a ∆Σmodulator that provides noise-shaping with a low-pass (in-stead of the traditional high-pass) characteristic, such that theoversampled narrow-band input signal is located at a carrier(chopping) frequency. This type of modulator is referred toas a high-pass (or chopper-stabilized) ∆Σ modulator, becausethe gain of the loop filter is highest at half of the samplingfrequency, fs/2, which corresponds to a high-pass filter indiscrete-time [30]–[33]. The carrier frequency of the narrow-band input signal has to be at fchop = fs/2. Otherwise, thehigh-pass ∆Σ modulator reverts to a band-pass topology andthe order of noise shaping decreases accordingly.

The second challenge can be mitigated by either employingoffset rejection techniques or, as it is proposed in this work,by embedding the IA inside the ∆Σ modulator to takeadvantage of the multi-bit quantization and to enable highlinearity performance in a power-efficient manner [34]. As

fs/2=fchop

IAS

H(z)

IFF path

DEM

FlashADC

DAC

fchop

DoutVin

a)

fchop

fchop

Zin~

Vin'

Vin

f f

IA Vin

fchop

IDAC

Dout

fs/2=fchop

IFF path

fs/2=fchop

fs/2=fchop

Dout

IDAC

IA Vin

10-comp.

10-units

X(z)

IAS

H(z)

IFF path

DAC

fchop

Vin

b)

S

DEM

Dout

fchop

fchop

10-comp.

10-units

Vin'

Zin~(Cs)-1

Dout

IDAC

FlashADC

X(z)

Tracking ADC

Vin

c)

IAS

H(z)

IFF path

DEM

fchop

Dout

T

Counter

fchop

fchop

4-comp.

Vin'Zin~

DoutDAC

10-units

IDAC

FlashADC

X(z)

Fig. 2. System architecture development process: a) the IA and ∆Σ modulatorare separated, b) the IA is embedded in the ∆Σ loop and c) addition of adigital counter to reduce the number of comparators and increase Zin.

shown in Fig. 2b, the IA is placed after the comparison withthe DAC, which bounds the voltage swing at the IA’s inputto the magnitude of the least significant bit (LSB) of theDAC. Consequently, the input feed-forward (IFF) path is DC-coupled to the microelectrode array, which decreases the inputimpedance of the readout architecture because of the samplingoperation. Removing the IFF path is a potential solution to thisissue. However, that would put a more stringent requirementon the amplifiers (OTAs) that are needed to implement the∆Σ loop filter, H(z). A better solution, as it is implementedin the proposed readout, is to reroute the IFF path from theIA’s output and add a digital counter to track the magnitude ofthe difference between the input signal and DAC output (e.g.the quantization error), as shown in Fig. 2c. In this way, theDAC is updated only when the magnitude of the X(z) signalincreases beyond the thresholds of the comparators in the flashADC, like in the case of a tracking ADC [35]. As highlightedin Fig. 2c, the key building blocks of a tracking ADC arethe flash ADC, the counter and the DAC. More importantly,the quantization error, which is needed to enable the trackingoperation, is contained in the IFF path. The benefit of thissolution is twofold: the input impedance, Zin, increases, andthe number of comparators in the flash ADC reduces.


B. IFF path design

To avoid direct feedthrough loops in the ∆Σ modulator,which is shown in Fig. 2c, the IFF path has to be sampledin a different phase than the sampling phase (S) of the loopfilter, called the tracking phase (T). Consequently, these twophases introduce a phase delay in the signal path. The impactof this phase delay is analyzed in MATLAB/Simulink bymodeling it with a 2nd order Thiran all-pass filter, which hasan excellent phase delay approximation and a flat group delayat low frequencies [36]. The transfer function of a 2nd orderThiran all-pass filter is given by

T (z) =a2 + a1z

−1 + z−2

1 + a1z−1 + a2z−2, (1)

where a1 = 0.4 and a2 = −0.0286 are the filter coefficients,which correspond to a phase delay of half a clock period.Additionally, T (z) has a net delay of two clock periods, whichcan affect the modeling of the ∆Σ loop. Therefore, the systemmodel in Fig. 3 is rearranged compared to Fig. 2c, to moveT (z) out of the loop. In this way, the net delay of T (z) doesnot have an impact on the stability of the system model. Themodel for the instrumentation amplifier, IA(z), appears twicesince it impacts both V ′in(z) and D′out(z), which correspond tothe up-converted input and output of the readout, respectively.The IFF path, in Fig. 2c, is decomposed into a feed-forwardsignal path, which is modeled as a delay of z−2 to cancelout the net delay in T (z), and a feedback path represented asa delay of z−1. The ’mixer-Counter-DEM-mixer-DAC’ pathshown in Fig. 2c is substituted in the system model, for thesake of simplicity, with a functionally equivalent digital high-pass filter (1 + z−1)−1.

C. Linear Model Analysis

The established linear model, given in Fig. 3, can providea qualitative understanding of the proposed readout architec-ture and its implications on the circuit implementation. Forinstance, a conventional ∆Σ modulator with an IFF path willhave a signal transfer function with unity gain over the entireNyquist bandwidth, however, in the proposed readout this isnot the case as it can be seen in the following expression:

STF′(z) =IA(z)

[T (z)H(z) + z−2

]G−1(1 + z−1) + IA(z) [H(z)− z−1]

, (2)

where G ≈ 0.8 is the gain of the flash ADC and the IA’stransfer function, IA(z), is approximately given by:

IA(z) ≈ 1− e−Ts2τ

1− z−1e−Ts2τ

, (3)

where τ ≈ Ts/10 is the settling time of the IA. The H(z) isimplemented as a feed-forward filter, which is adopted from[30], and is given by:

H(z) ≈ −0.6z−1

1 + z−1

[−0.6z−1

1 + z−1+ 2

]. (4)

The magnitude of the STF′(z), shown in Fig. 4a, has a high-pass characteristic with unity gain over a wide range of input

Vin'(z)

D'out(z)X(z)

E(z)

H(z)

z-2

z-1 z-1

T(z)

IA(z)

G

IA(z)

Fig. 3. Linear model of the proposed readout architecture.

Fig. 4. Magnitude of the conventional and proposed a) STF′(z), b) NTF′(z).c) Root locus of the NTF′(z). d) Magnitude of X(z)/V ′in(z) and X(z)/E(z).

frequencies near fs/2, but it does not change significantly therequirements of the ∆Σ modulator given in [30].

Similarly, the instrumentation amplifier also introduces aphase delay, which has an important impact on the stability ofthe ∆Σ modulator, in particular on the noise transfer function,which is given by:

NTF′(z) =1

G−1(1 + z−1) + IA(z) [H(z)− z−1]. (5)

Even though the modulator is operating at a relatively lowsampling frequency, fs =153.6 kHz, with an oversamplingratio of 256, the IA(z) is part of the feedback path and its phasedelay has a similar effect as the excess loop delay (ELD). Asit can be seen in Fig. 4b, a peaking occurs in the magnituderesponse of the NTF′(z), which is caused by the interactionof the poles in the unity circle shown in Fig. 4c. Since thedelayed output of the IA(z) is also added to the output ofH(z), the IA(z) also fulfills the role of the ELD compensationfilter [37]. In order to maintain stable operation, the voltageswing at node X(z) can not exceed the full-scale range of theflash ADC, which is represented as a linear gain block, G,in Fig. 3. This implies a minimum number of comparators,which can be determined from the following expressions:

X(z)

E(z)

∣∣∣∣V ′in=0

= NTF′(z)G (1 + z−1)− 1 (6)


R3

P

Ci

R

OTA1CsSd

STd

T

P

Sd

STd

R

OTA2T

fchop

Sd

OTA3Cs

10

fchop

Ci/10

Td

SdSd

TCs

22

Cs /22

Td

SdSd

TCs

22

Td

SdSd

TCs

11

CsTd

Tfchop

X(z)'IA(z) Vin(z)

T, Td

S,Sd

fch,A1, fch,A1d

fch,B1,fch,B1d

CLK

P

P

Ci

fch,A1fchop,B1fch,A1d

fchop,B1d

fchop,A1 fch,B1 fch,A1d

fch,B1d

Ci

H(z) loop lter

IFF path

-1

HP

LP

Sel

HP/LP mode

Fig. 5. Single-ended representation of the ∆Σ loop filter and the corresponding clock phases (with and without delay). The high-pass operation is achievedby swapping the integrating capacitors with the chopping mixers, fchop,A1 and fchop,B1, as shown in the inset.

X(z)

V ′in(z)

∣∣∣∣E=0

= STF′(z)G (1 + z−1) (7)

As it can be seen from the magnitude response of (6) and (7)given in Fig. 4d, the quantization error, E(z), can increase bya factor of 2.77 (or 8.85 dB), while the out-of-band tonesof V ′in(z) can appear with at most unity gain. Due to thegain in (6), the voltage swing at X(z) can increase beyondthe first quantization range in the flash ADC, e.g. ±VLSB/2.In this case, an additional pair of comparators is requiredto maintain the tracking operation when the swing at X(z)reaches the next quantization range, e.g. ±3·VLSB/2. Theseadditional comparators function as redundancy, which protectthe tracking ADC from overloading. Consequently, the flashADC requires minimum four comparators to capture thesefive level crossings (including zero) at X(z). On the otherhand, if the input signal contains large out-of-band interferesat odd multiples of the chopping frequency, then low-passfiltering can be applied to ensure that the voltage swing atX(z) remains within the quantization range.

System architecture description and analysis demonstratethat the operation of the proposed readout is similar to aconventional ∆Σ modulator. However, as shown in Fig. 3, theinstrumentation amplifier is considered both part of the signaland feedback path, which makes its circuit integration withthe loop filter a key challenge for achieving high linearity.

III. CIRCUIT IMPLEMENTATION

A. Loop filter

At the core of the proposed readout is a 2nd-order feed-forward switched-capacitor filter, and its single-ended repre-sentation is shown in Fig. 5. The switched-capacitor (SC)implementation has been chosen considering the reported po-tential power-efficiency [30]. Alternatively, recently reportedwork in [38] suggests that a continuous-time ∆Σ modulator

with chopped integrators at half the sampling rate could alsobe a power-efficient solution.

Stable operation is established by matching the samplingcapacitors, Cs, in the IFF path and the first active blockof the loop filter. In this way, a compensation filter, for theELD introduced by the IA, is implemented without additionalcomplexity. Apart from the sampling (S) and tracking (T)phases, the loop filter employs an asynchronous reset (R) anda preset phase (P). The R phase, which is not explicitly shownin Fig. 5, is used to set the initial condition of the integrators,while the P phase is used to equalize the charge in the parasiticcapacitors, at the input terminals of the OTA1,2, before mixing.Additionally, a passive mixer is placed in series with Cs ofthe IFF path to create a simple switch-RC filter [39], whichimproves the input signal response at the multiples of choppingfrequency while suppressing out-of-band interferes that canpotentially overload the internal quantizer.

Reconfiguration of the loop filter has been implemented tovalidate the immunity to flicker noise of the proposed readout.The loop filter can be reconfigured to a high-pass or a low-pass mode by adjusting the polarity of the second feed-forwardpath from the OTA1 and by disabling the switching activityof the complementary chopping clocks, fchop,A1 and fchop,B1

(see Fig. 5). Correspondingly, the SC high-pass filter reverts toa conventional integrator and the adjustment in polarity of theOTA1 output is needed to satisfy the mathematical substitutionof the z variable in H(z) with −z, which completes thetransformation from a high-pass to a low-pass topology. Thechopping frequency is set to half of the sampling rate ofthe ∆Σ modulator (76.8 kHz). As a result, a higher flickernoise corner of the IA can be tolerated, but, the influenceof the parasitic capacitance on the system input impedanceis more pronounced. Simulation results show that the inputimpedance of the IA (without packaging, ESD diodes, and


I/O pad parasitics) is limited to approximately 200 MΩ,which is sufficient for an ECoG recording interface [12].The parasitic capacitance of the transistors in the chopper(mixer) circuit is negligible due to their small dimensions(W/L = 800 nm/180 nm). Moreover, the correspondingmagnitude of charge injection (≈ fC) is considerably lowerthan the magnitude that can be found in literature, for brainstimulation (≈ nC) [18]–[20]. Additionally, the proposed read-out architecture operates with a 0.6 V common-mode voltage,which is beneficial for reducing the thermal noise density andsignal dependent charge injection introduced by the switches.

In the high-pass mode, the dominant noise source is thethermal kT/C noise, which is generated primarily by thefirst high-pass filter and secondarily by the IA and DAC.Because the system is limited by the kT/C noise, the low noiseperformance has to be traded-off with the capacitor area. Also,a substantial sampling capacitance puts a tougher challenge onthe IA specifications, which increases the power dissipation.Alternatively, lower noise performance can be achieved byincreasing the sampling rate of the ∆Σ modulator whilemaintaining the same cut-off frequency in the digital filter (seeFig. 1), but, at the cost of higher power consumption in bothanalog and digital domains. Moreover, a higher sampling rate,and subsequently a higher chopping frequency, reduces theinput impedance of the system. Therefore, we choose Cs andfs to be 6.6 pF and 153.6 kHz, respectively, as a trade-offbetween the noise, area/power consumption, input impedanceand IA linearity.

B. Current Feedback Instrumentation AmplifierA low power, low noise, high common-mode rejection,

current feedback topology is chosen for the IA [9]. The circuitdiagram of the IA is shown in Fig. 6a. To achieve a low powerconsumption despite the relatively high chopping frequency,all transistors in the signal path are biased in weak inversion re-gion, while the transistors in the biasing network are forced tomoderate inversion to reduce their thermal noise contribution.For the input stage, M1,2, PMOS transistors are chosen due tolower flicker noise contribution and improved isolation fromthe substrate noise. Alternatively, triple-well transistors couldhave been used, but the large design rule separation betweenthe different wells would impact the matching accuracy. Inorder to introduce design freedom in setting up the DC oper-ating point for the input and output stages, the intermediatestage is implemented as an NMOS folded-cascode with M3,4,which increases the loop gain and, in turn, the linearity of theIA, but, at the cost of an increased noise budget. The outputstage, M5 and M6, provides voltage buffering and currentfeedback via source degeneration resistor, R2. Consequently,the output stage experiences both the input and output voltageswings, which negatively impacts the linearity of the current-feedback IA. However, by including the IA inside a multi-bit∆Σ modulator, this issue is resolved partially since the outputvoltage across R2 is now reduced to the LSB of the DAC.The remaining part of the issue is the input signal swing,which induces a large current across resistor R1. Thus, wechoose R1 and R2 to be approximately 70 kΩ as a trade-off between linearity and noise performance. Additionally,

VDDA1

a)

DAC

10 units

R1/2 R1/2

R2/2 R2/2

to input

CMFB

0.6 VVcascB VcascB

VcascA VcascA

VbiasP VbiasP

VbiasN VbiasN

CMFBout

GNDA

IDAC+

DAC<9:0>

CC

1.2 A

1.95 A

1 A

4.45 A

750nA

M1 M2

M3 M4

M5 M6

IDAC

CC

Vin+Vin-

b) GNDA

2R1

VDDA1

IDAC+ILSB

DAC<0>

Cext 1:1

IDAC

#1

#...

#10

DAC<8...1>

DAC<9>

IA V

in-

IA V

in+

850 nA

Fig. 6. a) Instrumentation amplifier and b) current-steering DAC.

the linearity performance is also affected by the IA loop-gain at the chopping frequency and its harmonics. Consideringthe difficulties of stabilizing a high loop-gain amplifier withmultiple poles, a compensation capacitor, CC ≈ 660 fF, isadded in parallel with the drain of M3,4 to define a dominantpole. The position of the high-frequency poles introduced bythe source nodes of M1,2 and M3,4 is carefully controlledby maintaining low parasitic capacitance. Moreover, the poleintroduced by Cs is effectively canceled-out by choosing R3,(shown in Fig. 5), to be approximately the same as R2. Thecombination of R3 and Cs produces an equivalent resistancein the order of a MΩ, which has a negligible loading effect onthe IA gain. Considering the noise performance, the value ofR3 is theoretically irrelevant in a kT/C noise limited system.However, it has a direct impact on filtering the IA thermalnoise before aliasing. The value of R3 also impacts thesettling-time, and consequently the ELD, which is determinedby τ ≈ (R2/2 +R3)Cs. Based on system analysis and circuitsimulation results, a τ ≈ 0.7 µs is chosen as a trade-offbetween the IA noise aliasing and ELD.


C. Current-steering DAC

The DAC is implemented with a current-steering topology,which provides a high output impedance and enables the IA tobe interfaced to the electrodes via a high-impedance terminal.In principle, the DAC injects a current offset at the start ofeach sampling phase, which is compared against the inducedcurrent of the up-converted input signal. The resulting residuerepresents the quantization error, which is in the order of±R2ILSB. The current-steering DAC also provides a biasingcurrent for transistors M5,6 via ten unit elements, as it can beseen in Fig. 6a. When the DAC<9:0> thermometer code hasthe same number of logical ”1” and ”0”, the biasing currentis equally distributed among the IDAC+ and IDAC- currentbranches. Each element is implemented as a PMOS currentsource with a cascode, as it can be seen in Fig. 6b, so thatthe equivalent output impedance of all unit elements does notintroduce even order distortions [40]. The minimum transistordimensions are defined by the matching accuracy betweenthe unit elements. Behavioral level simulations showed that amaximum 1% standard deviation can be tolerated in the drain-source current of a unit element when a first order dynamicelement matching (DEM) is applied to the DAC. Based on theMonte Carlo results with both device and process mismatch,a W/L ratio of 80 µm / 8 µm is selected. The choppingof the IDAC output is performed in the digital domain byapplying the XOR operation between the fchop,A1 clock andDAC<9:0> signal. For testing purposes, an external capacitor(Cext ≈ 1 µF) is used to provide a clean biasing reference.

D. Tracking ADC

As it was explained in Section II, the tracking ADC con-sists of the aforementioned current-steering DAC, which islinearized with the DEM, as well as a flash ADC with areduced number of comparators and a digital counter.

1) Flash ADC: The output of the loop filter, X(z), isquantized by the flash ADC implemented with 4-comparators,while being assisted by a digital counter and the current-steering DAC to achieve the same functionality as a flashADC with 10-comparators. Each comparator consists of adifferential difference amplifier (DDA) and a current drivenstrong-arm latch, as it can be seen in Fig. 7a. The propagationdelay of the latch will vary depending on the magnitude of thesignal swing at X(z). As a result, simple combinational logicis used to generate asynchronous pulses (CLK1,2,3 in Fig. 7a),for the subsequent digital circuits, when the outputs of allcomparators resolve. An alternative solution, though with moresignificant power consumption and circuit complexity, wouldbe to use a higher clock frequency and a timer to preciselygenerate the necessary clock pulses.

The voltage references for the comparators are implementedvia a resistor ladder driven by a current source, equal to half ofthe DAC unit value, to further reduce the voltage swing at nodeX(z). The common-mode voltage of the ladder is regulatedto 0.6 V, by using a feedback amplifier. The ladder resistorsare the same value as R2 and are placed close together on thedie to ensure proper matching.

5

4

3

0 time [nT]

Dout<3:0> [LSB]

b)

DAC<9:0> Mixing (XOR)

with fchop Dout<3:0>

Bi-directional

shift register

Sign extraction

+Mixing (XOR)

adderWaller

Dout<3>

Control

Logic

Counter

Q<2:1>

Dout<2:0>

REG<4:0>

REG<0>

CLK

CLK3

CLK1

CLK2

CLK1

Tree-structured

DEM

Parallel

register

CLK3

VREF4X(z)

Comparator #4

-1.5 VLSB= VREF1 -0.5 VLSB= VREF2

+0.5 VLSB= VREF3+1.5 VLSB= VREF4

Voltage references

Flash ADC

Q<3>

...#1

Δt1

Δt2

Δt3

CLK

DEM<9:0>10

Q<3:0>

a)

DDA Latch

LSB

LSB

Fig. 7. a) Block diagram implementation of the tracking ADC. b) An exampleof the operation principle for the tracking ADC.

2) Counter and Tree-structured DEM: The digital counter,shown in Fig. 7a, operates as a bi-directional shift register,which can shift by one or two steps or maintain the previousvalue. The outputs of the flash ADC controls the directionand amount of the shifting, as it is depicted in Fig. 7a.The challenging part of the counter control logic is that ithas to determine the polarity of a fully differential signalX(z) without a direct point of reference, due to a reducednumber of comparators. A simple solution to this problem,as implemented in the proposed work, is to detect whichof the four comparators activates first when the counter isat zero (Dout<3:0> = 0), which is functionally equivalent tozero-crossing detection. The sign extraction logic is triggeredafter approximately ∆t1 = 1 ns (see Fig. 7a) of the risingedge of the CLK . The output of the counter, which istriggered ∆t2 = 10 ns after CLK1, is converted to a 3-bitbinary number Dout<2:0> and a sign bit, Dout<3>. The finalsigned binary output Dout<3:0> has to be first down-convertedfor the DEM to function correctly. The down-conversion isachieved by toggling the Dout<3> in the sign extraction logicduring every clock cycle. An example waveform of the digitaloutput, Dout<3:0>, is shown in Fig. 7b, where we can seethat it usually changes between adjacent quantization levels,but in some cases it can change by two LSBs. Thus, thetracking ADC monitors the slowly changing X(z) and updatesthe Dout<3:0>, and consequently the DAC output, accordinglywhen X(z) increases beyond the comparator thresholds.

A tree-structured DEM, presented in [30], is selected overother linearizion techniques because of the following advan-


tages [41]. 1) It is not as susceptible to generating spurioustones in the signal-band, 2) it can be implemented with anarbitrary number of DAC levels and 3) the required digitallogic is relatively simple, and it introduces only the combina-tional network delay (low latency). The internal registers ofthe tree-structured DEM, which control the switching logic,can be updated during the falling edge of CLK2, which doesnot introduce additional latency. As a result, the tree-structuredDEM functions as a look-up-table, which is randomized foreach subsequent digital input. A parallel register is addedbetween the DEM<9:0> output and the DAC<9:0>, as shownin Fig. 7a, to prevent any glitches from propagating to the IAduring logic transitions. The parallel register is triggered bythe rising edge of CLK3, which is delayed by ∆t3 = 10 nsafter CLK2.

E. Clock generation, Biasing network and Input CMFB

The non-overlapping clocks for the SC circuits are generatedwith a pair of cross-coupled NOR gates and delays. Asmentioned in Section III-A, the common-mode level at thesource/drain of an NMOS switch is reduced to 0.6 V comparedto the popular choice of VDD/2, which eliminates the needfor CMOS switches or clock bootstrapping. The choppingclock is created by using a T flip-flop, which divides thesampling clock frequency by two. The delays for setting upthe triggering events (for the counter, DEM and DAC register)are implemented with a cascaded stage of inverters, which areloaded with MOS-capacitors to allow for a compact integrationwith the digital circuitry. The internal biasing current isimplemented with a PTAT current reference (constant-Gm)circuit. The input common-mode feedback (I-CMFB) of theIA is set to 0.6 V with a single-ended differential pair biasedwith 1 µA and stabilized externally using a 10 pF capacitor.

IV. MEASUREMENT RESULTS

The proposed readout architecture is implemented in a0.18 µm CMOS triple-well process. The die micrograph withan overlying transparent image of the layout with block anno-tations, is shown in Fig. 8. The active die area, excluding thebonding pads, the logo, and the I/O drivers, is approximately0.43 mm2. There are four separate power domains in the chip,as it can be seen by the power-cuts in Fig. 8, two for the analogand two for the digital domains. The IA, DAC and the biasingnetwork fall under one 1.8 V analog domain, while the SCcircuits and the flash ADC have a separate analog domain.Similarly, in the digital domain, the DEM and the remainingon-chip logic are powered with a 1.8 V digital supply, whichis separated from the digital I/Os supply. Additionally, n-welltrenches are used to increase the lateral isolation of the noise-sensitive blocks. All digital circuits are placed in deep n-wellsto improve the shielding of the substrate from the digitalactivity. The chip is bonded to a 44-pin plastic leaded chipcarrier package for testing purposes. The packaged chip, e.g.,the device-under-test (DUT), is characterized using a customevaluation board (EVB).

Flash

ADC

Clock

gen.

1,72 mm

1,6

2 m

m

DEM and

Counter

Fig. 8. Die micrograph with an overlay of the transparent layout.

100

101

102

103

104

−120

−100

−80

−60

−40

−20

0

Frequency [Hz]

PS

D [

dB

FS

/NB

W]

SNDR = 68.47 dBSFDR = 69.46 dBcSNDR = 88.10 dB SFDR = 94.98 dBc

OSR = 256no. avg = 8

NBW = 2.967e−05

DEM off

DEM on

DC

Fig. 9. Power spectral density measurements of a -4.7 dBFS input sine waveat 37.5 Hz with DEM turned off (red line) and on (black line).

A. Measurement Setup

An ultra-low distortion signal generator (Keysight U8903B)is used to create a pure test-tone inside the signal bandwidth,as it is required for measuring the linearity of a DUT.The balanced test-tone is first processed by a common-mode(CM) level shifter (AD8475), which sets the common-modevoltage to 0.6 V. The common-mode level of the test-tone iscoarsely defined via an external current source and is regulatedby the I-CMFB of the IA. The on-board anti-aliasing RCfilter is implemented with a 200 pF ceramic capacitor and1 kΩ resistors with a ±0.1% tolerance rating. The voltagesupply and reference levels are provided to the DUT viaonboard voltage regulators (LP5912, TPS7A88, TPS7A8300).A function/arbitrary waveform generator (Agilent 33250A) isused to provide the external oversampling clock. The outputdata stream is captured by a digital logic analyzer (TektronixTLA621), which is triggered externally by the aforementionedoversampling clock. A Hann2 window is applied on thedata stream, before calculating a 65536-point fast Fouriertransform (FFT), to prevent signal leakage due to the lackof synchronization between the clock and signal generator.The resulting power spectral density (PSD) is averaged eighttimes to reduce the measurement uncertainty in the results.The DC offset introduced by the custom EVB is removed inpost-processing.


B. Measurement Results

The measured power consumption of the DUT, excludingthe I/O pads, is approximately 54 µW. Post-layout simulationsshow that the power distribution is as follows: 33.2 µW isconsumed cumulatively by the IA, DAC, biasing networkand I-CMFB; 11.7 µW is consumed mostly by the switched-capacitor circuits and partly by the flash ADC; the remaining9.1 µW is dissipated in the digital circuits.

The PSD measurements, when the DEM is turned on andoff, are shown in Fig. 9. The harmonic distortion, which isgenerated by the device mismatches in the current-steeringDAC, dominates the output spectrum of the DUT when theDEM is turned off. Note that the even-order harmonics arenot canceled since they are caused by the mismatch errorsbetween the unit elements (and not due to the transistornonlinearity). The spurious-free dynamic range (SFDR) im-proves by approximately 25 dB when the DEM is activatedand peaks at around 95 dBc. Subsequently, the SFDR is nolonger limited by the mismatch errors in the DAC, but bythe nonlinearity of the IA. Based on the measured PSD, thesignal-to-noise-and-distortion ratio (SNDR) is approximately88.1 dB for an in-band tone at 37.5 Hz with an amplitude of-4.7 dBFS. Considering the frequency resolution of the FFTand the applied averaging in the measurement setup, we canconclude that the SNDR is limited by the in-band noise and notby the nonlinearity of the DUT. These findings are consistentin all available packaged samples as shown in Fig. 10. Aspreviously explained in Section II-C, there is a noticeablepeak in the noise shaped spectrum in Fig. 9, which is morepronounced in the measurements than predicted by the simplelinear model, due to a gain error in the IA at the choppingfrequency. It is worth considering that the DC voltage offsetof the DUT spreads to the two adjacent bins, as highlighted inFig. 9 and Fig 11, due to the windowing function and shouldnot be mistaken with the flicker noise.

The noise floor and the DC offset of the DUT are measuredby connecting the differential inputs of the CM level shifter tothe ground of the EVB. The results of the noise measurementare shown in Fig. 11, while a histogram of the in-band noiserms values across samples is given in Fig. 12. The high-pass∆Σ modulator outperforms its low-pass counterpart in boththe rms noise and average input DC offset. The DC offset ofthe HP∆Σ modulator is approximately 25.85 µVrms across allsamples. As expected, the characteristic slope (-10 dB/decade)of the flicker noise dominates the in-band frequencies whenthe low-pass mode is activated. By configuring the loop filterto the high-pass operation, the rms noise reduces by morethan three times on average, as shown in Fig. 12. Note thatthe spurious out-of-band tones that are present in the noisemeasurements are caused by the pattern noise generated bythe ∆Σ modulator for a constant input (offset).

The dynamic range of the DUT is measured by sweepingthe input amplitude at 37.5 Hz from -77.7 to -3.5 dBFSand is shown in Fig. 13, Considering that dBFS refers to10log10

[vdiff,in/

(VFS√

2)]2

, where VFS is the DAC full-scalevalue of approximately 301.37 mVpeak and vdiff,in is the inputamplitude, the peak SNDR/SNR performance of 88/89 dB is

1 2 3 4 5 6 7 8 9 1060

70

80

90

100

110

120

130

140

Measured Samples

SN

DR

/SF

DR

/DR

[d

B/d

Bc/d

B]

SNDR

DEM,OFF, avg=70.86 dB, std=3.44 dB

SFDRDEM,OFF

, avg=73.66 dBc, std=4.05 dBc

SNDRDEM,ON

, avg=87.21 dB, std=0.70 dB

SFDRDEM,ON

, avg=93.06 dBc, std=1.70 dBc

DRDEM,ON

, avg=89.76 dB, std=1.17 dB

Fig. 10. Measured SNDR, SFDR across different packaged samples withDEM turned on/off, and achievable dynamic range (DR) with DEM.

100

101

102

103

104

−120

−100

−80

−60

−40

−20

0

Frequency [Hz]

PS

D [

dB

FS

/NB

W]

vn,HP

= 5.23 µVrms

vn,LP

= 17.68 µVrms

OSR = 256no. avg = 8

NBW = 2.967e−05

HP

LP

DC

Fig. 11. Measured input referred noise floor of the DUT for the high-pass(black line) and low-pass (gray line) configuration.

1 2 3 4 5 6 7 8 9 100

5

10

15

20

25

30

Measured Samples

Inp

ut

refe

rred

rm

s−

no

ise [

µV

rms]

HP, avg = 5.69 µVrms

, std = 0.95 µVrms

LP, avg = 19.32 µVrms

, std = 2.47 µVrms

Fig. 12. Measured total input referred rms-noise across different packagedsamples in the high-pass (black bar) and low-pass (gray bar) configuration.

measured for an input amplitude of -4.82 dBFS. The proposedarchitecture achieves 92 dB of dynamic range (DR). As itcan be appreciated from Fig. 10, the results are in goodagreement across all samples. Similarly, the peak SNDR/SNRperformance remains relatively consistent for various in-bandtest frequencies, as shown in Fig. 14.

The power supply rejection ratio (PSRR) measurements areperformed by providing the 1.8 V supply voltage togetherwith a -7.5 dBFS test-tone at 57.5 Hz. The correspondingPSRR is approximately 100 dB on average, as shown inFig. 15. The same setup is used for the common-moderejection ratio (CMRR) measurements, but with the common-mode voltage set to 0.6 V. The measured CMRR of the DUT


−100 −80 −60 −40 −20 00

20

40

60

80

100

Amplitude [dBFS]

SN

DR

/SN

R [

dB

]

Zoomed in

SNDR

SNR

−7 −6 −5 −4 −384

86

88

90

92

Fig. 13. Measured SNR and SNDR over various input signal amplitudes. Thecurve is extrapolated for input amplitudes smaller than -77.7 dBFS.

30 40 50 60 70 80 90 100 110 12085

86

87

88

89

90

Frequency [Hz]

SN

DR

/SN

R [

dB

]

SNR

#5

SNR#6

SNR#7

SNDR#5

SNDR#6

SNDR#7

Fig. 14. Measured SNR and SNDR at peak input amplitude over variousin-band frequencies (37.5 Hz, 56.25 Hz, 75 Hz and 93.75 Hz).

1 2 3 4 5 6 7 8 9 1090

95

100

105

110

Measured Samples

PS

RR

/CM

RR

[d

B]

PSRR, avg= 100.24 dB, std = 2.79 dB

CMRR, avg= 97.80 dB, std = 0.80 dB

Fig. 15. Histogram of the measured PSRR and CMRR at 57.5 Hz with a-7.5 dBFS test tone.

is approximately 98 dB on average, as shown in Fig. 15.The largest impedance mismatch, between the two recordingelectrodes, Zelect1 and Zelect2, for which the intrinsic CMRR ofthe system deteriorates by -3 dB, is approximately 1.2 kΩ (as-suming Zin>>Zelect1+Zelect2). Subsequently, the DUT inputimpedance, Zin, is limited to 94 MΩ at 57.5 Hz due to theadditional parasitic capacitance from the chip package.

V. DISCUSSION

A performance comparison of the proposed system with thestate-of-the-art ASICs for ECoG recording is summarized inTable I. The total harmonic distortion (THD) of the proposedarchitecture surpasses that of the state-of-the-art, in particular,

when considering the maximum peak-to-peak differential input(vpp,max). In conventional readout architectures, the THD andnoise are usually reported separately for the analog front-end and ADC without capturing the achievable ENOB of theentire system. Therefore, we combine the reported noise, vin,n,and THD performance (for vpp,max) in literature to calculatethe peak SNDR, and subsequently the ENOB, by using thefollowing expression:

SNDR’ =1

2

10 · log

(0.5vpp,max

vin,n√

2

)2

− THDdB

−3dB. (8)

Compared to the SNDR expression from [28], in (8) wealso include the linearity performance of the system. Theassumption is that the THD is primarily dominated by thethird order harmonic, which is a reasonable assumption for adifferential architecture, but, also optimistic since it neglectsthe existence of other harmonics. The ENOB of the system isthen calculated as:

ENOB =SNDR’− 1.76

6.02. (9)

Having ENOB, we can now have a comparison of thepower-efficiency at system level across different readoutdesigns by using the well-known Walden figure-of-merit(FOMW), which is given by:

FOMW =Ptotal

2 · BW · 2ENOB , (10)

where Ptotal is the total power consumption, and BW is the sig-nal bandwidth. The FOMW represents the amount of investedenergy in the readout architecture and has been recently usedto compare neural recording interfaces for action potentials[42]. As it can be seen in Table I, the proposed ECoG readoutachieves an excellent power-efficiency of 4.37 pJ/conversion-step and 14.33-ENOB. Additionally, according to the SchreierFOM, the proposed solution achieves a power-efficiency of155 dB, which is among the best of the start-of-the-art, dueto the high ENOB. However, the presented chip prototypehas a large area consumption compared to the state-of-the-art,primarily due to the sampling capacitors in the first high-passfilter. Although if we calculate the product of the FOMW andarea, which is a metric that has been recently introduced in[42], the proposed architecture has a moderate utilization ofboth power and area. On the other hand, the input referrednoise (IRN) is also comparatively higher due to the discrete-time operation of the ∆Σ loop filter. A potential solution,though at the cost of the reduced maximum input range, is toincrease the IA voltage gain to approximately 4 (e.g. 12 dB),which should reduce the total IRN by half and the peak inputswing to ≈ ±50 mV, which is currently a more popular valueamong the state-of-the-art.

VI. CONCLUSION

This paper has presented a ∆Σ based readout architecturewith a 92 dB dynamic range, which can be used for ECoGrecording in the presence of brain stimulation artifacts andelectrode offset. The readout architecture is comprised of a


TABLE IPERFORMANCE COMPARISON WITH THE STATE-OF-THE-ART FOR ECOG RECORDING.

[25] [5] [6] [13] [28] [16] ThisPublished in RHD2132’12 TCAS-I’13 JSCC’14 JSCC’15 TBCAS’16 JSCC’17 WorkTechnology [nm] N/A 180 180 65 180 40 180Area [mm2/ch.] 0.48(a) 0.282 0.19 0.025 0.1 0.135 0.43Supply(ana./dig.) [V] 3.3 1 / 1.8 1.8 0.5 1.5 1.2 / 0.45 1.8Power [µW/ch.] 93(a) 8.42(a) 28 2.3 5.5 7 54IRN [µVrms] 2.4 1.7(a) 5.8 1.29 1 5.2 5.23for BW [Hz] 200 0.38−438 0.5−200 500 250 1-200 300|ZIN| [MΩ] 50 16(a) 2500 28 62 31(a) 94meas. freq. [Hz] 10 50 50 100 76 50 57.5CMRR [dB] 82 60 60 88 97 66 98PSRR [dB] 75 70 76 67 N/A N/A 100THD [dB] -42 N/A -40 -48 -74 -79 -95for vpp,max [mVpp] 10 N/A 18 1 4 100 480Max Offset [mV] ±400 AC-Coupled AC-Coupled ±50 ±30 ±50 ±240ENOB [bits] 7.96 8.3(c) 7.58 7.24 9.43(b) 12(b) 14.33(b)

FOMW [pJ/conv.] 936.71 24.11 373.77 15.22 15.99 4.27 4.37FOMW·Area [pJ·mm−2/conv.] 449.62 6.8 71.02 0.38 1.6 0.58 1.88FOMS [dB](d) 112.98 129.91 115.84 128.72 135.08 148.56 155.47

a) Estimated based on the reported information.b) Reported ENOB from the SNDR measurements at system level.c) Reported ENOB for just the ADC.d) FOMS = SNDR’ + 10 · log(BW/Power).

high-pass ∆Σ modulator with a tracking ADC and an embed-ded current-feedback IA. The proposed system can record apeak input signal of ±240 mV over a 300 Hz bandwidth with a14.33-ENOB. Additionally, the proposed readout architecturereports an excellent power-efficiency and a moderate area-efficiency of 4.38 pJ/conv.-step and 1.88 pJ·mm−2/conv.-step,respectively.

ACKNOWLEDGMENT

The authors would like to thank M. Gustafsson fromMaxim Integrated; E. Habekotte from Catena Microelectron-ics; R. C. Onet from Technical University of Cluj-Napoca;G. Amozandeh, H. Bengtsson and O. Renstrom from Erics-son AB and L. Karlsson and J. Edvinsson from Exploric forvaluable discussions and comments during design reviews. Inaddition, the authors want to acknowledge Keysight Technolo-gies for lending the necessary lab equipment. Lastly, we wouldlike to thank W. Marxer from Europractice Fraunhofer IIS forthe technical support that lead to a successful tape-out.

REFERENCES

[1] J. Andreu-Perez, D. R. Leff, H. M. D. Ip, and G. Z. Yang, “Fromwearable sensors to smart implants– toward pervasive and personalizedhealthcare,” IEEE Trans. Biomed. Eng., vol. 62, no. 12, pp. 2750–2762,Dec 2015.

[2] P. Cong, “Neural interfaces for implantable medical devices: Circuitdesign considerations for sensing, stimulation, and safety,” IEEE Solid-State Circuits Mag., vol. 8, no. 4, pp. 48–56, Nov 2016.

[3] K. Abdelhalim, H. M. Jafari, L. Kokarovtseva, J. L. P. Velazquez, andR. Genov, “64-channel UWB wireless neural vector analyzer SoC with aclosed-loop phase synchrony-triggered neurostimulator,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2494–2510, Oct 2013.

[4] H. Kassiri, A. Bagheri, N. Soltani, K. Abdelhalim, H. M. Jafari,M. T. Salam, J. L. P. Velazquez, and R. Genov, “Battery-less tri-band-radio neuro-monitor and responsive neurostimulator for diagnosticsand treatment of neurological disorders,” IEEE J. Solid-State Circuits,vol. 51, no. 5, pp. 1274–1289, May 2016.

[5] X. Zou, L. Liu, J. H. Cheong, L. Yao, P. Li, M. Y. Cheng, W. L. Goh,R. Rajkumar, G. S. Dawe, K. W. Cheng, and M. Je, “A 100-channel1-mW implantable neural recording IC,” IEEE Trans. Circuits Syst. I,Reg. Papers, vol. 60, no. 10, pp. 2584–2596, Oct 2013.

[6] C. M. Lopez, A. Andrei, S. Mitra, M. Welkenhuysen, W. Eberle,C. Bartic, R. Puers, R. F. Yazicioglu, and G. G. E. Gielen, “Animplantable 455-active-electrode 52-channel CMOS neural probe,” IEEEJ. Solid-State Circuits, vol. 49, no. 1, pp. 248–261, Jan 2014.

[7] F. Zhang, A. Mishra, A. G. Richardson, and B. Otis, “A low-powerECoG/EEG processing IC with integrated multiband energy extractor,”IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 58, no. 9, pp. 2069–2082,Sept 2011.

[8] K. H. Teng, T. Wu, X. Liu, Z. Yang, and C. H. Heng, “A 400 MHzwireless neural signal processing IC with 625x on-chip data reductionand reconfigurable BFSK/QPSK transmitter based on sequential injec-tion locking,” IEEE Trans. Biomed. Circuits Syst., vol. 11, no. 3, pp.547–557, June 2017.

[9] J. Xu, B. Busze, C. V. Hoof, K. A. A. Makinwa, and R. F. Yazicioglu,“A 15-channel digital active electrode system for multi-parameter biopo-tential measurement,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp.2090–2100, Sept 2015.

[10] M. A. B. Altaf, C. Zhang, and J. Yoo, “A 16-channel patient-specificseizure onset and termination detection SoC with impedance-adaptivetranscranial electrical stimulator,” IEEE J. Solid-State Circuits, vol. 50,no. 11, pp. 2728–2740, Nov 2015.

[11] H. Kassiri, S. Tonekaboni, M. T. Salam, N. Soltani, K. Abdelhalim,J. L. P. Velazquez, and R. Genov, “Closed-loop neurostimulators: Asurvey and a seizure-predicting design example for intractable epilepsytreatment,” IEEE Trans. Biomed. Circuits Syst., vol. 11, no. 5, pp. 1026–1040, Oct 2017.

[12] S. Ha, A. Akinin, J. Park, C. Kim, H. Wang, C. Maier, P. P. Mercier,and G. Cauwenberghs, “Silicon-integrated high-density electrocorticalinterfaces,” Proc. IEEE, vol. 105, no. 1, pp. 11–33, Jan 2016.

[13] R. Muller, H. P. Le, W. Li, P. Ledochowitsch, S. Gambini, T. Bjorninen,A. Koralek, J. M. Carmena, M. M. Maharbiz, E. Alon, and J. M. Rabaey,


“A minimally invasive 64-channel wireless µECoG implant,” IEEE J.Solid-State Circuits, vol. 50, no. 1, pp. 344–359, Jan 2015.

[14] W. A. Smith, B. J. Mogen, E. E. Fetz, V. S. Sathe, and B. P. Otis,“Exploiting electrocorticographic spectral characteristics for optimizedsignal chain design: A 1.08 µW analog front end with reduced ADCresolution requirements,” IEEE Trans. Biomed. Circuits Syst., vol. 10,no. 6, pp. 1171–1180, Dec 2016.

[15] J. G. Webster, Medical Instrumentation Application and Design, 4th ed.New York: Wiley, 2009, pp. 233–234.

[16] W. Jiang, V. Hokhikyan, H. Chandrakumar, V. Karkare, andD. Markovic, “A ± 50-mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 173–184, Jan 2017.

[17] H. Chandrakumar and D. Markovic, “A high dynamic-range neuralrecording chopper amplifier for simultaneous neural recording andstimulation,” IEEE J. Solid-State Circuits, vol. 52, no. 3, pp. 645–656,March 2017.

[18] H. M. Lee, K. Y. Kwon, W. Li, and M. Ghovanloo, “A power-efficientswitched-capacitor stimulating system for electrical/optical deep brainstimulation,” IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 360–374,Jan 2015.

[19] S. Nag, X. Jia, N. V. Thakor, and D. Sharma, “Flexible charge balancedstimulator with 5.6 fC accuracy for 140 nC injections,” IEEE Trans.Biomed. Circuits Syst., vol. 7, no. 3, pp. 266–275, June 2013.

[20] K. Sooksood, T. Stieglitz, and M. Ortmanns, “An active approachfor charge balancing in functional electrical stimulation,” IEEE Trans.Biomed. Circuits Syst., vol. 4, no. 3, pp. 162–170, June 2010.

[21] P. Kmon and P. Grybo, “Energy efficient low-noise multichannel neuralamplifier in submicron CMOS process,” IEEE Trans. Circuits Syst. I:Reg. Papers, vol. 60, no. 7, pp. 1764–1775, July 2013.

[22] R. R. Harrison and C. Charles, “A low-power low-noise CMOS amplifierfor neural recording applications,” IEEE J. Solid-State Circuits, vol. 38,no. 6, pp. 958–965, June 2003.

[23] J. Xu, T. Wu, W. Liu, and Z. Yang, “A frequency shaping neural recorderwith 3 pF input capacitance and 11 plus 4.5 bits dynamic range,” IEEETrans. Biomed. Circuits Syst., vol. 8, no. 4, pp. 510–527, Aug 2014.

[24] K. A. Ng and Y. P. Xu, “A low-power, high CMRR neural amplifiersystem employing CMOS inverter-based OTAs with CMFB throughsupply rails,” IEEE J. Solid-State Circuits, vol. 51, no. 3, pp. 724–737,March 2016.

[25] I. Technologies. (2012) RHD2000 series digital electrophysiologyinterface chips. [Online]. Available: http://www.intantech.com/files/Intan RHD2000 series datasheet.pdf

[26] M. A. B. Altaf, C. Zhang, and J. Yoo, “A 16-channel patient-specificseizure onset and termination detection SoC with impedance-adaptivetranscranial electrical stimulator,” IEEE J. Solid-State Circuits, vol. 50,no. 11, pp. 2728–2740, Nov 2015.

[27] R. Muller, S. Gambini, and J. M. Rabaey, “A 0.013 mm2, 5 µW , DC-coupled neural signal acquisition IC with 0.5 V supply,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 232–243, Jan 2012.

[28] E. Greenwald, E. So, Q. Wang, M. Mollazadeh, C. Maier, R. Etienne-Cummings, G. Cauwenberghs, and N. Thakor, “A bidirectional neuralinterface IC with chopper stabilized bioADC array and charge balancedstimulator,” IEEE Trans. Biomed. Circuits Syst., vol. 10, no. 5, pp. 990–1002, Oct 2016.

[29] A. Bagheri, M. T. Salam, J. L. P. Velazquez, and R. Genov, “Low-frequency noise and offset rejection in DC-coupled neural amplifiers:A review and digitally-assisted design tutorial,” IEEE Trans. Biomed.Circuits Syst., vol. 11, no. 1, pp. 161–176, Feb 2017.

[30] N. Ivanisevic, S. Rodriguez, and A. Rusu, “A 96.4 dB high-pass delta-sigma modulator with dynamic biasing and tree-structured DEM,” in in14th IEEE Int. NEWCAS Conf., June 2016, pp. 1–4.

[31] H. A. Khushk, P. Loumeau, and V. T. Nguyen, “A comparative study ofloop filter alternatives in second-order high-pass ∆Σ modulators,” IEEETrans. Circuits Syst. I, Reg. Papers, vol. 58, no. 11, pp. 2604–2613, Nov2011.

[32] K. Ishida and M. Fujishima, “Chopper-stabilized high-pass sigma deltamodulator utilizing a resonator structure,” IEEE Trans. Circuits Syst. II,Analog Digit. Signal Processing, vol. 50, no. 9, pp. 627–631, Sept 2003.

[33] J. M. de la Rosa, S. Escalera, B. Perez-Verdu, F. Medeiro, O. Guerra,R. del Rio, and A. Rodriguez-Vazquez, “A CMOS 110-dB@40-kS/sprogrammable-gain chopper-stabilized third-order 2-1 cascade sigma-delta modulator for low-power high-linearity automotive sensor ASICs,”IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2246–2264, Nov 2005.

[34] R. S. Rajan and S. Pavan, “Design techniques for continuous-time ∆Σmodulators with embedded active filtering,” IEEE J. Solid-State Circuits,vol. 49, no. 10, pp. 2187–2198, Oct 2014.

[35] L. Dorrer, F. Kuttner, P. Greco, P. Torta, and T. Hartig, “A 3-mW 74-dBSNR 2-MHz continuous-time delta-sigma ADC with a tracking ADCquantizer in 0.13- µm CMOS,” IEEE J. Solid-State Circuits, vol. 40,no. 12, pp. 2416–2427, Dec 2005.

[36] T. I. Laakso, V. Valimaki, M. Karjalainen, and U. K. Laine, “Splittingthe unit delay [FIR/all pass filters design],” IEEE Signal Process. Mag.,vol. 13, no. 1, pp. 30–60, Jan 1996.

[37] A. Sukumaran and S. Pavan, “Low power design techniques for single-bit audio continuous-time delta sigma ADCs using FIR feedback,” IEEEJ. Solid-State Circuits, vol. 49, no. 11, pp. 2515–2525, Nov 2014.

[38] S. Pavan, “Analysis of chopped integrators, and its application tocontinuous-time delta-sigma modulator design,” IEEE Trans. CircuitsSyst. I, Reg. Papers, vol. 64, no. 8, pp. 1953–1965, Aug 2017.

[39] E. A. M. Klumperink, H. J. Westerveld, and B. Nauta, “N-path filtersand mixer-first receivers: A review,” in 2017 IEEE Custom IntegratedCircuits Conf. (CICC), April 2017, pp. 1–8.

[40] F. Maloberti, Data Converters, 1st ed. Dordrecht, Netherlands: Springer,2007, pp. 114–117.

[41] N. Rakuljic and I. Galton, “Tree-structured DEM DACs with arbitrarynumbers of levels,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57,no. 2, pp. 313–322, Feb 2010.

[42] S. Y. Park, J. Cho, K. Na, and E. Yoon, “Modular 128-channel ∆−∆Σ- analog front-end architecture using spectrum equalization scheme for1024-channel 3-D neural recording microsystems,” IEEE J. Solid-StateCircuits, vol. 53, no. 2, pp. 501–514, Feb 2018.

Nikola Ivanisevic (S'14) received the B.Sc. andM.Sc. degree in electrical and computer engineeringfrom the Faculty of Technical Sciences, Universityof Novi Sad, Novi Sad, Serbia, in 2011 and 2013,respectively,

He is currently working towards the Ph.D. degreeat the KTH Royal Institute of Technology, Stock-holm, Sweden. His doctoral research focuses onpower-efficient analog and mixed-signal circuits forimplantable medical devices.

Saul Rodriguez (M'06) received the B.Sc. degreein electrical engineering from the Army PolytechnicSchool (ESPE), Quito, Ecuador, in 2001, and theM.Sc. degree in system-on-chip design and the Ph.D.degree in electronic and computer systems from theRoyal Institute of Technology (KTH), Stockholm,Sweden, in 2005 and 2009, respectively. His re-search area covers RF CMOS circuit design forwideband front-ends, ultra-low power circuits formedical applications, and graphene-based RF andanalog/mixed-signal circuits.

Ana Rusu (M'92) received the M.Sc. degree inelectronics and telecommunications from the Tech-nical University of Iasi, Iasi, Romania, and the Ph.D.degree in electronics engineering from the TechnicalUniversity of Cluj-Napoca, Cluj-Napoca, Romania,in 1983 and 1998, respectively. Since September2001, she has been with the KTH Royal Instituteof Technology, Stockholm, Sweden, where she isa professor in electronic circuits for integrated sys-tems. Her research interests span from low/ultra-lowpower high performance CMOS circuits and systems

for a wide range of applications to circuits using emerging technologies, suchas graphene and SiC.

journal of la a 14-enob delta-sigma based readout ...1213039/fulltext01.pdf · a 14-enob...

Documents