joseph s. friedman - university of texas at dallasjoseph.friedman/friedmancv.pdfcurriculum vitae –...

Joseph S. Friedman Department of Electrical & Computer Engineering

The University of Texas at Dallas

800 W. Campbell Rd.

Richardson, TX 75080

[email protected] • +1 (972) 883-2191

http://www.utdallas.edu/~joseph.friedman

EDUCATION

Northwestern University, Evanston, IL

Ph.D., Electrical & Computer Engineering June 2014

M.S., Electrical & Computer Engineering June 2010

Dartmouth College, Hanover, NH

B.E. (Thayer School of Engineering) June 2009

A.B., Engineering Sciences June 2009

PROFESSIONAL EXPERIENCE

The University of Texas at Dallas, Richardson, TX Aug. 2016 – present

Assistant Professor of Electrical & Computer Engineering

Affiliated Member of Computer Engineering Program

Director of NeuroSpinCompute Laboratory

United States Air Force Research Laboratory, Rome, NY June – Aug. 2019

Summer Faculty Fellow at Information Institute

Politecnico di Torino, Turin, Italy June – July 2018

Visiting Professor at Department of Electronics and Telecommunications

Université Paris-Sud, Orsay, France July 2014 – June 2016

CNRS Post-Doctoral Research Associate

Supervisor: Damien Querlioz

RWTH Aachen University, Aachen, Germany Nov. 2015

Guest Scientist at Electronic Materials Research Laboratory

Northwestern University, Evanston, IL Sept. 2009 – June 2014

Research/Teaching Assistant

Doctoral Dissertation: Cascaded Magnetoresistive Spintronic Computing

Advisor: Alan V. Sahakian

http://www.utdallas.edu/~joseph.friedman

Curriculum Vitae – August 14, 2020 Joseph S. Friedman

2

Intel Corporation, Santa Clara, CA June–Dec. 2010

Logic Design Automation Intern

Johns Hopkins University Center for Talented Youth, Saratoga Springs, NY June–Aug. 2009

Electrical Engineering Teaching Assistant

Dartmouth College, Hanover, NH Sept. 2008

Electrical Engineering Laboratory Assistant

Columbia University, New York, NY June-Aug. 2008

Electrical Engineering Research Assistant

Tele Atlas (TomTom subsidiary), Lebanon, NH June-Sept. 2007

Software Engineering Intern

BOOK CHAPTER

1. X. Hu, W. H. Brigner, J. S. Friedman, “CNT and SiNW FED Modeling for Ambipolar Logic

Circuit Design,” Functionality-Enhanced Devices: An Alternative to Moore’s Law, P.-E.

Gaillardon (Ed.), The Institution of Engineering and Technology, 2019, ISBN: 978-1-78561-

558-0.

KEYNOTE PRESENTATION

1. J. S. Friedman, “Spintronic Devices for Memory, Logic, and Neuromorphic Computing,”

International Symposium on Quality Electronic Design, Mar. 2020.

JOURNAL PAPERS

1. V. Vyas, L. Jiang-Wei, P. Zhou, X. Hu, J. S. Friedman, “Karnaugh Map Method for

Memristive and Spintronic Asymmetric Basis Logic Functions,” IEEE Transactions on

Computers (accepted).

2. W. H. Brigner, X. Hu, N. Hassan, L. Jiang-Wei, C. H. Bennett, F. Garcia-Sanchez, O. Akinola,

M. Pasquale, M. J. Marinella, J. A. C. Incorvia, J. S. Friedman, “Three Artificial Spintronic

Leaky Integrate-and-Fire Neurons,” SPIN 10:2, 2040003 (2020).

► Featured as Cover Image for Issue

3. C. Cui, O. G. Akinola, N. Hassan, C. H. Bennett, M. J. Marinella, J. S. Friedman, J. A. C.

Incorvia, “Maximized Lateral Inhibition in Paired Magnetic Domain Wall Racetracks for

Neuromorphic Computing,” Nanotechnology 31:29, 294001 (2020).

4. F. Kenarangi, X. Hu, Y. Liu, J. A. C. Incorvia, J. S. Friedman, I. P.-Vaisband, “Exploiting

Dual-Gate Ambipolar CNFETs for Scalable Machine Learning Classification,” Scientific

Reports 10, 5735 (2020).


3

5. N. Hassan, S. P. Lainez-Garcia, F. Garcia-Sanchez, J. S. Friedman, “Toggle Spin-Orbit

Torque MRAM with Perpendicular Magnetic Anisotropy,” IEEE Journal on Exploratory

Solid-State Computational Devices and Circuits 5:2, 166-172 (2019).

6. T. P. Xiao, C. H. Bennett, X. Hu, B. Feinberg, R. Jacobs-Gedrim, S. Agarwal, J. Brunhaver,

J. S. Friedman, J. A. C. Incorvia, M. J. Marinella, “Energy and Performance Benchmarking

of a Domain Wall-Magnetic Tunnel Junction Multibit Adder,” IEEE Journal on Exploratory

Solid-State Computational Devices and Circuits 5:2, 188-196 (2019).

7. M. Chauwin*, X. Hu*, F. Garcia-Sanchez, N. Betrabet, A. Paler, C. Moutafis, J. S. Friedman,

“Skyrmion Logic System for Large-Scale Reversible Computation,” Physical Review Applied

12:6, 064053 (2019).

► Featured as Editors’ Suggestion

8. W. H. Brigner, N. Hassan, L. Jiang-Wei, X. Hu, D. Saha, C. H. Bennett, M. J. Marinella, J. A.

C. Incorvia, F. Garcia-Sanchez, J. S. Friedman, “Shape-Based Magnetic Domain Wall Drift

for an Artificial Spintronic Leaky Integrate-and-Fire Neuron,” IEEE Transactions on Electron

Devices 66:11, 4970-4975 (2019).

9. A. Siemon, R. Drabinski, M. J. Schultis, X. Hu, E. Linn, A. Heittmann, R. Waser, D. Querlioz,

S. Menzel, J. S. Friedman, “Stateful Three-Input Logic with Memristive Switches,” Scientific

Reports 9, 14618 (2019).

10. O. Akinola, X. Hu, C. H. Bennett, M. Marinella, J. S. Friedman, J. A. C. Incorvia, “Three-

Terminal Magnetic Tunnel Junction Synapse Circuits Showing Spike-Timing-Dependent

Plasticity,” Journal of Physics D: Applied Physics 54:49, 49LT01 (2019).

11. W. H. Brigner, X. Hu, N. Hassan, C. H. Bennett, J. A. C. Incorvia, F. Garcia-Sanchez, J. S.

Friedman, “Graded-Anisotropy-Induced Magnetic Domain Wall Drift for an Artificial

Spintronic Leaky Integrate-and-Fire Neuron,” IEEE Journal on Exploratory Solid-State

Computational Devices and Circuits 5:1, 17-24 (2019).

12. X. Hu, A. Timm, W. H. Brigner, J. A. C. Incorvia, J. S. Friedman, “SPICE-Only Model for

Spin-Transfer Torque Domain Wall MTJ Logic,” IEEE Transactions on Electron Devices

66:6, 2817-2821 (2019).

13. A. Peled, X. Hu, O. Amrani, J. S. Friedman, Y. Rosenwaks, “An SRAM Based on the MSET

Device,” IEEE Transactions on Electron Devices 66:3, 1262-1267 (2019).

14. X. Hu*, M. J. Schultis*, M. Kramer, A. Bagla, A. Shetty, J. S. Friedman, “Overhead

Requirements for Stateful Memristor Logic,” IEEE Transactions on Circuits & Systems I 66:1,

263-273 (2019).

15. N. Hassan*, X. Hu*, L. Jiang-Wei, W. H. Brigner, O. G. Akinola, F. Garcia-Sanchez, M.

Pasquale, C. H. Bennett, J. A. C. Incorvia, J. S. Friedman, “Magnetic Domain Wall Neuron

with Lateral Inhibition,” Journal of Applied Physics 124:15, 152127 (2018).

16. D. Vodenicarevic, N. Locatelli, A. Mizrahi, J. S. Friedman, A. F. Vincent, M. Romera, A.

Fukushima, K. Yakushiji, H. Kubota, S. Yuasa, S. Tiwari, J. Grollier, D. Querlioz, “Low-

Energy Truly Random Number Generation with Superparamagnetic Tunnel Junctions for

Unconventional Computing,” Physical Review Applied 8:5, 054045 (2017).

► Featured by nanotechweb.org: “Nanodevice Generates Random Numbers,” Dec. 2017.


4

17. J. S. Friedman, A. Girdhar, R. M. Gelfand, G. Memik, H. Mohseni, A. Taflove, B. W.

Wessels, J.-P. Leburton, A. V. Sahakian, “Cascaded Spintronic Logic with Low-Dimensional

Carbon,” Nature Communications 8, 15635 (2017).

► Featured by the World Economic Forum: “Your Computer Could Be 1000 Times Faster in

the Future, Thanks to Graphene,” Aug. 2017.

► Featured in Design News: “Spintronic Logic Circuit Can Operate 1000x Faster Than

CMOS,” July 2017.

► Featured in Science Daily: “Engineer Unveils New Spin on Future of Transistors with

Novel Design,” June 2017.

18. J. S. Friedman, J. Droulez, P. Bessière, J. Lobo, D. Querlioz, “Approximation Enhancement

for Stochastic Bayesian Inference,” International Journal of Approximate Reasoning 85, 139-

158 (2017).

19. J. S. Friedman, L. E. Calvet, P. Bessière, J. Droulez, D. Querlioz, “Bayesian Inference with

Muller C-Elements,” IEEE Transactions on Circuits & Systems I 63:6, 895-904 (2016).

20. J. S. Friedman, A. Godkin, A. Henning, Y. Vaknin, Y. Rosenwaks, A. V. Sahakian,

“Threshold Logic with Electrostatically Formed Nanowires,” IEEE Transactions on Electron

Devices 63:3, 1388-1391 (2016).

21. J. S. Friedman, E. R. Fadel, B. W. Wessels, D. Querlioz, A. V. Sahakian, “Bilayer Avalanche

Spin-Diode Logic,” AIP Advances 5:11, 117102 (2015).

22. J. S. Friedman, B. W. Wessels, G. Memik, A. V. Sahakian, “Emitter-Coupled Spin-Transistor

Logic: Cascaded Spintronic Computing Beyond 10 GHz,” IEEE Journal on Emerging and

Selected Topics in Circuits and Systems 5:1, 17-27 (2015).

23. J. S. Friedman, J. A. Peters, B. W. Wessels, G. Memik, A. V. Sahakian, “Emitter-Coupled

Spin-Transistor Logic,” Journal of Parallel and Distributed Computing 74:6, 2461-2469

(2014).

24. J. S. Friedman, A. V. Sahakian, “Complementary Magnetic Tunnel Junction Logic,” IEEE

Transactions on Electron Devices 61:4, 1207-1210 (2014).

25. J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, “A Spin-Diode Logic Family,”

IEEE Transactions on Nanotechnology 11:5, 1026-1032 (2012).

ARXIV PREPRINTS

1. X. Hu, B. A. Hill, F. Garcia-Sanchez, J. S. Friedman, “Threshold Logic with Current-Driven

Magnetic Domain Walls,” arXiv:2007.00815 (2020).

2. P. Zhou, N. R. McDonald, A. J. Edwards, L. Loomis, C. D. Thiem, J. S. Friedman, “Reservoir

Computing with Planar Nanomagnet Arrays,” arXiv:2003.10948 (2020).

3. A. Velasquez, C. Bennett, N. Hassan, W. H. Brigner, O. G. Akinola, J. A. C. Incorvia, M.

Marinella, J. S. Friedman, “Unsupervised Competitive Hardware Learning Rule for

Spintronic Clustering Architecture,” arXiv:2003.11120 (2020).

4. X. Hu, A. S. Abraham, J. A. C. Incorvia, J. S. Friedman, “Hybrid Pass Transistor Logic with

Dual-Gate Ambipolar CNTFETs,” arXiv:2002.01932 (2020).


5

5. W. H. Brigner, N. Hassan, X. Hu, C. H. Bennett, F. Garcia-Sanchez, M. J. Marinella, J. A. C.

Incorvia, J. S. Friedman, “CMOS-Free Multilayer Perceptron Enabled by Four-Terminal MTJ

Device,” arXiv:2002.00862 (2020).

CONFERENCE PAPERS & PRESENTATIONS

1. P. Zhou, A. J. Edwards, N. R. McDonald, L. Loomis, C. D. Thiem, J. S. Friedman, “Reservoir

Computing with Planar Nanomagnet Arrays,” Conference on Magnetism and Magnetic

Materials, Nov. 2020.

2. X. Hu, B. A. Hill, F. Garcia-Sanchez, J. S. Friedman, “Threshold Logic with Current-Driven

Magnetic Domain Walls,” Conference on Magnetism and Magnetic Materials, Nov. 2020.

3. N. Hassan, W. H. Brigner, C. H. Bennett, A. Velasquez, X. Hu, O. G. Akinola, F. Garcia-

Sanchez, M. J. Marinella, J. A. C. Incorvia, J. S. Friedman, “Purely Spintronic Multilayer

Perceptron Enabled by Four-Terminal Domain Wall-Magnetic Tunnel Junction Neuron,”

Conference on Magnetism and Magnetic Materials, Nov. 2020.

4. W. H. Brigner, N. Hassan, X. Hu, C. H. Bennett, F. Garcia-Sanchez, M. J. Marinella, J. A. C.

Incorvia, J. S. Friedman, “Linear Intrinsic Leaking in a Domain-Wall Magnetic Tunnel

Junction Neuron,” Conference on Magnetism and Magnetic Materials, Nov. 2020.

5. J. A. C. Incorvia, J. S. Friedman, M. J. Marinella, O. G. Akinola, C. Cui, N. Hassan, C. H.

Bennett, X. Hu, L. Jiang-Wei, W. H. Brigner, F. Garcia-Sanchez, M. Pasquale, “Modeling

Biological Behavior in Domain Wall-Magnetic Tunnel Junction Artificial Neurons and

Synapses for Energy-Efficient Neuromorphic Computing,” Conference on Magnetism and

Magnetic Materials, Nov. 2020 (invited).

6. O. G. Akinola, B. Mendawar, C. H. Bennett, X. Hu, J. S. Friedman, M. J. Marinella, J. A. C.

Incorvia, “Online Training of Spiking Neural Networks Using Domain Wall Magnetic Tunnel

Junction Synapses,” Conference on Magnetism and Magnetic Materials, Nov. 2020.


Incorvia, “Maximized Lateral Inhibition in Paired Magnetic Domain Wall Racetracks for

Neuromorphic Computing,” Conference on Magnetism and Magnetic Materials, Nov. 2020.

8. N. Hassan, W. H. Brigner, X. Hu, O. G. Akinola, C. H. Bennett, M. Marinella, F. Garcia-

Sanchez, J. A. C. Incorvia, J. S. Friedman, “CMOS-Free Magnetic Domain Wall Leaky

Integrate-and-Fire Neurons with Intrinsic Lateral Inhibition,” IEEE International Symposium

on Circuits & Systems, Oct. 2020 (invited).

9. X. Hu, A. J. Edwards, T. P. Xiao, C. H. Bennett, J. A. C. Incorvia, M. J. Marinella, J. S.

Friedman, “Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel

Junction Logic,” IEEE International Symposium on Circuits & Systems, Oct. 2020.

10. C. H. Bennett, T. P. Xiao, C. Cui, N. Hassan, O. Akinola, J. A. C. Incorvia, A. Velasquez, J.

S. Friedman, M. J. Marinella, “Plasticity-Enhanced Domain-Wall MTJ Neural Networks for

Energy-Efficient Online Learning,” IEEE International Symposium on Circuits & Systems,

Oct. 2020 (invited).

11. J. A. C. Incorvia, J. S. Friedman, M. J. Marinella, O. G. Akinola, C. Cui, N. Hassan, C.

Bennett, X. Hu, L. Jiang-Wei, W. H. Brigner, F. Garcia-Sanchez, M. Pasquale, “Capturing

Biological Behavior in Nanomagnetic Artificial Neurons and Synapses for Energy-Efficient


6

Neuromorphic Computing,” Pacific Rim Meeting on Electrochemical & Solid-State Science,

Oct. 2020 (invited).

12. N. Hassan, F. Garcia-Sanchez, S. P. Lainez-Garcia, P. Khalili Amiri, J. S. Friedman, “Field-

Free Toggle Spin-Orbit Torque MRAM with Perpendicular Magnetic Anisotropy,” The

Magnetic Recording Conference, Aug. 2020.

13. A. J. Edwards, P. Zhou, N. R. McDonald, L. Loomis, C. D. Thiem, J. S. Friedman, “Reservoir

Computing with Planar Nanomagnet Arrays,” International Conference on Neuromorphic

Systems, July 2020.

14. N. Hassan, S. P. Lainez-Garcia, F. Garcia-Sanchez, J. S. Friedman, “Spin-Orbit Torque

Driven Toggle Mode MRAM with Perpendicular Magnetic Anisotropy,” SPIE Spintronics,

Aug. 2020 (invited).


Incorvia, “Lateral Inhibition in Magnetic Domain Wall Racetrack Arrays for Neuromorphic

Computing,” SPIE Spintronics, Aug. 2020 (invited).

16. T. P. Xiao, C. H. Bennett, X. Hu, B. Feinberg, R. Jacobs-Gedrim, S. Agarwal, J. S. Brunhaver,

J. S. Friedman, J. A. C. Incorvia, M. J. Marinella, “Energy-Efficient Stateful Logic with

Magnetic Domain Walls,” SPIE Spintronics, Aug. 2020 (invited).

17. P. Zhou, N. R. McDonald, A. J. Edwards, L. Loomis, C. D. Thiem, J. S. Friedman, “Reservoir

Computing with Planar Nanomagnet Arrays,” Government Microcircuit Applications &

Critical Technology Conference, Mar. 2020.

18. W. H. Brigner, N. Hassan, X. Hu, C. Bennett, M. Marinella, F. Garcia-Sanchez, J. A. C.

Incorvia, J. S. Friedman, “CMOS-Free Multilayer Perceptron Enabled by Four-Terminal MTJ

Device,” Government Microcircuit Applications & Critical Technology Conference, Mar.

2020.

19. A. Velasquez, C. Bennett, N. Hassan, W. H. Brigner, O. G. Akinola, J. A. C. Incorvia, M.

Marinella, J. S. Friedman, “Unsupervised Competitive Hardware Learning Rule for

Spintronic Clustering Architecture,” Government Microcircuit Applications & Critical

Technology Conference, Mar. 2020.

20. N. Hassan, S. P. Lainez-Garcia, F. Garcia-Sanchez, J. S. Friedman, “Toggle Mode Spin-Orbit

Torque Driven Perpendicular Magnetic Anisotropy MRAM,” Conference on Magnetism and

Magnetic Materials, Nov. 2019.

21. W. H. Brigner, N. Hassan, X. Hu, L. Jiang-Wei, D. Saha, C. H. Bennett, M. J. Marinella, F.

Garcia-Sanchez, J. A. C. Incorvia, J. S. Friedman, “Magnetic Domain Wall Neurons with

Intrinsic Leaking,” Conference on Magnetism and Magnetic Materials, Nov. 2019.

22. C. Cui, N. Hassan, C. H. Bennett, M. J. Marinella, J. S. Friedman, J. A. C. Incorvia,

“Optimized Lateral Inhibition in Magnetic Domain Wall Tracks for Neuromorphic

Computing,” Conference on Magnetism and Magnetic Materials, Nov. 2019.

23. X. Hu, M. Chauwin, F. Garcia-Sanchez, N. Betrabet, C. Moutafis, J. S. Friedman, “Cascaded

Skyrmion Logic System Inspired by Conservative Logic,” SPIE Spintronics, Aug. 2019

(invited).

24. N. Hassan, X. Hu, L. Jiang-Wei, W. H. Brigner, O. G. Akinola, F. Garcia-Sanchez, M.

Pasquale, C. H. Bennett, J. A. C. Incorvia, J. S. Friedman, “Magnetic Domain Wall Neuron

with Intrinsic Leaking and Lateral Inhibition Capability,” SPIE Spintronics, Aug. 2019

(invited).


7

25. O. G. Akinola, M. Alamdar, N. Hassan, X. Hu, T. Leonard, J. S. Friedman, J. A. C. Incorvia,

“Three-Terminal Magnetic Tunnel Junctions for In-Memory and Neuromorphic Computing,”

SPIE Spintronics, Aug. 2019 (invited).

26. C. H. Bennett, J. A. C. Incorvia, X. Hu, N. Hassan, J. S. Friedman, M. M. Marinella, “Semi-

Supervised Learning and Inference in Domain-Wall Magnetic Tunnel Junction (DW-MTJ)

neural Networks,” SPIE Spintronics, Aug. 2019 (invited).

27. X. Hu*, M. J. Schultis*, M. Kramer, A. Bagla, A. Shetty, J. S. Friedman, “Overhead

Requirements for Stateful Memristor Logic,” IEEE International Symposium on Circuits &

Systems, May 2019.

28. J. S. Friedman, “Cascaded All-Carbon Spin Logic based on Graphene Nanoribbon

Magnetoresistance,” Joint IEEE International Magnetics Conference & Conference on

Magnetism and Magnetic Materials, Jan. 2019.

29. X. Hu, M. Chauwin, F. Garcia-Sanchez, N. Betrabet, C. Moutafis, J. S. Friedman, “Cascaded

Skyrmion Logic System Inspired by Conservative Logic,” Joint IEEE International Magnetics

Conference & Conference on Magnetism and Magnetic Materials, Jan. 2019.

30. N. Hassan, X. Hu, L. Jiang-Wei, W. H. Brigner, O. G. Akinola, F. Garcia-Sanchez, M.

Pasquale, C. H. Bennett, J. A. C. Incorvia, J. S. Friedman, “Neuromorphic Computing with

Domain Wall-Based Three-Terminal Magnetic Tunnel Junctions: Neurons,” Joint IEEE

International Magnetics Conference & Conference on Magnetism and Magnetic Materials,

Jan. 2019.

31. O. Akinola, E. J. Kim, N. Hassan, J. S. Friedman, J. A. C. Incorvia, “Neuromorphic

Computing with Domain Wall-Based Three-Terminal Magnetic Tunnel Junctions: Synapse,”

Joint IEEE International Magnetics Conference & Conference on Magnetism and Magnetic

Materials, Jan. 2019.

32. J. S. Friedman, “Beyond-CMOS Computing with Emerging Technologies,” Raytheon

Mechanical, Materials and Structures Symposium, Aug. 2018 (invited).

33. J. S. Friedman, “Cascaded Spintronic Logic Gates based on Graphene Nanoribbon

Magnetoresistance: All-Carbon Spin Logic,” SPIE Spintronics, Aug. 2018 (invited).

34. J. S. Friedman, A. Girdhar, S. K. Heinrich-Barna, W. A. Chalifoux, J.-P. Leburton, A. V.

Sahakian, “2D Carbon for Cascaded Spintronic Logic,” International Conference on

Superlattices, Nanostructures and Nanodevices, July 2018.

35. V. Vyas, J. S. Friedman, “Sequential Circuit Design with Bilayer Avalanche Spin Diode

Logic,” IEEE/ACM International Symposium on Nanoscale Architectures, July 2018.

36. S. K. Heinrich-Barna, J.-P. Leburton, J. S. Friedman, “All-Carbon Spin Logic Sensor for

RRAM Arrays,” IEEE International Symposium on Circuits & Systems, May 2018 (invited).

37. D. Vodenicarevic, N. Locatelli, A. Mizrahi, T. Hirtzlin, J. S. Friedman, J. Grollier, D.

Querlioz, “Circuit-Level Evaluation of the Generation of Truly Random Bits with

Superparamagnetic Tunnel Junctions,” IEEE International Symposium on Circuits & Systems,

May 2018 (invited).

38. D. Querlioz, A. F. Vincent, A. Mizrahi, D. Vodenicarevic, J. S. Friedman, N. Locatelli, J.

Grollier, “Neuromorphic Computing with Stochastic Spintronic Devices,” Conference on

Magnetism and Magnetic Materials, Nov. 2017 (invited).


8

39. J. S. Friedman, “Spintronic Logic: From Switching Devices to Computing Systems,” SPIE

Spintronics, Aug. 2017 (invited).

40. D. Querlioz, A. F. Vincent, A. Mizrahi, D. Vodenicarevic, N. Locatelli, J. S. Friedman, J.-O.

Klein, J. Grollier, “Neuromorphic Computing with Stochastic Spintronic Devices,” SPIE

Spintronics, Aug. 2017 (invited).

41. X. Hu, J. S. Friedman, “Transient Model with Interchangeability for Dual-Gate Ambipolar

CNTFET Logic Design,” IEEE/ACM International Symposium on Nanoscale Architectures,

July 2017.

42. J. S. Friedman, “Spintronic Computing System Integration,” Seiden Frontiers in Engineering

and Science Workshop on Beyond-CMOS: From Devices to Systems, June 2017 (invited).

43. X. Hu, J. S. Friedman, “Closed-Form Model for Dual-Gate Ambipolar CNTFET Circuit

Design,” IEEE International Symposium on Circuits & Systems, May 2017.

44. J. S. Friedman, “CMAT Non-Volatile Spintronic Computing: Complementary MTJ Logic,”

SPIE Spintronics, Aug. 2016 (invited).

45. L. E. Calvet, J. S. Friedman, D. Querlioz, P. Bessière, J. Droulez, “Sleep Stage Classification

with Stochastic Bayesian Inference,” IEEE/ACM International Symposium on Nanoscale

Architectures, July 2016.

46. J. S. Friedman, L. E. Calvet, P. Bessière, J. Droulez, D. Querlioz, “Bayesian Inference with

Muller C-Elements,” IEEE International Symposium on Circuits & Systems, May 2016.

47. D. Querlioz, A. F. Vincent, A. Mizrahi, N. Locatelli, J. S. Friedman, D. Vodenicarevic,

“Computational Techniques for the Design of Bioinspired Systems that Employ Nanodevices,”

International Workshop on Computational Electronics, Sep. 2015 (invited).

48. M. G. A. Martins, F. S. Marranghello, J. S. Friedman, A. V. Sahakian, R. P. Ribas, A. I. Reis,

“Enhanced Spin-Diode Synthesis using Logic Sharing,” EUROMICRO Digital System Design

Conference, Aug. 2015.

49. J. S. Friedman, D. Querlioz, A. V. Sahakian, “Magnetoresistance Implications for

Complementary Magnetic Tunnel Junction Logic (CMAT),” IEEE/ACM International

Symposium on Nanoscale Architectures, July 2015.


“Automated Synthesis Approaches for Digital Integrated Design of Spin-Diode Circuits,”

International Workshop on Logic & Synthesis, June 2015.

51. N. Locatelli, A. F. Vincent, A. Mizrahi, J. S. Friedman, D. Vodenicarevic, J.-V. Kim, J.-O.

Klein, W. Zhao, J. Grollier, D. Querlioz, “Spintronic Devices as Key Elements for Energy-

Efficient Neuroinspired Architectures,” Design, Automation & Test in Europe, March 2015

(invited).

52. J. S. Friedman, B. W. Wessels, D. Querlioz, A. V. Sahakian, “High-Performance Computing

based on Spin-Diode Logic,” SPIE Spintronics, Aug. 2014 (invited).


“Spin Diode Network Synthesis using Functional Composition,” Symposium on Integrated

Circuits and Systems Design, Sep. 2013.

54. J. S. Friedman, B. W. Wessels, A. V. Sahakian, “High-Performance Spintronic Computing

with Magnetoresistive Semiconductor Heterojunctions,” SPIE Spintronics, Aug. 2013

(invited).


9

55. J. S. Friedman, “Cascaded Magnetoresistive Spintronics: A Pathway for Computing Beyond

10 GHz,” CMOS Emerging Technologies Research Symposium, July 2013 (invited).

56. J. S. Friedman, Y. I. Ismail, G. Memik, A. V. Sahakian, B. W. Wessels, “Emitter-Coupled

Spin-Transistor Logic,” IEEE/ACM International Symposium on Nanoscale Architectures,

July 2012.

► Featured in Science Daily: “Toward Achieving One Million Times Increase in Computing

Efficiency,” July 2012.

57. J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, “InMnAs Magnetoresistive Spin-

Diode Logic,” ACM Great Lakes Symposium on VLSI, May 2012.

PATENTS

1. J. S. Friedman, M. L. Geier, M. C. Hersam, A. V. Sahakian, “System and Method for

Complimentary VT-Drop Ambipolar Carbon Nanotube Logic,” U.S. Patent #10,594,319

(2020).

2. J. S. Friedman, A. V. Sahakian, A. Godkin, A. Henning, Y. Rosenwaks, “System and Method

for Threshold Logic with Electrostatically Formed Nanowire Transistors,” U.S. Patent

#10,002,964 (2018).

3. J. S. Friedman, G. Memik, B. W. Wessels, “Emitter-Coupled Spin-Transistor Logic,” U.S.

Patent #9,780,791 (2017).

4. J. S. Friedman, A. V. Sahakian, A. Godkin, A. Henning, Y. Rosenwaks, “System and Method

for Threshold Logic with Electrostatically Formed Nanowire Transistors,” U.S. Patent

#9,728,636 (2017).

5. J. S. Friedman, A.V. Sahakian, “Method for Computing with Complementary Networks of

Magnetic Tunnel Junctions,” U.S. Patent #9,711,200 (2017).

6. J. S. Friedman, A.V. Sahakian, “Magnetic Tunnel Junctions with Control Wire,” U.S. Patent

#9,299,917 (2016).

7. J. S. Friedman, G. Memik, B. W. Wessels, “Emitter-Coupled Spin-Transistor Logic,” U.S.

Patent #9,270,277 (2016).

8. J. S. Friedman, B. W. Wessels, A. V. Sahakian, “System and Method for Spin Logic,” U.S.

Patent #9,186,103 (2015).

9. J. S. Friedman, N. Rangaraju, Y. I. Ismail, B. W. Wessels, “Logic Cells Based on Spin Diode

and Applications of Same,” U.S. Patent #8,912,821 (2014).

FUNDED AWARDS

1. National Science Foundation: Industry-University Cooperative Research Center: Center for

Hardware and Embedded Systems Security and Trust, “Stochasticity, Polymorphism and Non-

Volatility: Three Pillars of Security and Trust Intrinsic to Emerging Technologies,” $50,000,

June 2020 – May 2021. Co-PI: Yiorgos Makris.

2. United States Air Force Research Laboratory – Griffiss Institute, “Reservoir Computing with

Nanomagnets and Magnetic Skyrmions,” $10,000.00, Sep. 2019 – Dec. 2019.


10

3. Texas Instruments, “Neural Network Recognition & On-Chip Online Learning with STT-

MRAM,” Semiconductor Research Corporation/Texas Analog Center of Excellence Task

#2810.030, $150,000.00, Aug. 2019 – July 2022.

4. National Science Foundation: Computer and Information Science and Engineering: Computing

and Communication Foundations, “FET: Small: Collaborative Research: Integrated Spintronic

Synapses and Neurons for Neuromorphic Computing Circuits - I(SNC)^2,” Award #1910800,

$207,118.00, June 2019 – May 2022.

► Includes $16,000.00 Research Experience for Undergraduates Supplement

5. United States Air Force Research Laboratory: Summer Faculty Fellowship Program,

“Neuromorphic Computing Circuits with Non-Volatile Spintronic Devices,” $12,000.00, June

2019 – Aug. 2019.

6. The University of Texas at Dallas: National Research University Fund Seed Grant Initiative:

Workshop Grant, “Texas Symposium on Computing with Emerging Technologies (ComET),”

$7,000.00, April 2019 – March 2021.

7. Italy Young Investigator Training Program, “Bio-Inspired and Nanocomputing System

Architecture Integration with Emerging Technologies,” €4,000.00, June 2018 – July 2018.

8. European Cooperation in Science & Technology: COST IC1401: MemoCIS: Short Term

Scientific Mission, “Logic Cascading Techniques for Complementary Resistive Switches,”

€1,400.00, Nov. 2015.

9. Northwestern University: Walter P. Murphy Fellowship, $10,260.00, Sep. 2009 – Mar. 2010.

TUTORIAL COURSE ON LOGICAL COMPUTING

Spintronic & Beyond-CMOS Computing

Numerous nanodevices have been developed with exotic electronic and

spintronic characteristics. However, it is not obvious how to best connect these

devices to each other in cascaded systems that exploit their unique behavior. In this

six-lecture tutorial, I describe and analyze the wide range of techniques for

cascading logic devices. In addition to the electronic cascading mechanisms of

conventional computers, this course evaluates recently proposed integration

techniques for new nanocomputing systems. I particularly emphasize spintronics,

in which the rich physics enable a large variety of cascading mechanisms. In

contrast to conventional presentations that follow the vertical integration of a

single device from the physics to the full system performance, this course provides

a cross-section of cascading techniques for numerous devices. The advantages and

drawbacks of the techniques are evaluated to provide inspiration for innovative

circuit designs based on novel devices.

United States Air Force Research Lab – Information, Rome, NY June 20 – July 10, 2019

Istituto Nazionale di Ricerca Metrologica, Turin, Italy July 3-4, 2018

Politecnico di Torino, Turin, Italy June 20-29, 2018

Technion-Israel Institute of Technology, Haifa, Israel June 8, 2017

Université Paris-Sud, Orsay, France Sep. 21, 2016


11

University of Rochester, Rochester, NY Nov. 30 – Dec. 1, 2015

RWTH Aachen University, Aachen, Germany Nov. 4–6, 2015

École Polytechnique, Palaiseau, France Oct. 19, 2015

TUTORIAL COURSE ON NEUROMORPHIC COMPUTING

Neuromorphic Computing with Spintronic & Emerging Technologies

Neuromorphic computing promises exceptional capabilities for artificial

intelligence through highly-efficient devices and circuits that mimic the structure

and functionality of the human brain. Whereas conventional CMOS transistors

provide only volatile switching, the non-volatile analog behavior provided by

emerging non-volatile memory technologies are promising as potential hardware

components of a neuromorphic computing system. In particular, memristors and

spintronic devices (in which electron spin is manipulated in addition to electron

charge) have received significant attention due to their biomimetic characteristics.

In this three-lecture tutorial, I describe and analyze the wide range of techniques

to emulate neurobiological behavior with spintronic and emerging technologies

within a neuromorphic computing system. In contrast to conventional presentations

that follow the vertical integration of a single device from the physics to the full

system performance, this course evaluates the effectiveness through which the

various neuromorphic computing paradigms leverage the behavior of emerging

technologies within artificial neural networks.

United States Air Force Research Lab – Information, Rome, NY July 30 – August 1, 2019

OTHER PRESENTATIONS

1. J. S. Friedman, “Analog & Toggle Switching of Magnetic Domains for Memory &

Neuromorphic Computing,” Universidad Nacional Autónoma de México, Mexico City,

Mexico, Oct. 2019.

2. J. S. Friedman, “Beyond-CMOS Computing with Low-Dimensional and Hysteretic

Materials,” Centro de Investigación y de Estudios Avanzados del Instituto Politécnico

Nacional, Mexico City, Mexico, Oct. 2019.

3. J. S. Friedman, “Spintronic & Neuromorphic Computing Systems,” Sandia National

Laboratories, Albuquerque, NM, Aug. 2019.

4. J. S. Friedman, “Spintronic Neuromorphic Computing,” United States Air Force Research

Laboratory – Information, Rome, NY, July 2019.

5. N. Hassan, S. P. Lainez Garcia, F. Garcia-Sanchez, J. S. Friedman, “Toggle Mode Spin-Orbit

Torque MRAM with Perpendicular Magnetic Anisotropy,” Texas Symposium on Computing

with Emerging Technologies, The University of Texas at Dallas, Richardson, TX, May 2019.

6. W. H. Brigner, N. Hassan, X. Hu, L. Jiang-Wei, O. Akinola, C. H. Bennett, F. Garcia-Sanchez,

J. A. C. Incorvia, J. S. Friedman, “Magnetic Domain Wall Neuron with Intrinsic Leaking and


12

Lateral Inhibition Capability,” Texas Symposium on Computing with Emerging Technologies,

The University of Texas at Dallas, Richardson, TX, May 2019.

7. X. Hu, M. J. Schultis, M. Kramer, A. Bagla, A. Shetty, J. S. Friedman, “Overhead

Requirements for Stateful Memristor Logic,” Texas Symposium on Computing with Emerging

Technologies, The University of Texas at Dallas, Richardson, TX, May 2019.

8. J. S. Friedman, “Spintronic Logical & Neuromorphic Computing,” IEEE Circuits & System

Society – Dallas Chapter, The University of Texas at Dallas, Richardson, TX, Feb. 2019.

9. J. S. Friedman, “Graphene Nanoribbons and Magnetic Skyrmions for Spintronic Computing,”

Universidad Nacional Autónoma de México, Mexico City, Mexico, Sep. 2018.

10. X. Hu, W. H. Brigner, J. S. Friedman, “Ambipolar Transistor Models for Logic Circuit

Design,” Texas Symposium on Computing with Emerging Technologies, The University of

Texas at Dallas, Richardson, TX, Apr. 2018.

11. S. K. Heinrich-Barna, J.-P. Leburton, J. S. Friedman, “All-Carbon Spin Logic Sensor for

RRAM Arrays,” Texas Symposium on Computing with Emerging Technologies, The

University of Texas at Dallas, Richardson, TX, Apr. 2018.

12. N. Hassan, J. S. Friedman, “Challenges and Future Prospects of Spin-Orbit Torque for Non-

Volatile Memory Technology,” Texas Symposium on Computing with Emerging Technologies,

The University of Texas at Dallas, Richardson, TX, Apr. 2018.

13. N. Betrabet, X. Hu, M. Chauwin, F. Garcia-Sanchez, J. S. Friedman, “Skyrmion Track and

Skyrmion-Hall Effect Dynamics for Logic Circuit Design,” Texas Symposium on Computing

with Emerging Technologies, The University of Texas at Dallas, Richardson, TX, Apr. 2018.

14. V. Vyas, L. Jiang-Wei, X. Hu, J. S. Friedman, “A Novel Minimization Technique for

Asymmetric Logic Functions,” Texas Symposium on Computing with Emerging Technologies,

The University of Texas at Dallas, Richardson, TX, Apr. 2018.

15. J. S. Friedman, “Spintronic & Bio-Inspired Computing Systems,” National Institute of

Standards and Technology, Gaithersburg, MD, Apr. 2018.

16. A. Timm, M. Shihab, V. Sreenivasa, S. Rehman, J. S. Friedman, “A Framework for SPICE

Modeling of Domain-Wall Logic Devices,” Texas Symposium on Computing with Emerging

Technologies, The University of Texas at Dallas, Richardson, TX, Apr. 2017.

17. X. Hu, J. S. Friedman, “Closed-Form Model for Dual-Gate Ambipolar CNTFET Circuit

Design,” Texas Symposium on Computing with Emerging Technologies, The University of

Texas at Dallas, Richardson, TX, Apr. 2017.

18. M. J. Schultis, X. Hu, M. Kramer, A. Bagla, A. Shetty, M. Rathna, Y. Liu, P. X. Francis, J. S.

Friedman, “An Evaluation of CMOS Circuitry Requirements for Resistive Switch

(Memristor) Logic,” Texas Symposium on Computing with Emerging Technologies, The

University of Texas at Dallas, Richardson, TX, Apr. 2017.

19. V. Vyas, A. Pai, M. Joslin, H. Trinh, J. S. Friedman, “Effects of Temperature and Channel

Material on All-Spin Logic Performance,” Texas Symposium on Computing with Emerging

Technologies, The University of Texas at Dallas, Richardson, TX, Apr. 2017.

20. A. Bagla, V. Vyas, J. S. Friedman, “Logic Synthesis Techniques for Emerging

Technologies,” Texas Symposium on Computing with Emerging Technologies, The University

of Texas at Dallas, Richardson, TX, Apr. 2017.


13

21. J. S. Friedman, “Mumax Tutorial: Magnetic Integrated Circuit Simulation,” Université Paris-

Sud, Orsay, France, Sep. 2016.

22. J. S. Friedman, “Spintronic Logic,” Institut d’Electronique Fondamentale Nanotechnology

Day, Université Paris-Sud, Orsay, France, July 2015.

23. J. S. Friedman, “Spintronic Logic,” Université Paris-Sud, Orsay, France, Sep. 2014.

24. J. S. Friedman, “Beyond-CMOS Circuit Design and Spin-Diode Logic,” UIUC Coordinated

Science Laboratory Student Conference, University of Illinois at Urbana-Champaign,

Champaign, IL, Feb. 2013.

SERVICE & RECOGNITION

Fulbright Postdoctoral Research Fellowship (awarded; chose to decline)

Editorial Board Member of the Microelectronics Journal

Technical Program Chair of the 2018 IEEE Dallas Circuits & Systems Conference (DCAS)

Publicity Chair of the 2019 IEEE/ACM International Symposium on Nanoscale Architectures

(NANOARCH)

Publicity Chair of the 2020 IFIP/IEEE International Conference on Very Large Scale Integration

(VLSI-SoC)

Founder and Chairperson of the Texas Symposium on Computing with Emerging Technologies

(ComET)

2017, 2018, 2019

Technical Program Committee Member

Design Automation Conference (DAC)

o 2017, 2018, 2019, 2020

o 2020 Track Chair

o 2020 Late Breaking Results Committee

o 2019 Track Co-Chair

SPIE Spintronics

o 2017, 2018, 2019, 2020

IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

o 2017, 2018, 2019

ACM Great Lakes Symposium on VLSI (GLSVSI)

o 2017, 2018, 2019, 2020

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

o 2018, 2019, 2020

Design, Automation and Test in Europe Conference (DATE)

o 2020, 2021

IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

o 2020

Review Committee Member of the IEEE International Symposium on Circuits & Systems

(ISCAS)


14

o 2017, 2018, 2019, 2020

Technical Committee Member of the IEEE Circuits & Systems Society Nanoelectronics and

Gigascale Systems Technical Committee

Vice Chair of the Dallas Chapter of the IEEE Electron Devices Society

Special Issue Editor of SPIN: Spintronics for In-Memory Processing

Special Session Organizer at

o ISCAS 2018: Spintronic Memory Circuits

o ISCAS 2020: Spintronic Neuromorphic Computing

Best Poster Award at 2019 Semiconductor Research Corporation/Texas Analog Center of

Excellence (SRC/TxACE) Annual Symposium

Session Chair

IEEE International Symposium on Circuits & Systems (ISCAS)

o 2017, 2018, 2019, 2020

SPIE Spintronics

o 2017, 2018, 2019, 2020

Conference on Magnetism and Magnetic Materials (MMM)

o 2019

International Symposium on Quality Electronic Design (ISQED)

o 2020

Review Committee Member for IEEE Transactions on Parallel & Distributed Systems Special

Section on Non-von Neumann Computing

Journal Reviewer

ACM Transactions on Design Automation of Electronic Systems

Advanced Electronic Materials

AIP Advances

Applied Surface Science

Electronics Letters

Entropy

IEEE Access

IEEE Design & Test

IEEE Electron Device Letters

IEEE Journal of Exploratory Solid-State Computational Devices and Circuits

IEEE Transactions on Circuits & Systems I

IEEE Transactions on Circuits & Systems II

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Electron Devices

IEEE Transactions on Emerging Topics in Computing

IEEE Transactions on Fuzzy Systems

IEEE Transactions on Magnetics

IEEE Transactions on Nanotechnology


15

IEEE Transactions on Neural Networks and Learning Systems

IEEE Transactions on Nuclear Science

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IET Circuits, Devices & Systems

Journal of Applied Physics

Journal of Computational Electronics

Journal of Physics D: Applied Physics

Microelectronics Journal

Nanoscale

Proceedings of the IEEE

Proposal Reviewer

French National Research Agency (ANR)

National Science Foundation

National Science Foundation of China

Israel Science Foundation

ConTex (joint initiative of The University of Texas System and Mexico’s National Council

of Science and Technology (CONACYT))

University of Texas at Dallas National Research University Fund Seed Grant Program

RESEARCH GROUP ALUMNI

1. Adrienne M. Bull, The University of Texas at Dallas

B.S. in Electrical Engineering, 2020

2. Lucian Jiang-Wei, The University of Texas at Dallas

B.S. in Computer Science, 2019

3. Jennifer M. Ward, The University of Texas at Dallas

B.S. in Computer Engineering, 2019

4. Abel Thayil, École Polytechnique

M1 Internship (4.5 months), 2018

Thesis: Spintronic Devices for Neuromorphic Computing

► Awarded École Polytechnique’s Prix du Stage de Recherche

5. Vaibhav Vyas, The University of Texas at Dallas (now at John Deere Intelligent Solutions)

M.S. in Electrical Engineering, 2018

Thesis: Novel Logic Synthesis Techniques for Asymmetric Logic Functions based on

Spintronic and Memristive Devices

6. Michael J. Schultis, The University of Texas at Dallas (now at Texas Instruments)

M.S. in Electrical Engineering, 2018

7. Maverick Chauwin, École Polytechnique (now M.S. student at National U. Singapore)


16

M1 Internship (four months), 2017

Thesis: Skyrmion Logic Circuit Design

► Awarded École Polytechnique’s Grand Prix du Stage de Recherche

8. Jason Hyndman, The University of Texas at Dallas (now at Naval Surface Warfare Center

Panama City Division)

B.S. in Computer Engineering, 2017

9. Eric R. Fadel, École Polytechnique (now MIT Ph.D. student)

M1 Internship (four months), 2015

Thesis: Magnetic Domain Wall Oscillator and Logic

► Awarded École Polytechnique’s Prix du Stage de Recherche

CURRENT STUDENT MENTORING

1. Alexandru Paler, Google Munich, Johannes Kepler University Linz, and Transilvania

University

Fulbright Visiting Post-Doctoral Scholar

2. Xuan Hu, The University of Texas at Dallas

Ph.D. Candidate

3. Naimul Hassan, The University of Texas at Dallas

Ph.D. Candidate

4. Stephen Heinrich-Barna, The University of Texas at Dallas

Ph.D. Candidate

5. Peng Zhou, The University of Texas at Dallas

Ph.D. Candidate

6. Alexander J. Edwards, The University of Texas at Dallas

Ph.D. Candidate

7. Wesley H. Brigner, The University of Texas at Dallas

Ph.D. Candidate

B.S. in Electrical Engineering, 2020

► Supervised undergraduate research

8. Laura Deremo, The University of Texas at Dallas

M.S. Candidate

9. Brighton A. Hill, The University of Texas at Dallas

M.S. Candidate


17

10. Neilesh Betrabet, The University of Texas at Dallas

B.S. Candidate

11. Amy S. Abraham, The University of Texas at Dallas

B.S. Candidate

12. Susana P. Lainez Garcia, The University of Texas at Dallas

B.S. Candidate

13. Chandler M. Linseisen, The University of Texas at Dallas

B.S. Candidate

14. Joanna M. Martin, The University of Texas at Dallas

B.S. Candidate

15. Pranav O. Mathews, The University of Texas at Dallas

B.S. Candidate

16. Mustafa M. Sadriwala, The University of Texas at Dallas

B.S. Candidate

17. Abbas A. Zaki, The University of Texas at Dallas

B.S. Candidate

18. Aishani De Sirkar, The University of Texas at Dallas

B.S. Candidate

19. Christian B. Duffee, The University of Texas at Dallas

B.S. Candidate

20. Kristi Doleh, The University of Texas at Dallas

B.S. Candidate

21. Rhea Iyer, The University of Texas at Dallas

B.S. Candidate

22. Karthi Lakshmana Doss, The University of Texas at Dallas

B.S. Candidate

23. Nivetha Narayanan, The University of Texas at Dallas

B.S. Candidate

24. Samiha Sharif, The University of Texas at Dallas

B.S. Candidate

25. Julie A. Smith, The University of Texas at Dallas


18

B.S. Candidate

26. Evan E. Dobbs, The University of Texas at Dallas

B.S. Candidate

27. Kevin Y. Shi, The University of Texas at Dallas

B.S. Candidate

28. Varun Venkat, The University of Texas at Dallas

B.S. Candidate

29. Ben W. Walker, The University of Texas at Dallas

B.S. Candidate

TEACHING EXPERIENCE

The University of Texas at Dallas, Richardson, TX

EECT 7v88 – Special Topics in Circuits & Systems: Beyond-CMOS Computing

Spring 2017, Spring 2019

EECT 6325 – VLSI Design

Spring 2018, Spring 2019, Spring 2020

EE/CE 3301 – Electrical Network Analysis

Fall 2019, Spring 2020, Fall 2020

EE/CE 3101 – Electrical Network Analysis Laboratory

Fall 2017, Fall 2018

Northwestern University, Evanston, IL

EECS 391 – VLSI Systems Design

Winter 2013

joseph s. friedman - university of texas at dallasjoseph.friedman/friedmancv.pdfcurriculum vitae –...

Documents