issues in timing
DESCRIPTION
ISSUES IN TIMING. The Clock Skew Problem. Delay of Clock Wire. Constraints on Skew. Clock Constraints in Edge-Triggered Logic. Positive and Negative Skew. Clock Skew in Master-Slave Two Phase Design. Clock Skew in 2-phase design. How to counter Clock Skew?. Clock Distribution. - PowerPoint PPT PresentationTRANSCRIPT
Digital Integrated Circuits © Prentice Hall 1995Timing
ISSUES IN TIMING
Digital Integrated Circuits © Prentice Hall 1995Timing
The Clock Skew Problem
CL1 R1 CL2 R2 CL3 R3In Out
t’ t’’ t’’’
tl,mintl,max
tr,mintr,max
ti
Clock Edge Timing Depends upon Position
Clock Rates as High as 500 Mhz in CMOS!
Digital Integrated Circuits © Prentice Hall 1995Timing
Delay of Clock Wire
CL
r
c
RS
r = 0.07 /q, c = 0.04 fF/m2
(Tungsten wire)
Digital Integrated Circuits © Prentice Hall 1995Timing
Constraints on Skew
R1 R2
’ ’’
tr,min + tl,min + ti
(a) Race between clock and data.
R1 R2
’ ’’+ T
tr,max + tl,max + ti
(b) Data should be stable before clock pulse is applied.
t’ t’’ = t’ +
t’ t’’ + T =
data
data
’’
t’ + T
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Constraints in Edge-Triggered Logic
tr min ti tl min+ +
T tr max ti tl max –+ +
Maximum Clock Skew Determined by Minimum Delay between Latches
Minimum Clock Period Determined by Maximum Delay between Latches
Digital Integrated Circuits © Prentice Hall 1995Timing
Positive and Negative Skew
R CL R CL RData
CL
R CL R CL RData
CL
(a) Positive skew
(b) Negative skew
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Skew in Master-Slave Two Phase Design
M1CL1 CL2 CL3In
S1 S2 S3M2
M3
’’
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Skew in 2-phase design
clock period T
T
T T T
T
1
2
1’clockoverlap
new data applied to CL2previous data latched into M2
tmin > - T12
tmax T T
Digital Integrated Circuits © Prentice Hall 1995Timing
How to counter Clock Skew?
RE
G
RE
G
RE
G
.
RE
G
log Out
In
Clock Distribution
Positive Skew
Negative Skew
Data and Clock Routing
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Distribution
CLOCK
H-Tree Network
Observe: Only Relative Skew is Important
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Network with Distributed Buffering
Module
Module
Module
Module
Module
Module
CLOCK
main clock driver
secondary clock drivers
Reduces absolute delay, and makes Power-Down easier
Sensitive to variations in Buffer Delay
Local Area
Digital Integrated Circuits © Prentice Hall 1995Timing
Example: DEC Alpha 21164
Clock Frequency: 300 MHz - 9.3 Million Transistors
Total Clock Load: 3.75 nF
Power in Clock Distribution network : 20 W (out of 50)
Uses Two Level Clock Distribution:
• Single 6-stage driver at center of chip
• Secondary buffers drive left and right sideclock grid in Metal3 and Metal4
Total driver size: 58 cm!
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Drivers
Digital Integrated Circuits © Prentice Hall 1995Timing
Clock Skew in Alpha Processor