isscc2008 nand tutorial

ISSCC 2008 Tutorial T7

NAND successful as a media for SSDNAND successful as a media for SSD

Ken TakeuchiGraduate School of Frontier Sciences

Dept. of Electronics EngineeringUniversity of Tokyoy y

E-mail : [email protected]://www.lsi.t.u-tokyo.ac.jpp y jp

1ISSCC2008 : NAND successful as a medium for SSDKen Takeuchi

Definition of SSD

SSD : Solid State DriveSSD : Solid State DriveSSD can be anything.: MP3 players Camcorders PC USB drive and: MP3 players, Camcorders, PC, USB drive and …Define SSD as a mass storage for PC application in this tutorial.SSD consists of NAND and NAND controller(+RAM)


J. Elliott, WinHEC 2007, SS-S499b_WH07.

Key Design Challenge of SSD

Need to understand of the device especially aboutNeed to understand of the device especially about the reliability such as endurance, data retention, and disturband disturb.

fRequire co-design of NAND and NAND controllers to best optimize both NAND and NAND controllers.

Also, SW support such as driver and OS essential., pp


Outline

NAND OverviewSSD OverviewSSD OverviewNAND Circuit DesignC cu t es gNAND Controller Circuit DesignOperating System for SSDSSummary


Outline



NAND Overview

NAND ArchitectureNAND Density TrendNAND Density TrendNAND Performance Trende o a ce e dNAND Operation Principle


NAND Flash Cell Array

Page : program/read unit

Bitline

Block : Erase unit

Bitline

BitlineBitline

BitlineBitline

Source-line2 Select-gate32 Word-lines

2 Select-gate32 Word-lines

Memory cells are sandwiched by select gates.Contactless structure : ideal 4F2 cell size

Ken Takeuchi ISSCC2008 : NAND successful as a medium for SSD 7

Contactless structure : ideal 4F2 cell sizeF.Masuoka, IEDM 1987, pp.552-555.

Top View of NAND Flash Cell ArrayS liSource-line(first metal)Bitline (second metal)

Active area

STI

SGDSGD SGS SGSWord-linesContact to bitline Contact to source-line

Simple structure : High scalability High yield


Simple structure : High scalability, High yieldK. Imamiya, ISSCC 1999, pp.112-113.

MLC vs. SLCSLC : Single-level cell or 1bit/cellMLC : Multi-level cell or >2bit/cell

2bit/cell : Long production record since 20013bit/cell or 4bit/cell : R&D but may be commercialized in the near future (2008?)

Existing SSD uses SLC but some manufactures announce to produce MLC based SSD.

MLC (M lti le el cell)SLC (Single level cell)

“0” “1” “2” “3”Number of memory cellsMLC (Multi-level cell)

“0” “1”Number of memory cellsSLC (Single-level cell)

Vth

0 1 2 3

Vth

0 1


VthVth

NAND Density Trend100

m2 ]

10

[MB

/mm2

55% growth / year1

ensi

ty [ 55% growth / year

0.1mor

y de

0.01

Me

1994 1996 1998 2000 2002 2004 2006

YearMLC (Multi level cell) NAND flash

ISSCC paper


SLC (Single-level cell) NAND flashMLC (Multi-level cell) NAND flash

K. Takeuchi, ISSCC 2006,pp.144-145.

NAND Program Speed Trend

10

12c] SLC (Single-level cell) NAND flash

MLC (Multi-level cell) NAND flashISSCC paper

FTTH

8

10

[MB

/sec

HDTV 60fps

5M-pixel 5photos/sec

FTTH

6

m s

peed

4M pixel 3photos/sec

2

4

Prog

ram 4M-pixel 3photos/sec

01994 1996 1998 2000 2002 2004 2006

P

MPEG2 VGA 30fpsMotion JPEG VGA 30fps

1994 1996 1998 2000 2002 2004 2006

Year

MLC performance is comparable with SLC


MLC performance is comparable with SLC.K. Takeuchi, ISSCC 2006,pp.144-145.

Chip Architecture56nm 8Gbit NAND Flash Memory



Memory Core Circuit

Page bufferPage buffer

Even & Odd bit-lines share one page buffer and are alternatively selected.

Contain two latches to store two bit data for MLC operation.



NAND Operation PrincipleReadBit-line (0.8V 0V) “0” “1”

Number of memory cells

Selected word-line(Read voltage : 0V)

Vread (4.5V)Vth

Bit-line voltage“1”

( g )

Vread (4.5V)

Read voltage

Time

“1”

“0”Vread (4.5V) Time( )0V

After precharging, bit-lines are discharged through the memory cell.

Unselected cells are biased to the pass voltage, Vread.

Small cell read current (~1uA) Slow random access (~50us)


Serial access : 30-50ns Fast read = 20-30MB/sec

NAND Operation Principle (Cont’)Program : Electron injection

18V

Channel-FN tunneling

0V0V

Channel-FN tunneling

High reliability

L t ti0V

Low current consumption

(~pA/cell)Erase : Electron ejectionPage based parallel program

Typical page size : 2-4kB0V

20V 20V

20V


20VS. Aritome, IEDM 1990, pp.111-114.

NAND Operation Principle (Cont’)P b d ll l i

Bit-line

Page based parallel programming

Page

Row

dec

Page : 2-4KBytes

P b ff

coder ・・・

Memory cell array

Page buffer

All memory cells in a page areT.Tanaka, Symp. on VLSI Circuits 1990, pp.105-106.

Page buffer

All memory cells in a page are programmed at the same time.

Program speed = Page size / Programming time

= 8KByte / 800us


= 10MByte/sec (56nm MLC) K. Takeuchi, ISSCC 2006,pp.144-145.

Outline



SSD Overview

SSD Market ProjectionSSD C t T dSSD Cost TrendSSD ReliabilitySSD ReliabilitySSD PerformanceSSD Power Consumption


SSD Market Projection

PC expected as the next killer application of NAND.

Gartner Dataquest


I. Cohen, Flash Memory Summit 2007.

Cost Trend of NAND and HDDAnal st e pectationAnalyst expectation

O B l b Fl h M S it 2007

NAND will replace HDD in PC in 2009-2012 if the cost

O. Balaban, Flash Memory Summit 2007.

continues decreasing. Unclear scaling scenario e.g. double exposure vs. EUV,


floating gate vs. MONOS, and 2D vs. 3D cell.

SSD ReliabilitySSD is robust.

No mechanical parts.But need to be careful in PC application

Portable consumer electronics applicationpp(Digital still cameras, MP3 players, Camcorders)

Effective data retention time << 10yearsEffective data retention time << 10yearsData quickly transferred to PC or DVD th h USB d i d dthrough USB drive and memory cards.Most probably data backup in PC

PC applicationHigher reliability required w.o. backup


Need longer data retention time : 5-10 years

SSD Reliability (Cont’)Failure mechanism of NAND

Program disturbDuring programming, electrons are injected to unselected memory cells.yRead disturbDuring read electrons are injected to unselectedDuring read, electrons are injected to unselectedmemory cells. W it /E d & D t t tiWrite/Erase endurance & Data retentionAs the Write/Erase cycles increase, damage of the tunnel oxide causes a leakage of stored charge.


SSD Reliability (Cont’)“Classic” program disturb

Program inhibitBi li (V )

Programi i (0 )Bitline (Vcc)

Vcc

Bitline (0V)

Vpgm(18V)Vpass(10V) Vpass disturb cell

10V

V

(10V)

Vpgm disturb cell18V

D S0VVpass(10V)0VV

D S～8VVcc


Both selected and unselected cells suffer from the disturb.K. D. Suh, ISSCC 1995, pp.128-129.

SSD Reliability (Cont’)“Modern” program disturb

J. D. Lee, NVSMW 2006, pp. 31-33.K T Park SSDM 2006 pp 298 299

Hot carriers generated at the select gate edge inject

K.T.Park, SSDM 2006, pp.298-299.

g g g jinto the memory cell causing a Vth shift.The Vth shift can be reduced by increasing SG-WL


y gspace.

SSD Reliability (Cont’)“Modern” program disturb (Cont’)

S l t T D T WL0The Vth shift can be reduced by adding dummy WL.

Select Tr. Dummy Tr. WL0


K.T.Park, SSDM 2006, pp.298-299.

SSD Reliability (Cont’)

Read disturb

4.5VVread (4.5V)

Bitline (0.8V 0V)

5

D S0V

Selected word-line(0V)

0V

Vread (4.5V)

Vread (4.5V)Weak program bias conditionUnselected word-lines suffer

0VUnselected word-lines suffer from the read disturb.


SSD Reliability (Cont’)

Program disturb and read

Program disturb and read disturb summary

Program disturb and read disturb is a “bit error” not a “burst error” X1

Page assignment of MLC

burst error .Two bits in MLC are assigned to different pages.

X1

X2

X1X2

Even if one MLC cell fails, one bit in two pages fails.

ECC(Error correcting code)2-level cell 4-level cellK Takeuchi Symp on VLSI CircuitsECC(Error correcting code)

effectively corrects the bit error.Existing ECC corrects 4 8bit errors per

K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.

Existing ECC corrects 4-8bit errors per 512Byte sector.


SSD Reliability (Cont’)Write/Erase Endurance & Data Retention

E d h ti d t ittEndurance : how many times data are writtenData retention : how long the data remains validClear correlation between endurance and dataClear correlation between endurance and data retention

Damages to the tunnel oxide during write and erase cause the data retention problems.Traps are generated during write and erase.The unlucky cell with traps results in a leakageThe unlucky cell with traps results in a leakage path, causing the charge transfer.The leakage current is called SILC (Stress I d d L k C t)

K. Prall, NVSMW 2007, pp. 5-10.

Induced Leakage Current).To guarantee data retention, Write/Erase cycles are limited to 100K (SLC) or 10K (MLC).


are limited to 100K (SLC) or 10K (MLC).

SSD Reliability (Cont’)100K (SLC) or 10K(MLC) W/E cycles acceptable?

W/E cycles estimation32GB SSDUsage scenario : 2~5GB/day (#)g yService for 5years100% efficient wear levelingg(365 days/year) x 5years / (32GB / 2~5GB/day) = 114~285 W/E cyclesy114~285 cycles are far below the NAND limitation of 100K for SLC or 10K for MLC.of 100K for SLC or 10K for MLC.Actual W/E cycles are higher for the file management such as garbage collection.


management such as garbage collection.(#) W.Akin, IDF 2007_4, MEMS003.

Y.Kim, Flash Memory Summit 2007.

SSD Performance

Random accessOS changes such as

[Data transfer size in PC application]OS changes such as directory entry and file system metadataApplication S/W change50% of data is < 4KB.R d i lRandom access mainly decides the performance of PC. K Grimsrud IDF2006 MEMS004of PC.

Sequential access

K.Grimsrud, IDF2006, MEMS004.

qBootHibernation


SSD Performance (Cont’)

Random access

Read Write Erase

NAND (SLC) 25us 300us 1ms

NAND (MLC) 50us 800us 1ms

HDD 3ms 3ms N.A.

Erase are hidden by operating the erase during the idle period.

Read : SSD with SLC and MLD has a great advantage over HDD.Write : SSD still has a performance advantage. But the write performance can be an issue in the future if the NANDperformance can be an issue in the future if the NAND performance degrades by scaling the memory cell or increasing the number of bits per cell.


p

SSD Performance (Cont’)S ti l

NAND : Single chip operation NAND : 4 chip interleaving

R d W it R d W it

Sequential access

Read Write Read Write

NAND (SLC) 25MB/sec 20MB/sec 100MB/sec 80MB/sec

NAND (MLC) 20MB/sec 10MB/sec 80MB/sec 40MB/secNAND (MLC) 20MB/sec 10MB/sec 80MB/sec 40MB/sec

HDD 80MB/sec 80MB/sec ‐ ‐

[Block diagram of SSD w interleaving function]

SSD (SLC) : Comparable read and write performance with HDD

[Block diagram of SSD w. interleaving function]

write performance with HDD.SSD (MLC) : Comparable read performance. By introducing 8chip p y g pinterleaving, the write performance can be comparable with HDD.


C. Park, NVSMW 2006, pp.17-20.

SSD Performance (Cont’)Actual performance results

[PC-mark05]

[Bootvis][Bootvis]

[Sandra]

SSD (SLC) has superior performance over HDD.

Ken Takeuchi 33

SSD (SLC) has superior performance over HDD.C. Park, NVSMW 2006, pp.17-20.

SSD Power ConsumptionPower consumption

NAND : Single chip operation NAND : 4 chip interleaving

Read Write Read Write

NAND (SLC) 20mA 20mA 80mA 80mA

NAND (MLC) 20mA 20mA 80mA 80mA

HDD >300mA >300mA ‐ ‐

A t l P C ti

In SSD, additional current (~100mA) are consumed in the NAND controller, RAM and IO.

Actual Power Consumption


In all modes the power consumption of SSD is smaller


In all modes, the power consumption of SSD is smaller than HDD.

Outline



NAND Circuit Design

Random AccessHigh Speed ProgrammingHigh Speed ProgrammingHigh Speed Read

Sequential AccessSequential AccessHigh Speed ProgrammingHi h S d R dHigh Speed Read


Random Access : High Speed Programming

f SBit-by-bit Program Verify SchemeProgram pulse

18VProgram Algorithm

0V0VData load

FN tunneling0V

Bit-lineVerify‐read

Program pulse

No

PageAll cellsprogrammed ?

Page buffer

・・・

End

Yes

During the verify-read, the program data in the page buffer is updated so that the program pulse is applied ONLY to

g


T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.

s updated so t at t e p og a pu se s app ed O toinsufficiently programmed cells.

Random Access : High Speed Programming (Cont’)

Incremental Program Voltage SchemeIncremental Program Voltage Scheme

Program voltage, Vpgm ⊿

Program pulse

Word-line waveform

increases by ⊿Vpgm.

Constant electric field across the tunnel oxide.

Verify read

g p

⊿Vpgm

across the tunnel oxide.

Tpulse Tvfy

1 cycle

# f l N l l

Constant tunnel current.

Program characteristics

Vth shift is constant at ⊿Vpgm.# of program pulses: Npulse cycles

Programming time, Tprog = (Tpulse+Tvfy)×Npulse

Achieve both fast i d ⊿Vth0

Verifyvoltage

Fastest cellSlowest cell

Vth Npulse = ⊿Vth0/⊿Vpgmg

programming and precise Vth control.

⊿Vth0 Npulse(Time)

(⊿Vth0/⊿Vpgm) cycles

g


G. Hemink, Symp. on VLSI Technologies 1995, pp.129-130.K. D. Suh, ISSCC 1995, pp.128-129.


f CProblems of MLC programming

“0” “1” “2” “3”Number of memory cells

Vth

“0” “1” “2” “3”

Vth

MLC SLCY1 Y2 Y1 Y2

4‐level cell2‐level cell

Two bits in a cell are assigned to two column addresses.

“1”-program & ”1”verify


to two column addresses.3 operations (“1”-, “2”- and “3”-program) required.


Long programming.“3”-program & ”3”verify



SSolution : Multi-page Cell Architecture

1st

Number of memory cells“0” “1”

1st page programX1

X1X2

Vth1st page data : “1” “0”

X2

2-level cell 4-level cell

Two bits in a cell are i d t t

2nd page program


assigned to two rowaddresses.In average, 1.5 operations.

Vth

“0” “1” “2” “3”

1 t d “1” “0” “0” “1” In average, 1.5 operations.Twice faster than conventional scheme.

2nd page data : “1” “0”

1st page data : “1” “0” “0” “1”


K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.


OProgram Voltage Optimization

WL0, 31 : Higher capacitive coupling with word-lines.Initial program voltage is set lower.


T. Hara, ISSCC 2005, pp. 44-45.Optimized program voltage accelerates the programming.


G G fProblems : FG-FG interference

FG FG li hift th Vth f ll thFG-FG coupling shifts the Vth of a memory cell as the neighboring cell are programmed.To tighten the Vth distribution, ⊿Vpgm is decreased,To tighten the Vth distribution, ⊿Vpgm is decreased, causing a slow programming.The Vth modulation becomes significant as the memory


J.D. Lee, EDL 2002, pp. 264-266.M. Ichige, Symp. on VLSI Technologies 2003, pp.89-90.

cell is scaled down.


S G G C CSolution : FG-FG Coupling Compensation[3-step programming] [Programming order]

Step 1

Step2Step2

Step3p

Step 1. The memory cell is ROUGHLY programmed.Step 1. The memory cell is ROUGHLY programmed.Cells are programmed BELOW the target Vth.

Step 2. Neighboring cells are programmed.Step 3 The memory cell is PRECISELY programmed

FG-FG coupling is suppressed by 90%.Large ⊿Vpgm enables a fast programming.

Step 3. The memory cell is PRECISELY programmed.


N. Shibata, Symp. on VLSI Circuits 2007, pp.190-191.

Large ⊿Vpgm enables a fast programming.

Random Access : High Speed Readf CProblems of MLC read


Vth

“0” “1” “2” “3”

VthY1 Y2 Y1 Y2

4-level cell2-level cell① ② ③

Two bits in a cell are assigned t t l dd

MLC

“1” read “1” read

SLC

① ② ③

to two column addresses.3 operations (“1”-, “2”- and “3”-read) required.

“1”-read

“2”-read

“1”-read

3 read) required.Long random read.

“3”-read


Random Access : High Speed Read (Cont’)S CSolution : Multi-page Cell Architecture


X1

X2

X1X2

Vth

“0” “1” “2” “3”

X2

2-level cell 4-level cell

Vth

2nd d t “1” “0”

1st page data : “1” “0” “0” “1”

Two bits in a cell are assigned to two row

2nd page data : “1” “0”

①② ③g

addresses.In average, 1.5 operations.

1st page read : ②, ③ EXOR

2nd page read : ① Twice faster than conventional scheme.

2 page read : ①


K. Takeuchi, Symp. on VLSI Circuits 1997, pp. 67-68.S. Lee, ISSCC 2004, pp.52-53.

Sequential Access : High Speed Programming

Parallel OperationIncrease page sizeMulti-page operationMulti-page operationMulti-chip operation (Interleaving)

T b di d i “NAND C t ll Ci it D i ” tiTo be discussed in “NAND Controller Circuit Design” section

Pipeline OperationWrite/Read CacheCache Page CopyCache Page Copy


Parallel Operation : Increase Page SizePage size trend

By increasing the word-line length, the page size has been t d d t i th it d d th h textended to increase the write and read throughput.

Bit-line4000

4500

・・・

Page

2500

3000

3500

(Byt

e)

Page buffer

1000

1500

2000

2500

Page

siz

e

0

500

1000

But, the large page size also causes problems.

0.25um 0.16um 0.13um 90nm 70nm 50nm

Design rule


Noise issue due to the large RC delay of a word-line

SG

Parallel Operation : Increase Page Size (Cont’)Problems : SG-WL noise

[Conventional read/verify-read]

Bit-line SG WL capacitive

Selected

SGD1.5V

SG-WL capacitive coupling

SelectedWL31

WL bounce

SGS

WL0

Read failureSGS

Bit-line h

Bit-line di h

Read failure


precharge dischargeK. Takeuchi, ISSCC 2006,pp.144-145.

Parallel Operation : Increase Page Size (Cont’)S l ti R i i hb i SG BEFORE bit li di hSolution : Raise neighboring SG BEFORE bit-line discharge



Parallel Operation : Increase Page Size (Cont’)Problems : WL-WL noise



Parallel Operation : Increase Page Size (Cont’)SSolution



Parallel Operation : Multi-page OperationMulti-page operation

Operate multi-page simultaneously to increase the write/read th h tthroughput.

[Multi page operation] 0 25um 256Mb NAND[Multi-page operation] 0.25um 256Mb NAND


K. Imamiya, ISSCC 1999, pp.112-113.

Pipeline Operation : Write/Read Cachef / & /Pipelining of data-in/out & cell read/write

Implement data cache in NANDI t / t t d t t th d t h d i ll d/Input /output data to the data cache during cell read/program

[Write Cache Example : 0.13um 1Gbit NAND]


H. Nakamura, ISSCC 2002, pp.106-107.Data Cache

Pipeline Operation : Cache Page CopyS f fSystem performance degradation of a large block

70nm 8G MLC [Frequent block copy]56nm 8G MLC

(ISSCC2005) (This work)Old block

(ISSCC2006)

32WLs 32WLs

New block

① Cell read

4KB page (max)512KB block 1MB block

8KB page (max)

Page buffer

③ Cell program

NAND controller

② Data-out, ECC, Data-in

System performance degradation

Fast block copy required

degradationBlock copy time = (T_Cell read+T_Data_out+TECC+T_Cell program)

×(# of pages per block)

54ISSCC2008 : NAND successful as a medium for SSD


Ken Takeuchi

Fast block copy required ×(# of pages per block)= 125ms

Pipeline Operation : Cache Page Copy (Cont’)SSolution : Fast block copy

Step1 Step2 Step3 Step4

Old blockPage i

Old block Old block

Page i+1

Old block

New blockCell Read New block New block

Cell read

Cell programNew block

NAND

Page bufferData-outECC NAND

ll

Page buffer

NAND

Page buffer

NAND

Page buffer

Data-outECC

controller controller controller controller

Step 4 : Pipelining of programming Page ip p g p g g gand data out / ECC of Page i+1.

55ISSCC2008 : NAND successful as a medium for SSD


Ken Takeuchi

Fast block copy

Outline



NAND Controller Circuit Design

HW ArchitectureSW ArchitectureHigh speed technologyHigh speed technology

Interleaving

High reliability technologyWear LevelingWear LevelingBad Block ManagementECC

SLC/MLC ComboSLC/MLC Combo57ISSCC2008 : NAND successful as a medium for SSDKen Takeuchi

HW ArchitectureBlock diagram (Single channel)

HDD-like architecture : DRAM buffer to hide NAND random accessHigh power consumptionHi h t



High cost

HW Architecture (Cont’)Block diagram (Multi-channel)

DRAM eliminated :Random access of NANDRandom access of NAND is faster than HDD.Low power consumptionp pLow costMulti-channel

Parallel operationHigh bandwidth



SW ArchitectureH t d SSD SW t tHost and SSD SW structure

Host I/F : SATA, PATA, PCIe, USB LBA BA SD MMCUSB, LBA, BA, SD, MMC…NAND I/F : Low level driver to access NAND through NAND

FTL (Flash Translation Layer)controller.

( as a s at o aye )Main part of SSD.Address translation fromAddress translation from logical address to physical address of NAND.File management such as bad block management and wear l li



leveling.

High Speed TechnologySInterleaving : Sequential Parallel Write

2-channel 4-way interleavingMax write throughput : 80MB/sec for MLC.HW d i t ti ti



HW driven automatic operation.

High Reliability Technology (Cont’)Wear-leveling

Problem W it /E l f NAND i li it d t 100K f SLC d 10KWrite/Erase cycle of NAND is limited to 100K for SLC and 10K for MLC.SolutionSolution

Write data to be evenly distributed over the entire storage.Count # of Write/Erase cycles of each NAND block.Based on the Write/Erase count, NAND controller re-map the logical address to the different physical address.W l li i d b th NAND t ll (FTL) t bWear-leveling is done by the NAND controller (FTL), not by the host system.

Bitline

Block : Erase unitBitline

Bitline

Bitline


High Reliability Technology (Cont’)

Example of wear-levelingIf the block is occupied with old data, data is programmed to a new block.If there is no free block, the invalid block are erased.

Block 1Block 2Bl k 3

Block 1Block 2Bl k 3Block 3

Block 4Block 5Block 6

Old file Block 4 InvalidBlock 3Block 4Block 5Block 6Block 6

Block 7Block 8Block 9

Rewrite old file

Block 6Block 7Block 8Block 9

New File Write new file to an empty block

Empty block


an empty block

High Reliability Technology (Cont’)

Static dataData that does not change such as system dataData that does not change such as system data (OS, application SW).D i d tDynamic dataData that are rewritten often such as user data.

Dynamic wear-levelingWear-level only over empty and dynamic data.Static wear-levelinggWear-level over all data including static data.


High Reliability Technology (Cont’)Dynamic wear-leveling

Red : Static data such as system data.Write/Erase count Blue : Dynamic data such as user data

Physical block address

Block with static data is NOT used for wear-leveling.Block with static data is NOT used for wear leveling.Write and erase concentrate on the dynamic data block.


N.Balan, MEMCON2007.SiliconSystems, SSWP02.

High Reliability Technology (Cont’)Static wear-leveling

Write/Erase count Red : Static data such as system data.Blue : Dynamic data such as user dataBlue : Dynamic data such as user data

Physical block addressWear-level more effectively than dynamic wear-leveling.Search for the least used physical block and write the data to th l ti If th t l tithe location. If that location

Is empty, the write occurs normally.Contains static data, the static data moves to a heavily


Contains static data, the static data moves to a heavily used block and then the new data is written. N.Balan, MEMCON2007.

SiliconSystems, SSWP02.

High Reliability Technology (Cont’)Bad Block Management

Program/Erase characteristics vs. endurance

A h W i /E l i f ilAs the Write/Erase cycles increases, erase failure occurs, resulting in a bad block.The NAND controller detects and isolates the bad block


The NAND controller detects and isolates the bad block.Y.R. Kim, Flash Memory Summit 2007.

High Reliability Technology (Cont’)ECC (Error Correcting Code)

To overcome read disturb, program disturb and data retention failure, ECC have to ,be applied.Since failure pattern isSince failure pattern is random, BCH is sufficient.

Existing NAND controllerExisting NAND controller can correct 4-8bit error per 512Byte sector.

NAND with embedded ECC is


also published. R. Micheloni, ISSCC2006, pp.142-143.

MLC/SLC ComboFuture Direction : Hybrid SSD with SLC and MLC

Concept : Right device for the right use.Enjoy the Benefit of both SLC and MLC.SLC : Fast and highly reliable but low capacity.

Use SLC as a cache or system data storageUse SLC as a cache or system data storage.MLC : Large capacity but slow. Use MLC as user data storage.

Toshiba LBA-NANDhttp://www1 toshiba com/taec/index jsp

MLC(Multi Level Cell) SATA-III

56/112/224/336/448GB

SATA-II16/32/48/64/96/128GB

SATA-II32/48/64/128/256GB

SATA-III 48/64/128/256/512GB

Samsung Combo SSD J. Elliott, WinHEC2007. http://www1.toshiba.com/taec/index.jsp

Combo(SLC+MLC)

SATA-II16/32/64/96/128GB

SATA-II14/28/56/84/112GB

SATA-III32/64/128/192/256GB

SATA-II28/56/112/168/224GB

Spansion MirroBit Eclipsehttp://www.spansion.com/products/MirrorBit_Eclipse.html

PATA4/8/16/32GB

SATA-I8/16/32/48/64GB

SATA-II8/16/32/48/64GB

(SLC+MLC)

SLC(Single Level Cell)

57/32 64/45 100/80 160/160 800/800 1300/1300R/W Speed:


2006 20102007 2008 2009

Outline



Operating System for SSD

Performance OptimizationSector Size OptimizationSector Size Optimization

Reliability OptimizationEWF (E h d W it Filt )EWF (Enhanced Write Filter)SMART (Self-Monitoring, Analysis and Reporting Technology)


Future Perspective

Motivation

Existing OS is optimized for magnetic drives.Current SSD based PC uses the conventional OS and just replace HDD with SSD.j pTo achieve the best performance and reliability of SSD OS especially file systemreliability of SSD, OS especially file system should be optimized.


Performance OptimizationSector size optimization

Minimum write/read unit of NAND is a page.Typical page size is 4-8KByte.A page is written only ONCE to avoid the program disturbance

Pageprogram disturbance.With current OS having 512Byte sector , one sector write wastes >80% of data in a page.p g

1 sector ・・・

Remaining portion

LBD(Long Block Data) sector standard : 4KByte sector size fits better with SSD

writeg p

becomes garbage.

4KByte sector size fits better with SSD.Considering the page size increases as NAND is shrinking, larger sector size such as


g g16KByte or 32KByte is preferred.

Reliability OptimizationEnhanced Write Filter (Windows Embedded)

Control the file allocation to store frequently rewritten file in DRAM and not to access NAND.D it / l f NAND t di th NANDDecrease write/erase cycles of NAND, extending the NAND lifetime.Enhanced Write Filter (EWF) is located between file systemEnhanced Write Filter (EWF) is located between file system and low level driver interfacing with SSD.

SSD

Enhance Write FilterApplication

SSD

File System Low-level Driver


http://msdn2.microsoft.com/en-us/library/ms912909.aspx

Reliability Optimization (Cont’)SMART (Self-Monitoring, Analysis and Reporting Technology)

Monitor the storage and report/predict the failure.SMART for HDD is NOT smart because it is very difficult to predict the mechanical failure.(Google report http://209 85 163 132/papers/disk failures pdf)(Google report, http://209.85.163.132/papers/disk_failures.pdf)

SMART for SSD can be really smart.Product lifetime can be predicted because the failure rate is highly correlated with the write/erase cycles.

P di t th SSD lif ti b it i th it /Predict the SSD lifetime by monitoring the write/erase cycles and replace SSD before the fatal failure occurs.


http://www.tdk.co.jp/tefe02/ew_007.pdf

Outline



SummaryMarket & Cost : NAND will replace HDD in PC in 2009-2012.

Key issue : Is scaling sustainable?Unclear scaling scenario e.g. double exposure vs. EUV, floating gate vs MONOS and 2D vs 3D cellfloating gate vs. MONOS, and 2D vs. 3D cell.

MLC is a MUST for the cost reduction.Existing 2bit/cell satisfies performance, reliability and power consumption requirements.

>2bit/cell or scaled MLC may face performance/reliability challengeschallenges.

Key breakthrough of NAND circuit or NAND controller circuit such as SLC/MLC Combo required.Optimization of OS will also help.


Th k !Thank you!

E-mail : [email protected]://www.lsi.t.u-tokyo.ac.jpp y jp


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• K. Imamiya, Y. Sugiura, H. Nakamura, T. Himeno, K. Takeuchi, T. Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K. Shimizu, K. Hatakeyama and K. Sakui “ A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology”, ISSCC Digest of Technical Papers , 1999, pp.112-113.

• K. Takeuchi, Y. Kameda, S. Fujimura, H. Otake, K. Hosono, H. Shiga, Y. Watanabe, T. Futatsuyama, Y. Shindo, M. Kojima, M. Iwai, M. Shirakawa, M. Ichige, K. Hatakeyama, S. Tanaka, T. Kamei, J.Y. Fu, A. Cernea, Y. Li, M. Higashitani, G. Hemink, S. Sato, K. Oowada, S.C. Lee, N. Hayashida, J. Wan, J. Lutze, S. Tsao, M. Mofidi, K. Sakurai, N. Tokiwa, H. Waki, Y. Nozawa, K. Kanazawa and S. Ohshima, “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10Mbyte/sec Program Throughput,” in International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, February, 2006, pp.144-Throughput, in International Solid State Circuits Conference (ISSCC) Digest of Technical Papers, February, 2006, pp.144145.

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• T. Tanaka, M. Momodomi, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi and F. Masuoka, “A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution ” in Symp VLSI Circuits Dig Tech Papers June 1990 pp 105 106EEPROM with Tight Programmed Vt Distribution, in Symp. VLSI Circuits Dig. Tech. Papers, June 1990, pp.105-106.

• J. Elliott, “SSD:The Next Wave In NAND Flash”WinHEC 2007,” WinHEC, 2007, SS-S499b_WH07.• I. Cohen, “Is There a Killer Application for Flash Memory,” Flash Memory Summit, 2007.• O. Balaban, “Bringing Solid State Drives to Mainstream Notebooks,” Flash Memory Summit, 2007.• Kang-Deog Suh, Byung-Hoon Suh, Young-Ho Um, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung-Soo Lee, Suk-Chon

Kwon, Byung-Soon Choi, Jin-Sun Yum, Jung-Hyuk Choi, Jang-Rae Kim and Hyung-Kyu Lim, “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme”, in ISSCC Digest of Technical Papers, Feb., 1995, pp.128-129.

• Jae-Duk Lee, Chi-Kyung Lee, Myung-Won Lee, Han-Soo Kim, Kyu-Charn Park and Won-Seong Lee,”A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current,” in Non-volatile Semiconductor Memory Workshop (NVSMW) Dig. Tech. Papers, 2006, pp. 31-33.y p ( ) g p , , pp

• K. T. Park, S. C. Lee, J. Sel, J. Choi and K. Kim, “Scalable Wordline Shielding Scheme using Dummy Cell beyond 40nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell,” in International Conference on Solid State Devices and Materials (SSDM) Dig. Tech. Papers, 2006, pp.298-299.

• K. Takeuchi, T. Tanaka and T. Tazawa, “A multi-page cell architecture for high-speed programming multi-level NAND flash memories ” in Symp VLSI Circuits Dig Tech Papers June 1997 pp 67 68


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References (Cont’)• W. Akin, ”SSDs for IA Segments,” Intel Developer Forum (IDF), 2007, April, MEMS003.• Y. Kim, Flash Memory Summit 2007, “Solid State Drives Moving into Design,” Flash Memory Summit, 2007. • K. Grimsrud and R. Coulson, “Platform NV Memory Solutions for Storage Enhancement,” ,” Intel Developer Forum (IDF),

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• T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodaira, S. Aritome, R. Shirota and F. Masuoka, "A quick intelligent program architecture for 3V-only NAND EEPROMs," Symp. VLSI Circuits Dig. Tech. Papers, June 1992, pp.20-21.G J H i k T T k T E d h S A it d R Shi t “F t d t i th d f lti l l NAND• G.J.Hemink, T.Tanaka, T.Endoh, S.Aritome and R.Shirota, “Fast and accurate programming method for multi-level NAND flash EEPROM’s”, in Symp. VLSI Technology Dig. Tech. Papers, June 1995, pp.129-130.

• T.Hara, K.Fukuda, K.Kanazawa, N.Shibata, K.Hosono, H.Maejima, M.Nakagawa, T.Abe, M.Kojima, M.Fujiu, Y.Takeuchi, K.Amemiya, M.Morooka, T.Kamai, H.Nasu, K.Kawano, C.M.Wang, K.Sakurai, N.Tokiwa, H.Waki, T.Maruyama, S.Yoshikawa, M.Higashitani, T.D.Pham and T.Watanabe, “A 146mm2 8Gb NAND flash memory with 70nm COMS technology”, in ISSCC Digest of Technical Papers, 2005, pp.44-45.

• Jae-Duk Lee, Sung-Hoi Hur and Jung-Dal Choi, “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation,” Electron Device Letters, vol. 23, no. 5, 2002, pp. 264-266.

• M. Ichige, Y. Takeuchi, K. Sugimae, A. Sato, M. Matsui, T. Kamigaichi, H. Kutsukake, Y. Ishibashi, M. Saito, S. Mori, H. Meguro S Miyazaki T Miwa S Takahashi T Iguchi N Kawai S Tamon N Arai H Kamata T Minami H Iizuka MMeguro, S. Miyazaki, T. Miwa, S. Takahashi, T. Iguchi, N. Kawai, S. Tamon, N. Arai, H. Kamata, T. Minami, H. Iizuka, M. Higashitani, T. Pham, G. Hemink, M. Momodomi and R. Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. on VLSI Technologies Dig. Tech. Papers, 2003, pp.89-90.

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• Seungjae Lee, Young-Taek Lee, Wook-Kee Han, Dong-Hwan Kim, Moo-Sung Kim, Seung-Hyun Moon, Hyun Chul Cho, Jung-Woo Lee, Dae-Seok Byeon, Young-Ho Lim, Hyung-Suk Kim, Sung-Hoi Hur and Kang-Deog Suh,” A 3.3 V 4 Gb four-


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Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader and J.Chen, “A 125mm2 1Gb NAND Flash Memory with 10MB/s Program Throughput,” ISSCC Digest of Technical Papers, 2002, pp.106-107.

• N Balan “MLC NAND Flash Memory Systems: Understanding Hardware and Software Solutions ” MEMCON 2007N. Balan, MLC NAND Flash Memory Systems: Understanding Hardware and Software Solutions, MEMCON, 2007.• SiliconSystems, SSWP02.• R. Micheloni, R. Ravasio, A. Marelli, E. Alice, V. Altieri, A. Bovino, L. Crippa, E. Di Martino, L. D’Onofrio, A. Gambardella, E.

Grillea,G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone,M. Romano, M. Sangalli, P. Sauro, M. Scotti, and S. Won, “A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput”, ISSCC 2006 142 1432006, pp.142-143.

• http://www1.toshiba.com/taec/index.jsp• http://www.spansion.com/products/MirrorBit_Eclipse.html• http://msdn2.microsoft.com/en-us/library/ms912909.aspx• http://209.85.163.132/papers/disk_failures.pdf• http://www.tdk.co.jp/tefe02/ew_007.pdf


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