1142 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

Highly Scalable Horizontal Channel 3-D NANDMemory Excellent in Compatibility With

Conventional Fabrication TechnologyKiwamu Sakuma, Haruka Kusai, Shosuke Fujii, and Masato Koyama

Abstract We developed a stacked horizontal channel typefloating gate (HC-FG) NAND memory; a 3-D stacked NAND arraycomposed of conventional FG cells. With this cell structure, awide program/erase (P/E) window is obtained, accompanied bysuperior read disturb immunity, P/E endurance, and data reten-tion. In addition, we propose a low-cost layer select transistor(LST) that is easily integrated with the HC-FG cell. Because the3-D memory composed of the HC-FG cell and the LST has goodcompatibility with conventional fabrication technology, furtherbit cost scaling is expected.

Index Terms 3-D NAND Flash memory, floating gate (FG)cell, stacked horizontal channel.

I. INTRODUCTION

FLOATING gate (FG) type NAND Flash has been usedin many memory products. In addition, the demand forhigh density and low cost has been satisfied by the reductionof cell size and by increasing the number of memory levelsin a cell. Recently, prompted by the limits of reduction ofcell size, 3-D memory devices have been proposed [1][5].In addition, 3-D NAND devices with FG-type cells, such asdual control gate-surrounding FG [2] and sidewall controlpillar [3], have been suggested. The cell size of these structuresis, however, large owing to the gate-all-around (GAA) typestructure with FG. Their split-gate type structure complicatesthe cell operation.

In this letter, we propose a 3-D memory structure witha conventional FG cell. Compared with the 3-D FG typestructures reported so far, horizontal channel type FG(HC-FG) structure has higher compatibility with the current2-D FG structure in terms of fabrication process and operationschemes. Furthermore, we introduce a lower cost layer selec-tive structure that can be formed using a self-aligned processand demonstrate its operation.

II. DEVICE ARCHITECTURE

Fig. 1 shows a schematic birds eye view and the equiva-lent circuit of the HC-FG NAND structure. Stacked memory

Manuscript received June 11, 2013; revised July 10, 2013; accepted July 18,2013. Date of publication August 2, 2013; date of current version August 21,2013. The review of this letter was arranged by Editor T. San.

The authors are with the Corporate Research and Development Cen-ter, Toshiba Corporation, Kawasaki 212-8582, Japan (e-mail: kiwamu.sakuma@toshiba.co.jp).

Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2013.2274472

Fig. 1. (a) Birds eye view of HC-FG NAND structure. (b) Equivalent circuit.

Fig. 2. Schematic view of HC-FG NAND cells.

strings are connected in common to twisted-layout layer selecttransistor (LST) through stacked string select line (SSL), andshared the gate electrode for word lines (WLs) and othertransistors.

III. HC-FG NAND CELL

Fig. 2 shows a schematic view of the HC-FG NANDcell. Cells with the conventional FG structure are stackedperpendicular to the substrate. In this structure, FG mustbe separated between adjacent cells to avoid short circuit.Process flow of HC-FG NAND stacked cell is shown in Fig. 3.As shown in Fig. 3, stacked FG cell is formed by channel-firstprocess similar to that of the 2-D FG cell.

Fig. 4(a) shows an annular dark-field scanning transmis-sion electron microscope (ADF-STEM) image along WLdirection of HC-FG NAND stacked cells. Four NAND stringswith double-gate structure are stacked perpendicular to thesubstrate. Furthermore, it is clearly observed that conventionalFG type structure is well fabricated from the bright-fieldSTEM (BF-STEM) image of the cell shown in Fig. 4(b).Because FG is formed on the recessed Si region, FGs canbe formed in self-alignment with respect to stacked channels.The SEM image along bit line (BL) direction of the HC-FGNAND structure is shown in Fig. 4(c). WLs with 1-m height

0741-3106 2013 IEEE

SAKUMA et al.: HIGHLY SCALABLE HORIZONTAL CHANNEL 3-D NAND MEMORY 1143

Fig. 3. Process flow of HC-FG NAND cells. (a) SiO2/Si layers and hardmask deposition, (b) line/space etch, (c) Si recess, (d) fill the space by FG,(e) Si etch to separate adjacent FGs, (f) hard mask and SiO2 recess to divideFG at WL etch, and (g) deposition of IPD and CG.

T op view a fte r W L e tch

W L length 100nm 1m

W L

C hanne l S i

T unne l O x.

FG

IP D

C G

(b)

18nm

(c)

(a)

4 th FG ce ll

3 rd FG ce ll

2 nd FG ce ll

1 st FG ce ll

30nm

50nm

T op view a fte r W L e tch

W L length 100nm 1m

W L

C hanne l S i

T unne l O x.

FG

IP D

C G

(b)

18nm

(c)

(a)

4 th FG ce ll

3 rd FG ce ll

2 nd FG ce ll

1 st FG ce ll

30nm

50nm

Fig. 4. (a) ADF-STEM image along WL direction of HC-FG NAND stackedcells with channel height of 18 nm. (b) BF-STEM image of the cell. (c) SEMimage along BL direction of HC-FG NAND structure.

are formed. Because the adjacent FGs must be separated fromone another, a hard mask was recessed to the end side of achannel before WL etching, as shown in Fig. 3(f).

Program/erase (P/E) operation in the HC-FG NAND cell canbe carried out at the same voltage conditions as for 2-D FGcell. Here, applying a voltage to the SSL and LST allows BLbias to be transferred to the selected (or nonselected) memorystrings channel. Fig. 5 shows the cell characteristics of theHC-FG NAND cell with channel height of 70 nm. The P/Espeed is shown in Fig. 5(a). V th window after P/E operation isover 7 V, which is wide enough for multilevel operation. Readdisturb is measured as a function of read voltages in Fig. 5(b).The threshold voltage shift (Vth) is

1144 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

Fig. 7. Cross-sectional (a) SEM image along BL direction of LST structureand (b) SSRM image of stacked BLs [dashed line in Fig. 6(a)]. (c) Id Vgcharacteristics of stacked BLs with LST. The amount of current depends onthe number of BLs selected by LST. Solid line: sum of the currents flowingalong each layer.

TABLE I

COMPARISON OF 3-D FG TYPE MEMORY STRUCTURE

using normally-on SSL [5]. The overlap is dependent on theannealing temperature and time. Therefore, when the thermalbudget increases, it is necessary to extend the length of theLST gate in accordance with the amount of overlap region.In addition, the number of the LST gate increases withincreasing the number of the stacked BLs. Twisted layoutshown in Fig. 1(a) can, however, keep memory string lengthconstant regardless of the LST string length.

Fig. 7(c) shows the Id Vg characteristics of stacked BLswith LST structure, as shown in Fig. 7(a); two LSTs (Gate 1and Gate 2) and one normal transistor without normally-onregion (Gate 3). This figure shows that the amount of currentdepends on the number of BLs selected by LST. As describedabove, using a stair-like shape, impurity regions can be formedin the target position in a self-aligned manner. These resultsshow that the LST structure can be formed by an easy processat low cost.

V. CONCLUSION

We have successfully demonstrated a stacked FG Flashmemory array employing HC-FG technology. HC-FG NAND

Fig. 8. 2-D FG equivalent half pitch for various FG structure.

cell has higher compatibility with 2-D FG, and has goodcharacteristics suitable for multilevel operation. HC-FG NANDcan reduce the cell size more than GAA type 3-D structure,as shown in Table I and Fig. 8. Furthermore, we have demon-strated a low-cost LST structure that can be formed using aself-aligned process. In combination with twisted-layout LSTstructure, reduction in chip size of the HC-FG NAND canbe achieved even when the number of stacked cells is large.HC-FG NAND is a more realistic technology for low-cost andultrahigh density NAND memory.

ACKNOWLEDGMENT

The authors would like to thank L. Zhang, T. Muraoka,M. Shingu, and M. Kiyotoshi for their support.

REFERENCES

[1] R. Katsumata, M. Kito, Y. Fukuzumi, et al., Pipe-shaped BiCS flashmemory with 16 stacked layers and multi-level-cell operation for ultrahigh density storage devices, in Proc. Symp. VLSI Technol., 2009,pp. 136137.

[2] S. J. Whang, K. H. Lee, D. G. Shin, et al., Novel 3-D dualcontrol-gate with surrounding floating-gate (DC-SF) NAND flashcell for 1Tb file storage application, in IEDM Tech. Dig., 2010,pp. 668669.

[3] M. S. Seo, J. M. Choi, S. K. Park, et al., Highly scalable 3-D verticalFG NAND cell arrays using the sidewall control pillar (SCP), in Proc.4th IEEE IMW, May 2012, pp. 14.

[4] C. H. Hung, H. T. Lue, K. P. Chang, et al., A highly scalable verticalgate (VG) 3D NAND flash with robust program disturb immunity usinga novel pn diode decoding structure, in Proc. Symp. Technol. VLSI,2011, pp. 6869.

[5] W. Kim, S. Choi, J. Sung, et al., Multi-layered vertical gate NANDflash overcoming stacking limit for terabit density storage, in Proc.Symp. Technol. VLSI, 2009, pp. 188189.

[6] L. Zhang, K. Ohuchi, K. Adachi, et al., High-resolution characteriza-tion of ultrashallow junctions by measuring in vacuum with scanningspreading resistance microscopy, Appl. Phys. Lett., vol. 90, nos. 13,pp. 192103-1192103-3, May 2007.

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